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Commit f5dcb6ae authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
Browse files

Merge changes Ia1717b58,I46be9843,I38069105,Id065b8ad,I617fb0ef,I16ef1e31 into msm-4.14 

* changes:
  clk: qcom: mdss: update PLL programming for DisplayPort on SDM855
  clk: qcom: msm: update the DisplayPort clocks for SDM855
  drm/msm/dp: update the AUX setup sequence for DP PHY on SDM855
  drivers: soc: qcom: fix FSA4480 settings for DisplayPort orientation
  ARM: dts: msm: update the DisplayPort device node for SDM855
  drm/msm/dp: fix parsing of AUX switch device node
parents 5312d79e 35c3882c

arch/arm64/boot/dts/qcom/sdm855-sde.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -610,7 +610,7 @@ 
		cell-index = <0>;

		compatible = "qcom,dp-display";



		vdda-1p2-supply = <&pm855_l3>;

		vdda-1p2-supply = <&pm855l_l3>;

		vdda-0p9-supply = <&pm855_l5>;



		reg =	<0xae90000 0x0dc>,
@@ -622,7 +622,7 @@ 
			<0x88ea600 0x200>,

			<0xaf02000 0x1a0>,

			<0x780000 0x621c>,

			<0x88ea030 0x10>,

			<0x88ea040 0x10>,

			<0x88e8000 0x20>,

			<0x0aee1000 0x034>,

			<0xae91000 0x094>;
@@ -659,14 +659,14 @@ 


		qcom,phy-version = <0x420>;

		qcom,aux-cfg0-settings = [20 00];

		qcom,aux-cfg1-settings = [24 00];

		qcom,aux-cfg2-settings = [28 04];

		qcom,aux-cfg1-settings = [24 13];

		qcom,aux-cfg2-settings = [28 24];

		qcom,aux-cfg3-settings = [2c 10];

		qcom,aux-cfg4-settings = [30 0a];

		qcom,aux-cfg5-settings = [34 26];

		qcom,aux-cfg6-settings = [38 0a];

		qcom,aux-cfg7-settings = [3c 03];

		qcom,aux-cfg8-settings = [40 8b];

		qcom,aux-cfg8-settings = [40 bb];

		qcom,aux-cfg9-settings = [44 03];



		qcom,max-pclk-frequency-khz = <675000>;

drivers/clk/qcom/dispcc-sdm855.c

+36 −32
Original line number Diff line number Diff line
@@ -75,8 +75,8 @@ static const struct parent_map disp_cc_parent_map_0[] = { 


static const char * const disp_cc_parent_names_0[] = {

	"bi_tcxo",

	"dp_phy_pll_link_clk",

	"dp_phy_pll_vco_div_clk",

	"dp_link_clk_divsel_ten",

	"dp_vco_divided_clk_src_mux",

	"dptx1_phy_pll_link_clk",

	"dptx1_phy_pll_vco_div_clk",

	"dptx2_phy_pll_link_clk",
@@ -351,10 +351,10 @@ static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { 
};



static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto1_clk_src[] = {

	F( 12800000, P_BI_TCXO, 1.5, 0, 0),

	F( 180000000, P_DP_PHY_PLL_LINK_CLK,   1.5,   0,   0),

	F( 360000000, P_DP_PHY_PLL_LINK_CLK,   1.5,   0,   0),

	F( 540000000, P_DP_PHY_PLL_LINK_CLK,   1.5,   0,   0),

	F( 108000, P_DP_PHY_PLL_LINK_CLK,   3,   0,   0),

	F( 180000, P_DP_PHY_PLL_LINK_CLK,   3,   0,   0),

	F( 360000, P_DP_PHY_PLL_LINK_CLK,   3,   0,   0),

	F( 540000, P_DP_PHY_PLL_LINK_CLK,   3,   0,   0),

	{ }

};
@@ -373,10 +373,11 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto1_clk_src = { 
		.vdd_class = &vdd_mm,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 12800000,

			[VDD_LOWER] = 180000000,

			[VDD_LOW_L1] = 360000000,

			[VDD_NOMINAL] = 540000000},

			[VDD_MIN] = 12800,

			[VDD_LOWER] = 108000,

			[VDD_LOW] = 180000,

			[VDD_LOW_L1] = 360000,

			[VDD_NOMINAL] = 540000},

	},

};
@@ -395,18 +396,19 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { 
		.vdd_class = &vdd_mm,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 12800000,

			[VDD_LOWER] = 180000000,

			[VDD_LOW_L1] = 360000000,

			[VDD_NOMINAL] = 540000000},

			[VDD_MIN] = 12800,

			[VDD_LOWER] = 108000,

			[VDD_LOW] = 180000,

			[VDD_LOW_L1] = 360000,

			[VDD_NOMINAL] = 540000},

	},

};



static const struct freq_tbl ftbl_disp_cc_mdss_dp_link1_clk_src[] = {

	F( 19200000, P_BI_TCXO, 1, 0, 0),

	F( 270000000, P_DP_PHY_PLL_LINK_CLK,   1,   0,   0),

	F( 540000000, P_DP_PHY_PLL_LINK_CLK,   1,   0,   0),

	F( 810000000, P_DP_PHY_PLL_LINK_CLK,   1,   0,   0),

	F( 162000, P_DP_PHY_PLL_LINK_CLK,   1,   0,   0),

	F( 270000, P_DP_PHY_PLL_LINK_CLK,   1,   0,   0),

	F( 540000, P_DP_PHY_PLL_LINK_CLK,   1,   0,   0),

	F( 810000, P_DP_PHY_PLL_LINK_CLK,   1,   0,   0),

	{ }

};
@@ -425,10 +427,11 @@ static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = { 
		.vdd_class = &vdd_mm,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 19200000,

			[VDD_LOWER] = 270000000,

			[VDD_LOW_L1] = 540000000,

			[VDD_NOMINAL] = 810000000},

			[VDD_MIN] = 19200,

			[VDD_LOWER] = 162000,

			[VDD_LOW] = 270000,

			[VDD_LOW_L1] = 540000,

			[VDD_NOMINAL] = 810000},

	},

};
@@ -447,10 +450,11 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { 
		.vdd_class = &vdd_mm,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 19200000,

			[VDD_LOWER] = 270000000,

			[VDD_LOW_L1] = 540000000,

			[VDD_NOMINAL] = 810000000},

			[VDD_MIN] = 19200,

			[VDD_LOWER] = 162000,

			[VDD_LOW] = 270000,

			[VDD_LOW_L1] = 540000,

			[VDD_NOMINAL] = 810000},

	},

};
@@ -488,9 +492,9 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src = { 
		.vdd_class = &vdd_mm,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 19200000,

			[VDD_LOWER] = 337500000,

			[VDD_LOW_L1] = 675000000},

			[VDD_MIN] = 19200,

			[VDD_LOWER] = 337500,

			[VDD_LOW_L1] = 675000},

	},

};
@@ -508,9 +512,9 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { 
		.vdd_class = &vdd_mm,

		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 19200000,

			[VDD_LOWER] = 337500000,

			[VDD_LOW_L1] = 675000000},

			[VDD_MIN] = 19200,

			[VDD_LOWER] = 337500,

			[VDD_LOW_L1] = 675000},

	},

};

drivers/clk/qcom/mdss/mdss-dp-pll-7nm-util.c

+41 −44
Original line number Diff line number Diff line
@@ -11,7 +11,7 @@ 
 *

 */



#define pr_fmt(fmt)	"%s: " fmt, __func__

#define pr_fmt(fmt)	"[dp-pll] %s: " fmt, __func__



#include <linux/kernel.h>

#include <linux/err.h>
@@ -134,7 +134,7 @@ int dp_mux_set_parent_7nm(void *context, unsigned int reg, unsigned int val) 
	MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_VCO_DIV, auxclk_div);

	/* Make sure the PHY registers writes are done */

	wmb();

	pr_debug("%s: mux=%d auxclk_div=%x\n", __func__, val, auxclk_div);

	pr_debug("mux=%d auxclk_div=%x\n", val, auxclk_div);



	mdss_pll_resource_enable(dp_res, false);
@@ -170,7 +170,7 @@ int dp_mux_get_parent_7nm(void *context, unsigned int reg, unsigned int *val) 


	mdss_pll_resource_enable(dp_res, false);



	pr_debug("%s: auxclk_div=%d, val=%d\n", __func__, auxclk_div, *val);

	pr_debug("auxclk_div=%d, val=%d\n", auxclk_div, *val);



	return 0;

}
@@ -185,18 +185,19 @@ static int dp_vco_pll_init_db_7nm(struct dp_pll_db_7nm *pdb, 
	pdb->lane_cnt = spare_value & 0x0F;

	pdb->orientation = (spare_value & 0xF0) >> 4;



	pr_debug("%s: spare_value=0x%x, ln_cnt=0x%x, orientation=0x%x\n",

			__func__, spare_value, pdb->lane_cnt, pdb->orientation);

	pr_debug("spare_value=0x%x, ln_cnt=0x%x, orientation=0x%x\n",

			spare_value, pdb->lane_cnt, pdb->orientation);



	pdb->div_frac_start1_mode0 = 0x00;

	pdb->integloop_gain0_mode0 = 0x3f;

	pdb->integloop_gain1_mode0 = 0x00;

	pdb->vco_tune_map = 0x00;

	pdb->cmn_config = 0x02;

	pdb->txn_tran_drv_emp_en = 0xf;



	switch (rate) {

	case DP_VCO_HSCLK_RATE_1620MHZDIV1000:

		pr_debug("%s: VCO rate: %ld\n", __func__,

				DP_VCO_RATE_9720MHZDIV1000);

		pr_debug("VCO rate: %ld\n", DP_VCO_RATE_9720MHZDIV1000);

		pdb->hsclk_sel = 0x05;

		pdb->dec_start_mode0 = 0x69;

		pdb->div_frac_start2_mode0 = 0x80;
@@ -205,12 +206,9 @@ static int dp_vco_pll_init_db_7nm(struct dp_pll_db_7nm *pdb, 
		pdb->lock_cmp2_mode0 = 0x08;

		pdb->phy_vco_div = 0x1;

		pdb->lock_cmp_en = 0x04;

		pdb->cmn_config = 0x42;

		pdb->txn_tran_drv_emp_en = 0xf;

		break;

	case DP_VCO_HSCLK_RATE_2700MHZDIV1000:

		pr_debug("%s: VCO rate: %ld\n", __func__,

				DP_VCO_RATE_10800MHZDIV1000);

		pr_debug("VCO rate: %ld\n", DP_VCO_RATE_10800MHZDIV1000);

		pdb->hsclk_sel = 0x03;

		pdb->dec_start_mode0 = 0x69;

		pdb->div_frac_start2_mode0 = 0x80;
@@ -219,12 +217,9 @@ static int dp_vco_pll_init_db_7nm(struct dp_pll_db_7nm *pdb, 
		pdb->lock_cmp2_mode0 = 0x0e;

		pdb->phy_vco_div = 0x1;

		pdb->lock_cmp_en = 0x08;

		pdb->cmn_config = 0x02;

		pdb->txn_tran_drv_emp_en = 0xf;

		break;

	case DP_VCO_HSCLK_RATE_5400MHZDIV1000:

		pr_debug("%s: VCO rate: %ld\n", __func__,

				DP_VCO_RATE_10800MHZDIV1000);

		pr_debug("VCO rate: %ld\n", DP_VCO_RATE_10800MHZDIV1000);

		pdb->hsclk_sel = 0x01;

		pdb->dec_start_mode0 = 0x8c;

		pdb->div_frac_start2_mode0 = 0x00;
@@ -233,12 +228,9 @@ static int dp_vco_pll_init_db_7nm(struct dp_pll_db_7nm *pdb, 
		pdb->lock_cmp2_mode0 = 0x1c;

		pdb->phy_vco_div = 0x2;

		pdb->lock_cmp_en = 0x08;

		pdb->cmn_config = 0x12;

		pdb->txn_tran_drv_emp_en = 0xf;

		break;

	case DP_VCO_HSCLK_RATE_8100MHZDIV1000:

		pr_debug("%s: VCO rate: %ld\n", __func__,

				DP_VCO_RATE_8100MHZDIV1000);

		pr_debug("VCO rate: %ld\n", DP_VCO_RATE_8100MHZDIV1000);

		pdb->hsclk_sel = 0x00;

		pdb->dec_start_mode0 = 0x69;

		pdb->div_frac_start2_mode0 = 0x80;
@@ -247,8 +239,6 @@ static int dp_vco_pll_init_db_7nm(struct dp_pll_db_7nm *pdb, 
		pdb->lock_cmp2_mode0 = 0x2a;

		pdb->phy_vco_div = 0x0;

		pdb->lock_cmp_en = 0x08;

		pdb->cmn_config = 0x02;

		pdb->txn_tran_drv_emp_en = 0x3;

		break;

	default:

		pr_err("unsupported rate %ld\n", rate);
@@ -282,7 +272,7 @@ static int dp_config_vco_rate_7nm(struct dp_pll_vco_clk *vco, 
	/* Make sure the PHY register writes are done */

	wmb();



	MDSS_PLL_REG_W(dp_res->pll_base, QSERDES_COM_SVS_MODE_CLK_SEL, 0x01);

	MDSS_PLL_REG_W(dp_res->pll_base, QSERDES_COM_SVS_MODE_CLK_SEL, 0x05);

	MDSS_PLL_REG_W(dp_res->pll_base, QSERDES_COM_SYSCLK_EN_SEL, 0x3b);

	MDSS_PLL_REG_W(dp_res->pll_base, QSERDES_COM_SYS_CLK_CTRL, 0x02);

	MDSS_PLL_REG_W(dp_res->pll_base, QSERDES_COM_CLK_ENABLE1, 0x0c);
@@ -322,11 +312,14 @@ static int dp_config_vco_rate_7nm(struct dp_pll_vco_clk *vco, 
	MDSS_PLL_REG_W(dp_res->pll_base, QSERDES_COM_BG_TIMER, 0x0a);

	MDSS_PLL_REG_W(dp_res->pll_base, QSERDES_COM_CORECLK_DIV_MODE0, 0x0a);

	MDSS_PLL_REG_W(dp_res->pll_base, QSERDES_COM_VCO_TUNE_CTRL, 0x00);

	MDSS_PLL_REG_W(dp_res->pll_base, QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3d);

	MDSS_PLL_REG_W(dp_res->pll_base, QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1d);

	MDSS_PLL_REG_W(dp_res->pll_base, QSERDES_COM_CORE_CLK_EN, 0x1f);

	/* Make sure the PHY register writes are done */

	wmb();



	if (pdb->orientation == ORIENTATION_CC2)

		MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_MODE, 0x4c);

	else

		MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_MODE, 0x5c);

	/* Make sure the PLL register writes are done */

	wmb();
@@ -441,7 +434,7 @@ static int dp_pll_enable_7nm(struct clk_hw *hw) 
		goto lock_err;

	}



	pr_debug("%s: PLL is locked\n", __func__);

	pr_debug("PLL is locked\n");



	if (pdb->lane_cnt == 1) {

		bias_en = 0x3e;
@@ -640,7 +633,7 @@ unsigned long dp_vco_recalc_rate_7nm(struct clk_hw *hw, 
{

	struct dp_pll_vco_clk *vco;

	int rc;

	u32 div, hsclk_div, link_clk_div = 0;

	u32 hsclk_sel, link_clk_divsel, hsclk_div, link_clk_div = 0;

	unsigned long vco_rate;

	struct mdss_pll_resources *dp_res;
@@ -658,40 +651,43 @@ unsigned long dp_vco_recalc_rate_7nm(struct clk_hw *hw, 
		return 0;

	}



	div = MDSS_PLL_REG_R(dp_res->pll_base, QSERDES_COM_HSCLK_SEL);

	div &= 0x0f;

	pr_debug("input rates: parent=%lu, vco=%lu\n", parent_rate, vco->rate);



	if (div == 12)

		hsclk_div = 6; /* Default */

	else if (div == 4)

		hsclk_div = 4;

	else if (div == 0)

	hsclk_sel = MDSS_PLL_REG_R(dp_res->pll_base, QSERDES_COM_HSCLK_SEL);

	hsclk_sel &= 0x0f;



	if (hsclk_sel == 5)

		hsclk_div = 5;

	else if (hsclk_sel == 3)

		hsclk_div = 3;

	else if (hsclk_sel == 1)

		hsclk_div = 2;

	else if (div == 3)

	else if (hsclk_sel == 0)

		hsclk_div = 1;

	else {

		pr_debug("unknown divider. forcing to default\n");

		hsclk_div = 5;

	}



	div = MDSS_PLL_REG_R(dp_res->phy_base, DP_PHY_AUX_CFG2);

	div >>= 2;

	link_clk_divsel = MDSS_PLL_REG_R(dp_res->phy_base, DP_PHY_AUX_CFG2);

	link_clk_divsel >>= 2;

	link_clk_divsel &= 0x3;



	if ((div & 0x3) == 0)

	if (link_clk_divsel == 0)

		link_clk_div = 5;

	else if ((div & 0x3) == 1)

	else if (link_clk_divsel == 1)

		link_clk_div = 10;

	else if ((div & 0x3) == 2)

	else if (link_clk_divsel == 2)

		link_clk_div = 20;

	else

		pr_err("unsupported div. Phy_mode: %d\n", div);

		pr_err("unsupported div. Phy_mode: %d\n", link_clk_divsel);



	if (link_clk_div == 20) {

		vco_rate = DP_VCO_HSCLK_RATE_2700MHZDIV1000;

	} else {

		if (hsclk_div == 6)

		if (hsclk_div == 5)

			vco_rate = DP_VCO_HSCLK_RATE_1620MHZDIV1000;

		else if (hsclk_div == 4)

		else if (hsclk_div == 3)

			vco_rate = DP_VCO_HSCLK_RATE_2700MHZDIV1000;

		else if (hsclk_div == 2)

			vco_rate = DP_VCO_HSCLK_RATE_5400MHZDIV1000;
@@ -699,7 +695,8 @@ unsigned long dp_vco_recalc_rate_7nm(struct clk_hw *hw, 
			vco_rate = DP_VCO_HSCLK_RATE_8100MHZDIV1000;

	}



	pr_debug("returning vco rate = %lu\n", vco_rate);

	pr_debug("hsclk: sel=0x%x, div=0x%x; lclk: sel=%lu, div=%lu, rate=%lu\n",

		hsclk_sel, hsclk_div, link_clk_divsel, link_clk_div, vco_rate);



	mdss_pll_resource_enable(dp_res, false);
@@ -728,7 +725,7 @@ long dp_vco_round_rate_7nm(struct clk_hw *hw, unsigned long rate, 
	else

		rrate = vco->max_rate;



	pr_debug("%s: rrate=%ld\n", __func__, rrate);

	pr_debug("rrate=%ld\n", rrate);



	if (parent_rate)

		*parent_rate = rrate;

drivers/gpu/drm/msm/dp/dp_catalog_v420.c

+9 −3
Original line number Diff line number Diff line
@@ -108,13 +108,15 @@ static void dp_catalog_aux_setup_v420(struct dp_catalog_aux *aux, 
	catalog = dp_catalog_get_priv_v420(aux);



	io_data = catalog->io->dp_phy;

	dp_write(catalog, io_data, DP_PHY_PD_CTL, 0x7D);

	dp_write(catalog, io_data, DP_PHY_PD_CTL, 0x65);

	wmb(); /* make sure PD programming happened */



	/* Turn on BIAS current for PHY/PLL */

	dp_write(catalog, io_data,

		QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3d);

	io_data = catalog->io->dp_pll;

	dp_write(catalog, io_data, QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x17);

	wmb(); /* make sure PD programming happened */



	io_data = catalog->io->dp_phy;

	/* DP AUX CFG register programming */

	for (i = 0; i < PHY_AUX_CFG_MAX; i++) {

		pr_debug("%s: offset=0x%08x, value=0x%08x\n",
@@ -123,6 +125,7 @@ static void dp_catalog_aux_setup_v420(struct dp_catalog_aux *aux, 
		dp_write(catalog, io_data, cfg[i].offset,

			cfg[i].lut[cfg[i].current_index]);

	}

	wmb(); /* make sure DP AUX CFG programming happened */



	dp_write(catalog, io_data, DP_PHY_AUX_INTERRUPT_MASK_V420, 0x1F);

}
@@ -327,5 +330,8 @@ int dp_catalog_get_v420(struct device *dev, struct dp_catalog *catalog, 
	catalog->ctrl.phy_lane_cfg = dp_catalog_ctrl_phy_lane_cfg_v420;

	catalog->ctrl.update_vx_px = dp_catalog_ctrl_update_vx_px_v420;



	/* Set the default execution mode to hardware mode */

	dp_catalog_set_exe_mode_v420(catalog, "hw");



	return 0;

}

drivers/gpu/drm/msm/dp/dp_display.c

+8 −15
Original line number Diff line number Diff line
@@ -73,7 +73,7 @@ struct dp_display_private { 
	atomic_t aborted;



	struct platform_device *pdev;

	struct platform_device *aux_switch_pdev;

	struct device_node *aux_switch_node;

	struct dentry *root;

	struct completion notification_comp;
@@ -656,7 +656,7 @@ static int dp_display_configure_aux_switch(struct dp_display_private *dp) 
	int rc = 0;

	enum fsa_function event = FSA_EVENT_MAX;



	if (!dp->aux_switch_pdev) {

	if (!dp->aux_switch_node) {

		pr_debug("undefined fsa4480 handle\n");

		goto end;

	}
@@ -674,7 +674,7 @@ static int dp_display_configure_aux_switch(struct dp_display_private *dp) 
		goto end;

	}



	rc = fsa4480_switch_event(dp->aux_switch_pdev->dev.of_node, event);

	rc = fsa4480_switch_event(dp->aux_switch_node, event);

	if (rc)

		pr_err("failed to configure fsa4480 i2c device (%d)\n", rc);

end:
@@ -1593,7 +1593,6 @@ static int dp_display_fsa4480_callback(struct notifier_block *self, 
static int dp_display_init_aux_switch(struct dp_display_private *dp)

{

	int rc = 0;

	struct device_node *pd = NULL;

	const char *phandle = "qcom,dp-aux-switch";

	struct notifier_block nb;
@@ -1603,29 +1602,23 @@ static int dp_display_init_aux_switch(struct dp_display_private *dp) 
		goto end;

	}



	pd = of_parse_phandle(dp->pdev->dev.of_node, phandle, 0);

	if (!pd) {

	dp->aux_switch_node = of_parse_phandle(dp->pdev->dev.of_node,

			phandle, 0);

	if (!dp->aux_switch_node) {

		pr_warn("cannot parse %s handle\n", phandle);

		goto end;

	}



	dp->aux_switch_pdev = of_find_device_by_node(pd);

	if (!dp->aux_switch_pdev) {

		pr_err("cannot find %s pdev\n", phandle);

		rc = -ENODEV;

		goto end;

	}



	nb.notifier_call = dp_display_fsa4480_callback;

	nb.priority = 0;



	rc = fsa4480_reg_notifier(&nb, dp->aux_switch_pdev->dev.of_node);

	rc = fsa4480_reg_notifier(&nb, dp->aux_switch_node);

	if (rc) {

		pr_err("failed to register notifier (%d)\n", rc);

		goto end;

	}



	fsa4480_unreg_notifier(&nb, dp->aux_switch_pdev->dev.of_node);

	fsa4480_unreg_notifier(&nb, dp->aux_switch_node);

end:

	return rc;

}