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Commit f5d8491a authored by Damien Lespiau's avatar Damien Lespiau Committed by Daniel Vetter
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drm/i915/tv: Use intel_flush_display_plane() to flush the primary plane 



Instead of writing to the DSP_ADDR ourselves. This will do the right
thing on gen >= 4 as well.

Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 01a415fd

drivers/gpu/drm/i915/intel_tv.c

+2 −5
Original line number Diff line number Diff line
@@ -1088,13 +1088,11 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, 
		int dspcntr_reg = DSPCNTR(intel_crtc->plane);

		int pipeconf = I915_READ(pipeconf_reg);

		int dspcntr = I915_READ(dspcntr_reg);

		int dspbase_reg = DSPADDR(intel_crtc->plane);

		int xpos = 0x0, ypos = 0x0;

		unsigned int xsize, ysize;

		/* Pipe must be off here */

		I915_WRITE(dspcntr_reg, dspcntr & ~DISPLAY_PLANE_ENABLE);

		/* Flush the plane changes */

		I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));

		intel_flush_display_plane(dev_priv, intel_crtc->plane);



		/* Wait for vblank for the disable to take effect */

		if (IS_GEN2(dev))
@@ -1123,8 +1121,7 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, 


		I915_WRITE(pipeconf_reg, pipeconf);

		I915_WRITE(dspcntr_reg, dspcntr);

		/* Flush the plane changes */

		I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));

		intel_flush_display_plane(dev_priv, intel_crtc->plane);

	}



	j = 0;