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Commit f56cb86f authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau: add instmem flush() hook 



This removes the previous prepare_access() and finish_access() hooks, and
replaces it with a much simpler flush() hook.

All the chipset-specific code before nv50 has its use removed completely,
as it's not required there at all.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 2107cce3

drivers/gpu/drm/nouveau/nouveau_drv.h

+3 −6
Original line number Diff line number Diff line
@@ -269,8 +269,7 @@ struct nouveau_instmem_engine { 
	void	(*clear)(struct drm_device *, struct nouveau_gpuobj *);

	int	(*bind)(struct drm_device *, struct nouveau_gpuobj *);

	int	(*unbind)(struct drm_device *, struct nouveau_gpuobj *);

	void	(*prepare_access)(struct drm_device *, bool write);

	void	(*finish_access)(struct drm_device *);

	void	(*flush)(struct drm_device *);

};



struct nouveau_mc_engine {
@@ -1027,8 +1026,7 @@ extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 
extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);

extern int  nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);

extern int  nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);

extern void nv04_instmem_prepare_access(struct drm_device *, bool write);

extern void nv04_instmem_finish_access(struct drm_device *);

extern void nv04_instmem_flush(struct drm_device *);



/* nv50_instmem.c */

extern int  nv50_instmem_init(struct drm_device *);
@@ -1040,8 +1038,7 @@ extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, 
extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);

extern int  nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);

extern int  nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);

extern void nv50_instmem_prepare_access(struct drm_device *, bool write);

extern void nv50_instmem_finish_access(struct drm_device *);

extern void nv50_instmem_flush(struct drm_device *);



/* nv04_mc.c */

extern int  nv04_mc_init(struct drm_device *);

drivers/gpu/drm/nouveau/nouveau_mem.c

+2 −4
Original line number Diff line number Diff line
@@ -143,7 +143,6 @@ nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size, 
		phys |= 0x30;

	}



	dev_priv->engine.instmem.prepare_access(dev, true);

	while (size) {

		unsigned offset_h = upper_32_bits(phys);

		unsigned offset_l = lower_32_bits(phys);
@@ -175,7 +174,7 @@ nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size, 
			}

		}

	}

	dev_priv->engine.instmem.finish_access(dev);

	dev_priv->engine.instmem.flush(dev);



	nv_wr32(dev, 0x100c80, 0x00050001);

	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
@@ -218,7 +217,6 @@ nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size) 
	virt -= dev_priv->vm_vram_base;

	pages = (size >> 16) << 1;



	dev_priv->engine.instmem.prepare_access(dev, true);

	while (pages) {

		pgt = dev_priv->vm_vram_pt[virt >> 29];

		pte = (virt & 0x1ffe0000ULL) >> 15;
@@ -232,7 +230,7 @@ nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size) 
		while (pte < end)

			nv_wo32(dev, pgt, pte++, 0);

	}

	dev_priv->engine.instmem.finish_access(dev);

	dev_priv->engine.instmem.flush(dev);



	nv_wr32(dev, 0x100c80, 0x00050001);

	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {

drivers/gpu/drm/nouveau/nouveau_object.c

+12 −33
Original line number Diff line number Diff line
@@ -132,7 +132,6 @@ nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref) 
		}

	}



	instmem->prepare_access(dev, true);

	co = ho = nouveau_ramht_hash_handle(dev, chan->id, ref->handle);

	do {

		if (!nouveau_ramht_entry_valid(dev, ramht, co)) {
@@ -143,7 +142,7 @@ nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref) 
			nv_wo32(dev, ramht, (co + 4)/4, ctx);



			list_add_tail(&ref->list, &chan->ramht_refs);

			instmem->finish_access(dev);

			instmem->flush(dev);

			return 0;

		}

		NV_DEBUG(dev, "collision ch%d 0x%08x: h=0x%08x\n",
@@ -153,7 +152,6 @@ nouveau_ramht_insert(struct drm_device *dev, struct nouveau_gpuobj_ref *ref) 
		if (co >= dev_priv->ramht_size)

			co = 0;

	} while (co != ho);

	instmem->finish_access(dev);



	NV_ERROR(dev, "RAMHT space exhausted. ch=%d\n", chan->id);

	return -ENOMEM;
@@ -173,7 +171,6 @@ nouveau_ramht_remove(struct drm_device *dev, struct nouveau_gpuobj_ref *ref) 
		return;

	}



	instmem->prepare_access(dev, true);

	co = ho = nouveau_ramht_hash_handle(dev, chan->id, ref->handle);

	do {

		if (nouveau_ramht_entry_valid(dev, ramht, co) &&
@@ -186,7 +183,7 @@ nouveau_ramht_remove(struct drm_device *dev, struct nouveau_gpuobj_ref *ref) 
			nv_wo32(dev, ramht, (co + 4)/4, 0x00000000);



			list_del(&ref->list);

			instmem->finish_access(dev);

			instmem->flush(dev);

			return;

		}
@@ -195,7 +192,6 @@ nouveau_ramht_remove(struct drm_device *dev, struct nouveau_gpuobj_ref *ref) 
			co = 0;

	} while (co != ho);

	list_del(&ref->list);

	instmem->finish_access(dev);



	NV_ERROR(dev, "RAMHT entry not found. ch=%d, handle=0x%08x\n",

		 chan->id, ref->handle);
@@ -280,10 +276,9 @@ nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan, 
	if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {

		int i;



		engine->instmem.prepare_access(dev, true);

		for (i = 0; i < gpuobj->im_pramin->size; i += 4)

			nv_wo32(dev, gpuobj, i/4, 0);

		engine->instmem.finish_access(dev);

		engine->instmem.flush(dev);

	}



	*gpuobj_ret = gpuobj;
@@ -371,10 +366,9 @@ nouveau_gpuobj_del(struct drm_device *dev, struct nouveau_gpuobj **pgpuobj) 
	}



	if (gpuobj->im_pramin && (gpuobj->flags & NVOBJ_FLAG_ZERO_FREE)) {

		engine->instmem.prepare_access(dev, true);

		for (i = 0; i < gpuobj->im_pramin->size; i += 4)

			nv_wo32(dev, gpuobj, i/4, 0);

		engine->instmem.finish_access(dev);

		engine->instmem.flush(dev);

	}



	if (gpuobj->dtor)
@@ -606,10 +600,9 @@ nouveau_gpuobj_new_fake(struct drm_device *dev, uint32_t p_offset, 
	}



	if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) {

		dev_priv->engine.instmem.prepare_access(dev, true);

		for (i = 0; i < gpuobj->im_pramin->size; i += 4)

			nv_wo32(dev, gpuobj, i/4, 0);

		dev_priv->engine.instmem.finish_access(dev);

		dev_priv->engine.instmem.flush(dev);

	}



	if (pref) {
@@ -697,8 +690,6 @@ nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class, 
		return ret;

	}



	instmem->prepare_access(dev, true);



	if (dev_priv->card_type < NV_50) {

		uint32_t frame, adjust, pte_flags = 0;
@@ -735,7 +726,7 @@ nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class, 
		nv_wo32(dev, *gpuobj, 5, flags5);

	}



	instmem->finish_access(dev);

	instmem->flush(dev);



	(*gpuobj)->engine = NVOBJ_ENGINE_SW;

	(*gpuobj)->class  = class;
@@ -850,7 +841,6 @@ nouveau_gpuobj_gr_new(struct nouveau_channel *chan, int class, 
		return ret;

	}



	dev_priv->engine.instmem.prepare_access(dev, true);

	if (dev_priv->card_type >= NV_50) {

		nv_wo32(dev, *gpuobj, 0, class);

		nv_wo32(dev, *gpuobj, 5, 0x00010000);
@@ -875,7 +865,7 @@ nouveau_gpuobj_gr_new(struct nouveau_channel *chan, int class, 
			}

		}

	}

	dev_priv->engine.instmem.finish_access(dev);

	dev_priv->engine.instmem.flush(dev);



	(*gpuobj)->engine = NVOBJ_ENGINE_GR;

	(*gpuobj)->class  = class;
@@ -988,17 +978,13 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan, 
	if (dev_priv->card_type >= NV_50) {

		uint32_t vm_offset, pde;



		instmem->prepare_access(dev, true);



		vm_offset = (dev_priv->chipset & 0xf0) == 0x50 ? 0x1400 : 0x200;

		vm_offset += chan->ramin->gpuobj->im_pramin->start;



		ret = nouveau_gpuobj_new_fake(dev, vm_offset, ~0, 0x4000,

							0, &chan->vm_pd, NULL);

		if (ret) {

			instmem->finish_access(dev);

		if (ret)

			return ret;

		}

		for (i = 0; i < 0x4000; i += 8) {

			nv_wo32(dev, chan->vm_pd, (i+0)/4, 0x00000000);

			nv_wo32(dev, chan->vm_pd, (i+4)/4, 0xdeadcafe);
@@ -1008,10 +994,8 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan, 
		ret = nouveau_gpuobj_ref_add(dev, NULL, 0,

					     dev_priv->gart_info.sg_ctxdma,

					     &chan->vm_gart_pt);

		if (ret) {

			instmem->finish_access(dev);

		if (ret)

			return ret;

		}

		nv_wo32(dev, chan->vm_pd, pde++,

			    chan->vm_gart_pt->instance | 0x03);

		nv_wo32(dev, chan->vm_pd, pde++, 0x00000000);
@@ -1021,17 +1005,15 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan, 
			ret = nouveau_gpuobj_ref_add(dev, NULL, 0,

						     dev_priv->vm_vram_pt[i],

						     &chan->vm_vram_pt[i]);

			if (ret) {

				instmem->finish_access(dev);

			if (ret)

				return ret;

			}



			nv_wo32(dev, chan->vm_pd, pde++,

				    chan->vm_vram_pt[i]->instance | 0x61);

			nv_wo32(dev, chan->vm_pd, pde++, 0x00000000);

		}



		instmem->finish_access(dev);

		instmem->flush(dev);

	}



	/* RAMHT */
@@ -1164,10 +1146,8 @@ nouveau_gpuobj_suspend(struct drm_device *dev) 
			return -ENOMEM;

		}



		dev_priv->engine.instmem.prepare_access(dev, false);

		for (i = 0; i < gpuobj->im_pramin->size / 4; i++)

			gpuobj->im_backing_suspend[i] = nv_ro32(dev, gpuobj, i);

		dev_priv->engine.instmem.finish_access(dev);

	}



	return 0;
@@ -1212,10 +1192,9 @@ nouveau_gpuobj_resume(struct drm_device *dev) 
		if (!gpuobj->im_backing_suspend)

			continue;



		dev_priv->engine.instmem.prepare_access(dev, true);

		for (i = 0; i < gpuobj->im_pramin->size / 4; i++)

			nv_wo32(dev, gpuobj, i, gpuobj->im_backing_suspend[i]);

		dev_priv->engine.instmem.finish_access(dev);

		dev_priv->engine.instmem.flush(dev);

	}



	nouveau_gpuobj_suspend_cleanup(dev);

drivers/gpu/drm/nouveau/nouveau_sgdma.c

+3 −9
Original line number Diff line number Diff line
@@ -97,7 +97,6 @@ nouveau_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem) 


	NV_DEBUG(dev, "pg=0x%lx\n", mem->mm_node->start);



	dev_priv->engine.instmem.prepare_access(nvbe->dev, true);

	pte = nouveau_sgdma_pte(nvbe->dev, mem->mm_node->start << PAGE_SHIFT);

	nvbe->pte_start = pte;

	for (i = 0; i < nvbe->nr_pages; i++) {
@@ -116,7 +115,7 @@ nouveau_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem) 
			dma_offset += NV_CTXDMA_PAGE_SIZE;

		}

	}

	dev_priv->engine.instmem.finish_access(nvbe->dev);

	dev_priv->engine.instmem.flush(nvbe->dev);



	if (dev_priv->card_type == NV_50) {

		nv_wr32(dev, 0x100c80, 0x00050001);
@@ -154,7 +153,6 @@ nouveau_sgdma_unbind(struct ttm_backend *be) 
	if (!nvbe->bound)

		return 0;



	dev_priv->engine.instmem.prepare_access(nvbe->dev, true);

	pte = nvbe->pte_start;

	for (i = 0; i < nvbe->nr_pages; i++) {

		dma_addr_t dma_offset = dev_priv->gart_info.sg_dummy_bus;
@@ -170,7 +168,7 @@ nouveau_sgdma_unbind(struct ttm_backend *be) 
			dma_offset += NV_CTXDMA_PAGE_SIZE;

		}

	}

	dev_priv->engine.instmem.finish_access(nvbe->dev);

	dev_priv->engine.instmem.flush(nvbe->dev);



	if (dev_priv->card_type == NV_50) {

		nv_wr32(dev, 0x100c80, 0x00050001);
@@ -272,7 +270,6 @@ nouveau_sgdma_init(struct drm_device *dev) 
		pci_map_page(dev->pdev, dev_priv->gart_info.sg_dummy_page, 0,

			     PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);



	dev_priv->engine.instmem.prepare_access(dev, true);

	if (dev_priv->card_type < NV_50) {

		/* Maybe use NV_DMA_TARGET_AGP for PCIE? NVIDIA do this, and

		 * confirmed to work on c51.  Perhaps means NV_DMA_TARGET_PCIE
@@ -294,7 +291,7 @@ nouveau_sgdma_init(struct drm_device *dev) 
			nv_wo32(dev, gpuobj, (i+4)/4, 0);

		}

	}

	dev_priv->engine.instmem.finish_access(dev);

	dev_priv->engine.instmem.flush(dev);



	dev_priv->gart_info.type      = NOUVEAU_GART_SGDMA;

	dev_priv->gart_info.aper_base = 0;
@@ -325,14 +322,11 @@ nouveau_sgdma_get_page(struct drm_device *dev, uint32_t offset, uint32_t *page) 
{

	struct drm_nouveau_private *dev_priv = dev->dev_private;

	struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma;

	struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem;

	int pte;



	pte = (offset >> NV_CTXDMA_PAGE_SHIFT);

	if (dev_priv->card_type < NV_50) {

		instmem->prepare_access(dev, false);

		*page = nv_ro32(dev, gpuobj, (pte + 2)) & ~NV_CTXDMA_PAGE_MASK;

		instmem->finish_access(dev);

		return 0;

	}

drivers/gpu/drm/nouveau/nouveau_state.c

+6 −12
Original line number Diff line number Diff line
@@ -54,8 +54,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) 
		engine->instmem.clear		= nv04_instmem_clear;

		engine->instmem.bind		= nv04_instmem_bind;

		engine->instmem.unbind		= nv04_instmem_unbind;

		engine->instmem.prepare_access	= nv04_instmem_prepare_access;

		engine->instmem.finish_access	= nv04_instmem_finish_access;

		engine->instmem.flush		= nv04_instmem_flush;

		engine->mc.init			= nv04_mc_init;

		engine->mc.takedown		= nv04_mc_takedown;

		engine->timer.init		= nv04_timer_init;
@@ -95,8 +94,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) 
		engine->instmem.clear		= nv04_instmem_clear;

		engine->instmem.bind		= nv04_instmem_bind;

		engine->instmem.unbind		= nv04_instmem_unbind;

		engine->instmem.prepare_access	= nv04_instmem_prepare_access;

		engine->instmem.finish_access	= nv04_instmem_finish_access;

		engine->instmem.flush		= nv04_instmem_flush;

		engine->mc.init			= nv04_mc_init;

		engine->mc.takedown		= nv04_mc_takedown;

		engine->timer.init		= nv04_timer_init;
@@ -138,8 +136,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) 
		engine->instmem.clear		= nv04_instmem_clear;

		engine->instmem.bind		= nv04_instmem_bind;

		engine->instmem.unbind		= nv04_instmem_unbind;

		engine->instmem.prepare_access	= nv04_instmem_prepare_access;

		engine->instmem.finish_access	= nv04_instmem_finish_access;

		engine->instmem.flush		= nv04_instmem_flush;

		engine->mc.init			= nv04_mc_init;

		engine->mc.takedown		= nv04_mc_takedown;

		engine->timer.init		= nv04_timer_init;
@@ -181,8 +178,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) 
		engine->instmem.clear		= nv04_instmem_clear;

		engine->instmem.bind		= nv04_instmem_bind;

		engine->instmem.unbind		= nv04_instmem_unbind;

		engine->instmem.prepare_access	= nv04_instmem_prepare_access;

		engine->instmem.finish_access	= nv04_instmem_finish_access;

		engine->instmem.flush		= nv04_instmem_flush;

		engine->mc.init			= nv04_mc_init;

		engine->mc.takedown		= nv04_mc_takedown;

		engine->timer.init		= nv04_timer_init;
@@ -225,8 +221,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) 
		engine->instmem.clear		= nv04_instmem_clear;

		engine->instmem.bind		= nv04_instmem_bind;

		engine->instmem.unbind		= nv04_instmem_unbind;

		engine->instmem.prepare_access	= nv04_instmem_prepare_access;

		engine->instmem.finish_access	= nv04_instmem_finish_access;

		engine->instmem.flush		= nv04_instmem_flush;

		engine->mc.init			= nv40_mc_init;

		engine->mc.takedown		= nv40_mc_takedown;

		engine->timer.init		= nv04_timer_init;
@@ -271,8 +266,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) 
		engine->instmem.clear		= nv50_instmem_clear;

		engine->instmem.bind		= nv50_instmem_bind;

		engine->instmem.unbind		= nv50_instmem_unbind;

		engine->instmem.prepare_access	= nv50_instmem_prepare_access;

		engine->instmem.finish_access	= nv50_instmem_finish_access;

		engine->instmem.flush		= nv50_instmem_flush;

		engine->mc.init			= nv50_mc_init;

		engine->mc.takedown		= nv50_mc_takedown;

		engine->timer.init		= nv04_timer_init;