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Commit f51ecd77 authored by Sujith Manoharan's avatar Sujith Manoharan Committed by John W. Linville
Browse files

ath9k: Add SERDES initvals for AR9462 2.1 



Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent babaa80a

drivers/net/wireless/ath/ath9k/ar9003_hw.c

+4 −0
Original line number Diff line number Diff line
@@ -223,6 +223,10 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) 
			       ar9462_2p1_modes_fast_clock);

		INIT_INI_ARRAY(&ah->iniCckfirJapan2484,

			       ar9462_2p1_baseband_core_txfir_coeff_japan_2484);

		INIT_INI_ARRAY(&ah->iniPcieSerdes,

			       ar9462_2p1_pciephy_clkreq_disable_L1);

		INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,

			       ar9462_2p1_pciephy_clkreq_disable_L1);

	} else if (AR_SREV_9462_20(ah)) {



		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);

drivers/net/wireless/ath/ath9k/ar9462_2p1_initvals.h

+7 −0
Original line number Diff line number Diff line
@@ -1771,4 +1771,11 @@ static const u32 ar9462_2p1_baseband_core_txfir_coeff_japan_2484[][2] = { 
	{0x0000a3a0, 0xca9228ee},

};



static const u32 ar9462_2p1_pciephy_clkreq_disable_L1[][2] = {

	/* Addr      allmodes  */

	{0x00018c00, 0x18213ede},

	{0x00018c04, 0x000801d8},

	{0x00018c08, 0x0003780c},

};



#endif /* INITVALS_9462_2P1_H */