staging: sm750fb: restructure multi-line comments to follow CodingStyle (f5016082) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/staging/sm750fb/ddk750.h

+11 −11

Original line number	Diff line number	Diff line
		#ifndef DDK750_H__
		#define DDK750_H__
		/*******************************************************************
		*
		/*
		* Copyright (c) 2007 by Silicon Motion, Inc. (SMI)
		*
		* All rights are reserved. Reproduction or in part is prohibited
		@@ -9,8 +6,11 @@
		*
		* RegSC.h --- SM718 SDK
		* This file contains the definitions for the System Configuration registers.
		*
		*******************************************************************/
		*/

		#ifndef DDK750_H__
		#define DDK750_H__

		#include "ddk750_reg.h"
		#include "ddk750_mode.h"
		#include "ddk750_chip.h"

drivers/staging/sm750fb/ddk750_chip.c

+24 −15

Original line number	Diff line number	Diff line
		@@ -62,16 +62,17 @@ static void set_chip_clock(unsigned int frequency)

		if (frequency) {
		/*
		* Set up PLL, a structure to hold the value to be set in clocks.
		* Set up PLL structure to hold the value to be set in clocks.
		*/
		pll.inputFreq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */
		pll.clockType = MXCLK_PLL;

		/*
		* Call calc_pll_value() to fill the other fields of PLL structure.
		* Sometime, the chip cannot set up the exact clock
		* required by the User.
		* Return value of calc_pll_value gives the actual possible clock.
		* Call calc_pll_value() to fill the other fields of the PLL
		* structure. Sometimes, the chip cannot set up the exact
		* clock required by the User.
		* Return value of calc_pll_value gives the actual possible
		* clock.
		*/
		ulActualMxClk = calc_pll_value(frequency, &pll);

		@@ -84,7 +85,8 @@ static void set_memory_clock(unsigned int frequency)
		{
		unsigned int reg, divisor;

		/* Cheok_0509: For SM750LE, the memory clock is fixed.
		/*
		* Cheok_0509: For SM750LE, the memory clock is fixed.
		* Nothing to set.
		*/
		if (sm750_get_chip_type() == SM750LE)
		@@ -135,14 +137,16 @@ static void set_master_clock(unsigned int frequency)
		{
		unsigned int reg, divisor;

		/* Cheok_0509: For SM750LE, the memory clock is fixed.
		/*
		* Cheok_0509: For SM750LE, the memory clock is fixed.
		* Nothing to set.
		*/
		if (sm750_get_chip_type() == SM750LE)
		return;

		if (frequency) {
		/* Set the frequency to the maximum frequency
		/*
		* Set the frequency to the maximum frequency
		* that the SM750 engine can run, which is about 190 MHz.
		*/
		if (frequency > MHz(190))
		@@ -241,7 +245,8 @@ int ddk750_init_hw(struct initchip_param *pInitParam)
		set_master_clock(MHz(pInitParam->masterClock));


		/* Reset the memory controller.
		/*
		* Reset the memory controller.
		* If the memory controller is not reset in SM750,
		* the system might hang when sw accesses the memory.
		* The memory should be resetted after changing the MXCLK.
		@@ -306,7 +311,8 @@ int ddk750_init_hw(struct initchip_param *pInitParam)
		*/
		unsigned int calc_pll_value(unsigned int request_orig, struct pll_value *pll)
		{
		/* as sm750 register definition,
		/*
		* as sm750 register definition,
		* N located in 2,15 and M located in 1,255
		*/
		int N, M, X, d;
		@@ -318,7 +324,8 @@ unsigned int calc_pll_value(unsigned int request_orig, struct pll_value *pll)
		int max_d = 6;

		if (sm750_get_chip_type() == SM750LE) {
		/* SM750LE don't have
		/*
		* SM750LE don't have
		* programmable PLL and M/N values to work on.
		* Just return the requested clock.
		*/
		@@ -330,14 +337,16 @@ unsigned int calc_pll_value(unsigned int request_orig, struct pll_value *pll)
		request = request_orig / 1000;
		input = pll->inputFreq / 1000;

		/* for MXCLK register,
		/*
		* for MXCLK register,
		* no POD provided, so need be treated differently
		*/
		if (pll->clockType == MXCLK_PLL)
		max_d = 3;

		for (N = 15; N > 1; N--) {
		/* RN will not exceed maximum long
		/*
		* RN will not exceed maximum long
		* if @request <= 285 MHZ (for 32bit cpu)
		*/
		RN = N * request;

drivers/staging/sm750fb/ddk750_chip.h

+36 −25

Original line number	Diff line number	Diff line
		@@ -46,31 +46,42 @@ struct pll_value {

		/* input struct to initChipParam() function */
		struct initchip_param {
		unsigned short powerMode; /* Use power mode 0 or 1 */
		unsigned short chipClock; /**
		/* Use power mode 0 or 1 */
		unsigned short powerMode;

		/*
		* Speed of main chip clock in MHz unit
		* 0 = keep the current clock setting
		* Others = the new main chip clock
		*/
		unsigned short memClock; /**
		unsigned short chipClock;

		/*
		* Speed of memory clock in MHz unit
		* 0 = keep the current clock setting
		* Others = the new memory clock
		*/
		unsigned short masterClock; /**
		unsigned short memClock;

		/*
		* Speed of master clock in MHz unit
		* 0 = keep the current clock setting
		* Others = the new master clock
		*/
		unsigned short setAllEngOff; /**
		unsigned short masterClock;

		/*
		* 0 = leave all engine state untouched.
		* 1 = make sure they are off: 2D, Overlay,
		* video alpha, alpha, hardware cursors
		*/
		unsigned char resetMemory; /**
		unsigned short setAllEngOff;

		/*
		* 0 = Do not reset the memory controller
		* 1 = Reset the memory controller
		*/
		unsigned char resetMemory;

		/* More initialization parameter can be added if needed */
		};

drivers/staging/sm750fb/ddk750_display.h

+20 −10

Original line number	Diff line number	Diff line
		#ifndef DDK750_DISPLAY_H__
		#define DDK750_DISPLAY_H__

		/* panel path select
		/*
		* panel path select
		* 80000[29:28]
		*/

		@@ -12,7 +13,8 @@
		#define PNL_2_SEC ((2 << PNL_2_OFFSET) \| PNL_2_USAGE)


		/* primary timing & plane enable bit
		/*
		* primary timing & plane enable bit
		* 1: 80000[8] & 80000[2] on
		* 0: both off
		*/
		@@ -23,7 +25,8 @@
		#define PRI_TP_OFF ((0x0 << PRI_TP_OFFSET) \| PRI_TP_USAGE)


		/* panel sequency status
		/*
		* panel sequency status
		* 80000[27:24]
		*/
		#define PNL_SEQ_OFFSET 6
		@@ -32,7 +35,8 @@
		#define PNL_SEQ_ON (BIT(PNL_SEQ_OFFSET) \| PNL_SEQ_USAGE)
		#define PNL_SEQ_OFF ((0 << PNL_SEQ_OFFSET) \| PNL_SEQ_USAGE)

		/* dual digital output
		/*
		* dual digital output
		* 80000[19]
		*/
		#define DUAL_TFT_OFFSET 8
		@@ -41,7 +45,8 @@
		#define DUAL_TFT_ON (BIT(DUAL_TFT_OFFSET) \| DUAL_TFT_USAGE)
		#define DUAL_TFT_OFF ((0 << DUAL_TFT_OFFSET) \| DUAL_TFT_USAGE)

		/* secondary timing & plane enable bit
		/*
		* secondary timing & plane enable bit
		* 1:80200[8] & 80200[2] on
		* 0: both off
		*/
		@@ -51,7 +56,8 @@
		#define SEC_TP_ON ((0x1 << SEC_TP_OFFSET) \| SEC_TP_USAGE)
		#define SEC_TP_OFF ((0x0 << SEC_TP_OFFSET) \| SEC_TP_USAGE)

		/* crt path select
		/*
		* crt path select
		* 80200[19:18]
		*/
		#define CRT_2_OFFSET 2
		@@ -61,7 +67,8 @@
		#define CRT_2_SEC ((0x2 << CRT_2_OFFSET) \| CRT_2_USAGE)


		/* DAC affect both DVI and DSUB
		/*
		* DAC affect both DVI and DSUB
		* 4[20]
		*/
		#define DAC_OFFSET 7
		@@ -70,7 +77,8 @@
		#define DAC_ON ((0x0 << DAC_OFFSET) \| DAC_USAGE)
		#define DAC_OFF ((0x1 << DAC_OFFSET) \| DAC_USAGE)

		/* DPMS only affect D-SUB head
		/*
		* DPMS only affect D-SUB head
		* 0[31:30]
		*/
		#define DPMS_OFFSET 9
		@@ -81,7 +89,8 @@



		/* LCD1 means panel path TFT1 & panel path DVI (so enable DAC)
		/*
		* LCD1 means panel path TFT1 & panel path DVI (so enable DAC)
		* CRT means crt path DSUB
		*/
		typedef enum _disp_output_t {
		@@ -89,7 +98,8 @@ typedef enum _disp_output_t {
		do_LCD1_SEC = PNL_2_SEC \| SEC_TP_ON \| PNL_SEQ_ON \| DAC_ON,
		do_LCD2_PRI = CRT_2_PRI \| PRI_TP_ON \| DUAL_TFT_ON,
		do_LCD2_SEC = CRT_2_SEC \| SEC_TP_ON \| DUAL_TFT_ON,
		/* do_DSUB_PRI = CRT_2_PRI \| PRI_TP_ON \| DPMS_ON\|DAC_ON,
		/*
		* do_DSUB_PRI = CRT_2_PRI \| PRI_TP_ON \| DPMS_ON\|DAC_ON,
		* do_DSUB_SEC = CRT_2_SEC \| SEC_TP_ON \| DPMS_ON\|DAC_ON,
		*/
		do_CRT_PRI = CRT_2_PRI \| PRI_TP_ON \| DPMS_ON \| DAC_ON,

drivers/staging/sm750fb/ddk750_hwi2c.c

+6 −3

Original line number	Diff line number	Diff line
		@@ -20,7 +20,8 @@ unsigned char bus_speed_mode
		value \|= (GPIO_MUX_30 \| GPIO_MUX_31);
		POKE32(GPIO_MUX, value);

		/* Enable Hardware I2C power.
		/*
		* Enable Hardware I2C power.
		* TODO: Check if we need to enable GPIO power?
		*/
		enableI2C(1);
		@@ -92,7 +93,8 @@ static unsigned int hw_i2c_write_data(
		/* Set the Device Address */
		POKE32(I2C_SLAVE_ADDRESS, addr & ~0x01);

		/* Write data.
		/*
		* Write data.
		* Note:
		* Only 16 byte can be accessed per i2c start instruction.
		*/
		@@ -158,7 +160,8 @@ static unsigned int hw_i2c_read_data(
		/* Set the Device Address */
		POKE32(I2C_SLAVE_ADDRESS, addr \| 0x01);

		/* Read data and save them to the buffer.
		/*
		* Read data and save them to the buffer.
		* Note:
		* Only 16 byte can be accessed per i2c start instruction.
		*/