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Commit f4f4b59b authored by Ander Conselvan de Oliveira's avatar Ander Conselvan de Oliveira
Browse files

drm/i915/glk: Implement WaDDIIOTimeout 



Implement WaDDIIOTimeout to avoid a timeout when enabling the DDI IO
power domains.

Signed-off-by: default avatarAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170222063431.10060-5-ander.conselvan.de.oliveira@intel.com
parent 9a5da00b

drivers/gpu/drm/i915/i915_drv.h

+6 −0
Original line number Diff line number Diff line
@@ -2787,6 +2787,12 @@ intel_info(const struct drm_i915_private *dev_priv) 
#define IS_KBL_REVID(dev_priv, since, until) \

	(IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))



#define GLK_REVID_A0		0x0

#define GLK_REVID_A1		0x1



#define IS_GLK_REVID(dev_priv, since, until) \

	(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))



/*

 * The genX designation typically refers to the render engine, so render

 * capability related checks should use IS_GEN, while display and other checks

drivers/gpu/drm/i915/i915_reg.h

+5 −0
Original line number Diff line number Diff line
@@ -6479,6 +6479,11 @@ enum { 
#define CHICKEN_PAR2_1		_MMIO(0x42090)

#define  KVM_CONFIG_CHANGE_NOTIFICATION_SELECT	(1 << 14)



#define CHICKEN_MISC_2		_MMIO(0x42084)

#define  GLK_CL0_PWR_DOWN	(1 << 10)

#define  GLK_CL1_PWR_DOWN	(1 << 11)

#define  GLK_CL2_PWR_DOWN	(1 << 12)



#define _CHICKEN_PIPESL_1_A	0x420b0

#define _CHICKEN_PIPESL_1_B	0x420b4

#define  HSW_FBCQ_DIS			(1 << 22)

drivers/gpu/drm/i915/intel_pm.c

+10 −0
Original line number Diff line number Diff line
@@ -114,6 +114,16 @@ static void glk_init_clock_gating(struct drm_i915_private *dev_priv) 
	 */

	I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |

		   PWM1_GATING_DIS | PWM2_GATING_DIS);



	/* WaDDIIOTimeout:glk */

	if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1)) {

		u32 val = I915_READ(CHICKEN_MISC_2);

		val &= ~(GLK_CL0_PWR_DOWN |

			 GLK_CL1_PWR_DOWN |

			 GLK_CL2_PWR_DOWN);

		I915_WRITE(CHICKEN_MISC_2, val);

	}



}



static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)