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Commit f4da21a2 authored by Manaf Meethalavalappu Pallikunhi's avatar Manaf Meethalavalappu Pallikunhi
Browse files

ARM: dts: msm: Add LMH-DCVSh configuration for SDMSHRIKE 



Add LMH-DCVSh hardware configuration like debug interrupt and cluster
affinity value for SDMSHRIKE. Add the CPU to LMH-DCVSh hardware
mapping, along with the thermal algorithm configuration.

Change-Id: I54e62461a7853ccf8cadc2003df572d9c928860b
Signed-off-by: default avatarManaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
parent e53681d7

arch/arm64/boot/dts/qcom/sdmshrike-thermal.dtsi

+54 −0
Original line number Diff line number Diff line
@@ -12,6 +12,28 @@ 


#include <dt-bindings/thermal/thermal.h>



&clock_cpucc {

	#address-cells = <1>;

	#size-cells = <1>;

	lmh_dcvs0: qcom,limits-dcvs@18358800 {

		compatible = "qcom,msm-hw-limits";

		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

		qcom,affinity = <0>;

		reg = <0x18358800 0x1000>,

			<0x18323000 0x1000>;

		#thermal-sensor-cells = <0>;

	};



	lmh_dcvs1: qcom,limits-dcvs@18350800 {

		compatible = "qcom,msm-hw-limits";

		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;

		qcom,affinity = <1>;

		reg = <0x18350800 0x1000>,

			<0x18325800 0x1000>;

		#thermal-sensor-cells = <0>;

	};

};



&thermal_zones {

	aoss0-usr {

		polling-delay-passive = <0>;
@@ -652,4 +674,36 @@ 
			};

		};

	};



	lmh-dcvs-01 {

		polling-delay-passive = <0>;

		polling-delay = <0>;

		thermal-governor = "user_space";

		thermal-sensors = <&lmh_dcvs1>;

		wake-capable-sensor;



		trips {

			active-config {

				temperature = <85000>;

				hysteresis = <25000>;

				type = "passive";

			};

		};

	};



	lmh-dcvs-00 {

		polling-delay-passive = <0>;

		polling-delay = <0>;

		thermal-governor = "user_space";

		thermal-sensors = <&lmh_dcvs0>;

		wake-capable-sensor;



		trips {

			active-config {

				temperature = <85000>;

				hysteresis = <25000>;

				type = "passive";

			};

		};

	};

};

arch/arm64/boot/dts/qcom/sdmshrike.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -55,6 +55,7 @@ 
			enable-method = "psci";

			cache-size = <0x8000>;

			next-level-cache = <&L2_0>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_0: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -86,6 +87,7 @@ 
			enable-method = "psci";

			cache-size = <0x8000>;

			next-level-cache = <&L2_1>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_1: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -111,6 +113,7 @@ 
			enable-method = "psci";

			cache-size = <0x8000>;

			next-level-cache = <&L2_2>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_2: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -136,6 +139,7 @@ 
			enable-method = "psci";

			cache-size = <0x8000>;

			next-level-cache = <&L2_3>;

			qcom,lmh-dcvs = <&lmh_dcvs0>;

			L2_3: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x20000>;
@@ -161,6 +165,7 @@ 
			enable-method = "psci";

			cache-size = <0x20000>;

			next-level-cache = <&L2_4>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			L2_4: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x80000>;
@@ -186,6 +191,7 @@ 
			enable-method = "psci";

			cache-size = <0x20000>;

			next-level-cache = <&L2_5>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			L2_5: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x80000>;
@@ -211,6 +217,7 @@ 
			enable-method = "psci";

			cache-size = <0x20000>;

			next-level-cache = <&L2_6>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			L2_6: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x80000>;
@@ -236,6 +243,7 @@ 
			enable-method = "psci";

			cache-size = <0x20000>;

			next-level-cache = <&L2_7>;

			qcom,lmh-dcvs = <&lmh_dcvs1>;

			L2_7: l2-cache {

			      compatible = "arm,arch-cache";

			      cache-size = <0x80000>;