drm/nouveau: remove (most) hardcoded object handle usage (f45f55c4) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/gpu/drm/nouveau/nouveau_abi16.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -301,7 +301,7 @@ nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS)
	if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) {		if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) {
	init->subchan[0].handle = 0x00000000;		init->subchan[0].handle = 0x00000000;
	init->subchan[0].grclass = 0x0000;		init->subchan[0].grclass = 0x0000;
	init->subchan[1].handle = NvSw;		init->subchan[1].handle = chan->chan->nvsw.handle;
	init->subchan[1].grclass = 0x506e;		init->subchan[1].grclass = 0x506e;
	init->nr_subchan = 2;		init->nr_subchan = 2;
	}		}

drivers/gpu/drm/nouveau/nouveau_bo.c

+5 −5

Original line number	Original line	Diff line number	Diff line
	@@ -765,9 +765,9 @@ nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
	BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);		BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
	OUT_RING (chan, handle);		OUT_RING (chan, handle);
	BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);		BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);
	OUT_RING (chan, NvNotify0);		OUT_RING (chan, chan->drm->ntfy.handle);
	OUT_RING (chan, NvDmaFB);		OUT_RING (chan, chan->vram.handle);
	OUT_RING (chan, NvDmaFB);		OUT_RING (chan, chan->vram.handle);
	}		}

	return ret;		return ret;
	@@ -854,7 +854,7 @@ nv04_bo_move_init(struct nouveau_channel *chan, u32 handle)
	BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);		BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
	OUT_RING (chan, handle);		OUT_RING (chan, handle);
	BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);		BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);
	OUT_RING (chan, NvNotify0);		OUT_RING (chan, chan->drm->ntfy.handle);
	}		}

	return ret;		return ret;
	@@ -866,7 +866,7 @@ nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
	{		{
	if (mem->mem_type == TTM_PL_TT)		if (mem->mem_type == TTM_PL_TT)
	return NvDmaTT;		return NvDmaTT;
	return NvDmaFB;		return chan->vram.handle;
	}		}

	static int		static int

drivers/gpu/drm/nouveau/nouveau_chan.c

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -335,7 +335,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)

	/* allocate software object class (used for fences on <= nv05) */		/* allocate software object class (used for fences on <= nv05) */
	if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) {		if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) {
	ret = nvif_object_init(chan->object, NULL, NvSw, 0x006e,		ret = nvif_object_init(chan->object, NULL, 0x006e, 0x006e,
	NULL, 0, &chan->nvsw);		NULL, 0, &chan->nvsw);
	if (ret)		if (ret)
	return ret;		return ret;
	@@ -349,7 +349,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
	return ret;		return ret;

	BEGIN_NV04(chan, NvSubSw, 0x0000, 1);		BEGIN_NV04(chan, NvSubSw, 0x0000, 1);
	OUT_RING (chan, NvSw);		OUT_RING (chan, chan->nvsw.handle);
	FIRE_RING (chan);		FIRE_RING (chan);
	}		}

drivers/gpu/drm/nouveau/nouveau_dma.h

+1 −15

Original line number	Original line	Diff line number	Diff line
	@@ -58,28 +58,14 @@ enum {
	FermiSw = 5, /* DO NOT CHANGE (well.. 6/7 will work...) */		FermiSw = 5, /* DO NOT CHANGE (well.. 6/7 will work...) */
	};		};

	/* Object handles. */		/* Object handles - for stuff that's doesn't use handle == oclass. */
	enum {		enum {
	NvM2MF = 0x80000001,
	NvDmaFB = 0x80000002,		NvDmaFB = 0x80000002,
	NvDmaTT = 0x80000003,		NvDmaTT = 0x80000003,
	NvNotify0 = 0x80000006,		NvNotify0 = 0x80000006,
	Nv2D = 0x80000007,
	NvCtxSurf2D = 0x80000008,
	NvRop = 0x80000009,
	NvImagePatt = 0x8000000a,
	NvClipRect = 0x8000000b,
	NvGdiRect = 0x8000000c,
	NvImageBlit = 0x8000000d,
	NvSw = 0x8000000e,
	NvSema = 0x8000000f,		NvSema = 0x8000000f,
	NvEvoSema0 = 0x80000010,		NvEvoSema0 = 0x80000010,
	NvEvoSema1 = 0x80000011,		NvEvoSema1 = 0x80000011,
	NvNotify1 = 0x80000012,

	/* G80+ display objects */
	NvEvoVRAM = 0x01000000,
	NvEvoSync = 0xcafe0000
	};		};

	#define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039		#define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039

drivers/gpu/drm/nouveau/nv04_fbcon.c

+18 −18

Original line number	Original line	Diff line number	Diff line
	@@ -173,33 +173,33 @@ nv04_fbcon_accel_init(struct fb_info *info)
	return -EINVAL;		return -EINVAL;
	}		}

	ret = nvif_object_init(chan->object, NULL, NvCtxSurf2D,		ret = nvif_object_init(chan->object, NULL, 0x0062,
	device->info.family >= NV_DEVICE_INFO_V0_CELSIUS ?		device->info.family >= NV_DEVICE_INFO_V0_CELSIUS ?
	0x0062 : 0x0042, NULL, 0, &nfbdev->surf2d);		0x0062 : 0x0042, NULL, 0, &nfbdev->surf2d);
	if (ret)		if (ret)
	return ret;		return ret;

	ret = nvif_object_init(chan->object, NULL, NvClipRect, 0x0019, NULL, 0,		ret = nvif_object_init(chan->object, NULL, 0x0019, 0x0019, NULL, 0,
	&nfbdev->clip);		&nfbdev->clip);
	if (ret)		if (ret)
	return ret;		return ret;

	ret = nvif_object_init(chan->object, NULL, NvRop, 0x0043, NULL, 0,		ret = nvif_object_init(chan->object, NULL, 0x0043, 0x0043, NULL, 0,
	&nfbdev->rop);		&nfbdev->rop);
	if (ret)		if (ret)
	return ret;		return ret;

	ret = nvif_object_init(chan->object, NULL, NvImagePatt, 0x0044, NULL, 0,		ret = nvif_object_init(chan->object, NULL, 0x0044, 0x0044, NULL, 0,
	&nfbdev->patt);		&nfbdev->patt);
	if (ret)		if (ret)
	return ret;		return ret;

	ret = nvif_object_init(chan->object, NULL, NvGdiRect, 0x004a, NULL, 0,		ret = nvif_object_init(chan->object, NULL, 0x004a, 0x004a, NULL, 0,
	&nfbdev->gdi);		&nfbdev->gdi);
	if (ret)		if (ret)
	return ret;		return ret;

	ret = nvif_object_init(chan->object, NULL, NvImageBlit,		ret = nvif_object_init(chan->object, NULL, 0x005f,
	device->info.chipset >= 0x11 ? 0x009f : 0x005f,		device->info.chipset >= 0x11 ? 0x009f : 0x005f,
	NULL, 0, &nfbdev->blit);		NULL, 0, &nfbdev->blit);
	if (ret)		if (ret)
	@@ -211,10 +211,10 @@ nv04_fbcon_accel_init(struct fb_info *info)
	}		}

	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);		BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
	OUT_RING(chan, NvCtxSurf2D);		OUT_RING(chan, nfbdev->surf2d.handle);
	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0184, 2);		BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0184, 2);
	OUT_RING(chan, NvDmaFB);		OUT_RING(chan, chan->vram.handle);
	OUT_RING(chan, NvDmaFB);		OUT_RING(chan, chan->vram.handle);
	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 4);		BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 4);
	OUT_RING(chan, surface_fmt);		OUT_RING(chan, surface_fmt);
	OUT_RING(chan, info->fix.line_length \| (info->fix.line_length << 16));		OUT_RING(chan, info->fix.line_length \| (info->fix.line_length << 16));
	@@ -222,12 +222,12 @@ nv04_fbcon_accel_init(struct fb_info *info)
	OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);		OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);

	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);		BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
	OUT_RING(chan, NvRop);		OUT_RING(chan, nfbdev->rop.handle);
	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 1);		BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 1);
	OUT_RING(chan, 0x55);		OUT_RING(chan, 0x55);

	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);		BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
	OUT_RING(chan, NvImagePatt);		OUT_RING(chan, nfbdev->patt.handle);
	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 8);		BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 8);
	OUT_RING(chan, pattern_fmt);		OUT_RING(chan, pattern_fmt);
	#ifdef __BIG_ENDIAN		#ifdef __BIG_ENDIAN
	@@ -243,15 +243,15 @@ nv04_fbcon_accel_init(struct fb_info *info)
	OUT_RING(chan, ~0);		OUT_RING(chan, ~0);

	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);		BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
	OUT_RING(chan, NvClipRect);		OUT_RING(chan, nfbdev->clip.handle);
	BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 2);		BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 2);
	OUT_RING(chan, 0);		OUT_RING(chan, 0);
	OUT_RING(chan, (info->var.yres_virtual << 16) \| info->var.xres_virtual);		OUT_RING(chan, (info->var.yres_virtual << 16) \| info->var.xres_virtual);

	BEGIN_NV04(chan, NvSubImageBlit, 0x0000, 1);		BEGIN_NV04(chan, NvSubImageBlit, 0x0000, 1);
	OUT_RING(chan, NvImageBlit);		OUT_RING(chan, nfbdev->blit.handle);
	BEGIN_NV04(chan, NvSubImageBlit, 0x019c, 1);		BEGIN_NV04(chan, NvSubImageBlit, 0x019c, 1);
	OUT_RING(chan, NvCtxSurf2D);		OUT_RING(chan, nfbdev->surf2d.handle);
	BEGIN_NV04(chan, NvSubImageBlit, 0x02fc, 1);		BEGIN_NV04(chan, NvSubImageBlit, 0x02fc, 1);
	OUT_RING(chan, 3);		OUT_RING(chan, 3);
	if (device->info.chipset >= 0x11 /XXX: oclass == 0x009f/) {		if (device->info.chipset >= 0x11 /XXX: oclass == 0x009f/) {
	@@ -262,12 +262,12 @@ nv04_fbcon_accel_init(struct fb_info *info)
	}		}

	BEGIN_NV04(chan, NvSubGdiRect, 0x0000, 1);		BEGIN_NV04(chan, NvSubGdiRect, 0x0000, 1);
	OUT_RING(chan, NvGdiRect);		OUT_RING(chan, nfbdev->gdi.handle);
	BEGIN_NV04(chan, NvSubGdiRect, 0x0198, 1);		BEGIN_NV04(chan, NvSubGdiRect, 0x0198, 1);
	OUT_RING(chan, NvCtxSurf2D);		OUT_RING(chan, nfbdev->surf2d.handle);
	BEGIN_NV04(chan, NvSubGdiRect, 0x0188, 2);		BEGIN_NV04(chan, NvSubGdiRect, 0x0188, 2);
	OUT_RING(chan, NvImagePatt);		OUT_RING(chan, nfbdev->patt.handle);
	OUT_RING(chan, NvRop);		OUT_RING(chan, nfbdev->rop.handle);
	BEGIN_NV04(chan, NvSubGdiRect, 0x0304, 1);		BEGIN_NV04(chan, NvSubGdiRect, 0x0304, 1);
	OUT_RING(chan, 1);		OUT_RING(chan, 1);
	BEGIN_NV04(chan, NvSubGdiRect, 0x0300, 1);		BEGIN_NV04(chan, NvSubGdiRect, 0x0300, 1);