Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f449e04d authored by Harry Yang's avatar Harry Yang
Browse files

power: smb1355: Fix multiple I2C addr issue 



SMB1355 is responding to both I2C addr of 0x0C and 0x0D due to setting
in slave ID register I2C_SS_DIG_PMIC_SID_REG.

To correct this issue such that SMB1355 only responds to 0x0C, SMB1355's
I2C_SS_DIG_PMIC_SID_REG must have only PMIC_SID0_BIT bit set through
secure write at the start.

Change-Id: I088087fc9681fdb01616bab33f73d556f3e7f813
Signed-off-by: default avatarHarry Yang <harryy@codeaurora.org>
parent 952512e3

drivers/power/supply/qcom/smb1355-charger.c

+14 −0
Original line number Diff line number Diff line
@@ -32,11 +32,16 @@ 


/* SMB1355 registers, different than mentioned in smb-reg.h */



#define I2C_SS_DIG_BASE 0x0E00

#define CHGR_BASE	0x1000

#define BATIF_BASE	0x1200

#define USBIN_BASE	0x1300

#define MISC_BASE	0x1600



#define I2C_SS_DIG_PMIC_SID_REG			(I2C_SS_DIG_BASE + 0x45)

#define PMIC_SID_MASK				GENMASK(3, 0)

#define PMIC_SID0_BIT				BIT(0)



#define BATTERY_STATUS_2_REG			(CHGR_BASE + 0x0B)

#define DISABLE_CHARGING_BIT			BIT(3)
@@ -694,6 +699,15 @@ static int smb1355_init_hw(struct smb1355 *chip) 
{

	int rc;



	/* Change to let SMB1355 only respond to address 0x0C  */

	rc = smb1355_masked_write(chip, I2C_SS_DIG_PMIC_SID_REG,

					PMIC_SID_MASK, PMIC_SID0_BIT);

	if (rc < 0) {

		pr_err("Couldn't configure the I2C_SS_DIG_PMIC_SID_REG rc=%d\n",

					rc);

		return rc;

	}



	/* enable watchdog bark and bite interrupts, and disable the watchdog */

	rc = smb1355_masked_write(chip, WD_CFG_REG, WDOG_TIMER_EN_BIT

			| WDOG_TIMER_EN_ON_PLUGIN_BIT | BITE_WDOG_INT_EN_BIT