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Commit f43b95bb authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add USB related nodes for QCS405"

parents 21b8aa0b 9428ec4e

arch/arm64/boot/dts/qcom/qcs405-rumi.dtsi

+32 −0
Original line number Diff line number Diff line
@@ -13,6 +13,30 @@ 
#include "qcs405.dtsi"



&soc {

	usb_emu_phy: usb_emu_phy@78ccd00 {

		compatible = "qcom,usb-emu-phy";

		reg = <0x78ccd00 0x9500>,

		      <0x79b8800 0x100>;

		reg-names = "base", "qcratch_base";



		qcom,emu-init-seq = <0xfff0 0x4

				     0xfff3 0x4

				     0x40 0x4

				     0xfff3 0x4

				     0xfff0 0x4

				     0x100000 0x20

				     0x0 0x20

				     0x1a0 0x20

				     0x100000 0x3c

				     0x0 0x3c

				     0x10060 0x3c

				     0x0 0x4>;

	};



	usb_nop_phy: usb_nop_phy {

		compatible = "usb-nop-xceiv";

	};



	timer {

		clock-frequency = <0x100000>;

	};
@@ -21,3 +45,11 @@ 
		clock-frequency = <0x100000>;

	};

};



&usb0 {

	dwc3@78c0000 {

		usb-phy = <&usb_emu_phy>, <&usb_nop_phy>;

		maximum-speed = "high-speed";

		dr_mode = "peripheral";

	};

};

arch/arm64/boot/dts/qcom/qcs405.dtsi

+38 −0
Original line number Diff line number Diff line
@@ -275,6 +275,44 @@ 
	};



	thermal_zones: thermal-zones {};



	usb0: hsusb@78c0000 {

		compatible = "qcom,dwc-usb3-msm";

		reg = <0x78c0000 0x100000>;

		reg-names = "core_base";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		interrupts = <0 32 0>;

		interrupt-names = "pwr_event_irq";

		/* Using dummy Xo clock, need to check the proper mapping */

		clocks = <&clock_gcc GCC_USB_HS_SYSTEM_CLK>,

			 <&clock_gcc GCC_PCNOC_USB2_CLK>,

			 <&clock_gcc GCC_USB30_SLEEP_CLK>,

			 <&clock_gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,

			 <&clock_gcc GCC_USB20_MOCK_UTMI_CLK>;

		clock-names = "core_clk", "iface_clk", "xo",

				"sleep_clk", "utmi_clk";



		qcom,core-clk-rate = <200000000>;

		qcom,core-clk-rate-hs = <66666667>;

		qcom,dwc-usb3-msm-tx-fifo-size = <27696>;

		resets = <&clock_gcc GCC_USB_HS_BCR>;

		reset-names = "core_reset";



		dwc3@78c0000 {

			compatible = "snps,dwc3";

			reg = <0x78c0000 0xcd00>;

			interrupt-parent = <&intc>;

			interrupts = <0 44 0>;

			tx-fifo-resize;

			linux,sysdev_is_parent;

			snps,disable-clk-gating;

			snps,has-lpm-erratum;

			snps,hird-threshold = /bits/ 8 <0x10>;

		};

	};

};



#include "qcs405-gdsc.dtsi"