Merge "Revert "drm/msm/sde: modify DSC initial_lines calculation"" (f439ea0b) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/gpu/drm/msm/sde/sde_encoder.c

+7 −19

Original line number	Diff line number	Diff line
		@@ -1158,37 +1158,25 @@ static void _sde_encoder_dsc_pclk_param_calc(struct msm_display_dsc_info *dsc,
		static int _sde_encoder_dsc_initial_line_calc(struct msm_display_dsc_info *dsc,
		int enc_ip_width)
		{
		int ssm_delay, total_pixels, soft_slice_per_enc, fifo_size;
		int first_line_offset, tmp[3];
		int ssm_delay, total_pixels, soft_slice_per_enc;

		soft_slice_per_enc = enc_ip_width / dsc->slice_width;

		/*
		* minimum number of initial line pixels is a sum of:
		* 1. sub-stream multiplexer delay (84 groups for 8bpc,
		* 92 for 10 bpc) * 3
		* 1. sub-stream multiplexer delay (83 groups for 8bpc,
		* 91 for 10 bpc) * 3
		* 2. for two soft slice cases, add extra sub-stream multiplexer * 3
		* 3. the initial xmit delay
		* 4. total pipeline delay through the "lock step" of encoder (47)
		* 5. 6 additional pixels as the output of the rate buffer is
		* 48 bits wide
		*/
		ssm_delay = 3 * ((dsc->bpc < 10) ? 84 : 92);
		total_pixels = (soft_slice_per_enc * ssm_delay)
		+ dsc->initial_xmit_delay + 47;
		fifo_size = ((soft_slice_per_enc == 2) ? 5610 : 11610);
		first_line_offset =
		(dsc->first_line_bpg_offset * dsc->pic_width) / (3 * 8);

		ssm_delay = ((dsc->bpc < 10) ? 84 : 92);
		total_pixels = ssm_delay * 3 + dsc->initial_xmit_delay + 47;
		if (soft_slice_per_enc > 1)
		total_pixels += (ssm_delay * 3);
		dsc->initial_lines = DIV_ROUND_UP(total_pixels, dsc->slice_width);

		tmp[0] = dsc->initial_xmit_delay + first_line_offset;
		tmp[1] = (2 + (0.75 * soft_slice_per_enc)) * dsc->chunk_size;
		tmp[2] = (total_pixels % dsc->slice_width) * (dsc->bpp / 8);

		if ((tmp[0] + tmp[1] - tmp[2]) < fifo_size)
		dsc->initial_lines++;

		return 0;
		}

drivers/gpu/drm/msm/sde/sde_hw_dsc.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -56,6 +56,7 @@ static void sde_hw_dsc_config(struct sde_hw_dsc *hw_dsc,
		u32 data;
		int bpp, lsb;
		u32 initial_lines = dsc->initial_lines;
		bool is_cmd_mode = !(mode & BIT(2));
		struct sde_hw_blk_reg_map *dsc_c = &hw_dsc->hw;

		SDE_REG_WRITE(dsc_c, DSC_COMMON_MODE, mode);
		@@ -64,6 +65,9 @@ static void sde_hw_dsc_config(struct sde_hw_dsc *hw_dsc,
		if (ich_reset_override)
		data = 3 << 28;

		if (is_cmd_mode)
		initial_lines += 1;

		data \|= (initial_lines << 20);
		data \|= (dsc->slice_last_group_size << 18);
		/* bpp is 6.4 format, 4 LSBs bits are for fractional part */