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Commit f4166c54 authored by Markus Metzger's avatar Markus Metzger Committed by Ingo Molnar
Browse files

x86, bts: DS and BTS initialization 



Impact: widen BTS/PEBS ptrace enablement to more CPU models

Move BTS initialisation out of an #ifdef CONFIG_X86_64 guard.

Assume core2 BTS and DS layout for future models of family 6 processors.

Signed-off-by: default avatarMarkus Metzger <markus.t.metzger@intel.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent f7160c75

arch/x86/kernel/cpu/intel.c

+1 −2
Original line number Original line Diff line number Diff line
@@ -307,12 +307,11 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) 
		set_cpu_cap(c, X86_FEATURE_P4);

		set_cpu_cap(c, X86_FEATURE_P4);

	if (c->x86 == 6)

	if (c->x86 == 6)

		set_cpu_cap(c, X86_FEATURE_P3);

		set_cpu_cap(c, X86_FEATURE_P3);

#endif





	if (cpu_has_bts)

	if (cpu_has_bts)

		ptrace_bts_init_intel(c);

		ptrace_bts_init_intel(c);





#endif



	detect_extended_topology(c);

	detect_extended_topology(c);

	if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {

	if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {

		/*

		/*

arch/x86/kernel/ds.c

+4 −5
Original line number Original line Diff line number Diff line
@@ -821,17 +821,16 @@ void __cpuinit ds_init_intel(struct cpuinfo_x86 *c) 
	switch (c->x86) {

	switch (c->x86) {

	case 0x6:

	case 0x6:

		switch (c->x86_model) {

		switch (c->x86_model) {

		case 0 ... 0xC:

			/* sorry, don't know about them */

			break;

		case 0xD:

		case 0xD:

		case 0xE: /* Pentium M */

		case 0xE: /* Pentium M */

			ds_configure(&ds_cfg_var);

			ds_configure(&ds_cfg_var);

			break;

			break;

		case 0xF: /* Core2 */

		default: /* Core2, Atom, ... */

		case 0x1C: /* Atom */

			ds_configure(&ds_cfg_64);

			ds_configure(&ds_cfg_64);

			break;

			break;

		default:

			/* sorry, don't know about them */

			break;

		}

		}

		break;

		break;

	case 0xF:

	case 0xF:

arch/x86/kernel/ptrace.c

+4 −5
Original line number Original line Diff line number Diff line
@@ -929,17 +929,16 @@ void __cpuinit ptrace_bts_init_intel(struct cpuinfo_x86 *c) 
	switch (c->x86) {

	switch (c->x86) {

	case 0x6:

	case 0x6:

		switch (c->x86_model) {

		switch (c->x86_model) {

		case 0 ... 0xC:

			/* sorry, don't know about them */

			break;

		case 0xD:

		case 0xD:

		case 0xE: /* Pentium M */

		case 0xE: /* Pentium M */

			bts_configure(&bts_cfg_pentium_m);

			bts_configure(&bts_cfg_pentium_m);

			break;

			break;

		case 0xF: /* Core2 */

		default: /* Core2, Atom, ... */

        case 0x1C: /* Atom */

			bts_configure(&bts_cfg_core2);

			bts_configure(&bts_cfg_core2);

			break;

			break;

		default:

			/* sorry, don't know about them */

			break;

		}

		}

		break;

		break;

	case 0xF:

	case 0xF: