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Commit f3b8f912 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915/execlists: Reorder execlists register enabling 



Empirically we restart following a GPU reset more successfully if we call
lrc_init_hws() (which contains a posting read) last. (The failure mode
that was observed was that breadcrumb writes into the HWS from the
recovered requests went astray leading to the context-switch maintaining
forward progress, but the requests not being retired/completed.)

For clarity, lrc_init_hws() is inlined (and the unused function then
removed).

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170105153023.30575-3-chris@chris-wilson.co.uk
parent 56f6e0a7

drivers/gpu/drm/i915/intel_lrc.c

+4 −14
Original line number Diff line number Diff line
@@ -1335,15 +1335,6 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine) 
	return ret;

}



static void lrc_init_hws(struct intel_engine_cs *engine)

{

	struct drm_i915_private *dev_priv = engine->i915;



	I915_WRITE(RING_HWS_PGA(engine->mmio_base),

		   engine->status_page.ggtt_offset);

	POSTING_READ(RING_HWS_PGA(engine->mmio_base));

}



static int gen8_init_common_ring(struct intel_engine_cs *engine)

{

	struct drm_i915_private *dev_priv = engine->i915;
@@ -1353,20 +1344,19 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine) 
	if (ret)

		return ret;



	lrc_init_hws(engine);



	intel_engine_reset_breadcrumbs(engine);

	intel_engine_init_hangcheck(engine);



	I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);



	I915_WRITE(RING_MODE_GEN7(engine),

		   _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |

		   _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));

	I915_WRITE(RING_HWS_PGA(engine->mmio_base),

		   engine->status_page.ggtt_offset);

	POSTING_READ(RING_HWS_PGA(engine->mmio_base));



	DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);



	intel_engine_init_hangcheck(engine);



	/* After a GPU reset, we may have requests to replay */

	if (!execlists_elsp_idle(engine)) {

		engine->execlist_port[0].count = 0;