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Commit f3b33ede authored by Mats Randgaard's avatar Mats Randgaard Committed by Mauro Carvalho Chehab
Browse files

[media] ad9389b: change initial register configuration in ad9389b_setup() 



- register 0x17: CSC scaling factor was set to +/- 2.0. This register
  is set by ad9389b_csc_conversion_mode() to the right value.
- register 0x3b: bits for pixel repetition and CSC was set to zero,
  but that is the default value.

Signed-off-by: default avatarMats Randgaard <matrandg@cisco.com>
Signed-off-by: default avatarHans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: default avatarMauro Carvalho Chehab <m.chehab@samsung.com>
parent 350a1815

drivers/media/i2c/ad9389b.c

+3 −5
Original line number Diff line number Diff line
@@ -894,11 +894,9 @@ static void ad9389b_setup(struct v4l2_subdev *sd) 
	ad9389b_wr_and_or(sd, 0x15, 0xf1, 0x0);

	/* Output format: RGB 4:4:4 */

	ad9389b_wr_and_or(sd, 0x16, 0x3f, 0x0);

	/* CSC fixed point: +/-2, 1st order interpolation 4:2:2 -> 4:4:4 up

	   conversion, Aspect ratio: 16:9 */

	ad9389b_wr_and_or(sd, 0x17, 0xe1, 0x0e);

	/* Disable pixel repetition and CSC */

	ad9389b_wr_and_or(sd, 0x3b, 0x9e, 0x0);

	/* 1st order interpolation 4:2:2 -> 4:4:4 up conversion,

	   Aspect ratio: 16:9 */

	ad9389b_wr_and_or(sd, 0x17, 0xf9, 0x06);

	/* Output format: RGB 4:4:4, Active Format Information is valid. */

	ad9389b_wr_and_or(sd, 0x45, 0xc7, 0x08);

	/* Underscanned */