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Commit f39e5b6d authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Update the clock controller nodes for TRINKET"

parents 0bf88e44 8e322965

arch/arm64/boot/dts/qcom/trinket.dtsi

+44 −18
Original line number Diff line number Diff line
@@ -18,7 +18,7 @@ 
#include <dt-bindings/clock/qcom,cpucc-sm8150.h>

#include <dt-bindings/clock/qcom,dispcc-trinket.h>

#include <dt-bindings/clock/qcom,gpucc-trinket.h>

#include <dt-bindings/clock/qcom,videocc-sm6150.h>

#include <dt-bindings/clock/qcom,videocc-trinket.h>

#include <dt-bindings/iio/qcom,spmi-vadc.h>

#include <dt-bindings/spmi/spmi.h>

#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
@@ -727,38 +727,64 @@ 
		};

	};



	clocks {

		sleep_clk: sleep-clk {

			compatible = "fixed-clock";

			clock-frequency = <32000>;

			clock-output-names = "chip_sleep_clk";

			#clock-cells = <1>;

		};

	};



	clock_rpmcc: qcom,rpmcc {

		compatible = "qcom,dummycc";

		clock-output-names = "rpmcc_clocks";

		compatible = "qcom,rpmcc-trinket";

		#clock-cells = <1>;

	};



	clock_gcc: qcom,gcc {

		compatible = "qcom,dummycc";

		clock-output-names = "gcc_clocks";

	clock_gcc: qcom,gcc@1400000 {

		compatible = "qcom,gcc-trinket", "syscon";

		reg = <0x1400000 0x1f0000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	clock_videocc: qcom,videocc {

		compatible = "qcom,dummycc";

		clock-output-names = "videocc_clocks";

	clock_videocc: qcom,videocc@5b00000 {

		compatible = "qcom,videocc-trinket", "syscon";

		reg = <0x5b00000 0x10000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	clock_dispcc: qcom,dispcc {

		compatible = "qcom,dummycc";

		clock-output-names = "dispcc_clocks";

	clock_dispcc: qcom,dispcc@5f00000 {

		compatible = "qcom,dispcc-trinket", "syscon";

		reg = <0x5f00000 0x20000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	clock_gpucc: qcom,gpupcc {

		compatible = "qcom,dummycc";

		clock-output-names = "gpucc_clocks";

	clock_gpucc: qcom,gpupcc@5990000 {

		compatible = "qcom,gpucc-trinket", "syscon";

		reg = <0x5990000 0x9000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_mx-supply = <&VDD_MX_LEVEL>;

		#clock-cells = <1>;

	};



	clock_debugcc: qcom,cc-debug {

		compatible = "qcom,debugcc-trinket";

		qcom,gcc = <&clock_gcc>;

		qcom,videocc = <&clock_videocc>;

		qcom,dispcc = <&clock_dispcc>;

		qcom,gpucc = <&clock_gpucc>;

		clock-names = "cxo";

		clocks = <&clock_rpmcc RPM_SMD_XO_CLK_SRC>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	clock_cpucc: qcom,cpucc {