CLK: TI: Add DPLL clock support

Binding for Texas Instruments DPLL clock.

Binding status: Unstable - ABI compatibility may be broken in the future

This binding uses the common clock binding[1].  It assumes a

register-mapped DPLL with usually two selectable input clocks

(reference clock and bypass clock), with digital phase locked

loop logic for multiplying the input clock to a desired output

clock. This clock also typically supports different operation

modes (locked, low power stop etc.) This binding has several

sub-types, which effectively result in slightly different setup

for the actual DPLL clock.

[1] Documentation/devicetree/bindings/clock/clock-bindings.txt

Required properties:

- compatible : shall be one of:

		"ti,omap3-dpll-clock",

		"ti,omap3-dpll-core-clock",

		"ti,omap3-dpll-per-clock",

		"ti,omap3-dpll-per-j-type-clock",

		"ti,omap4-dpll-clock",

		"ti,omap4-dpll-x2-clock",

		"ti,omap4-dpll-core-clock",

		"ti,omap4-dpll-m4xen-clock",

		"ti,omap4-dpll-j-type-clock",

		"ti,am3-dpll-no-gate-clock",

		"ti,am3-dpll-j-type-clock",

		"ti,am3-dpll-no-gate-j-type-clock",

		"ti,am3-dpll-clock",

		"ti,am3-dpll-core-clock",

		"ti,am3-dpll-x2-clock",

- #clock-cells : from common clock binding; shall be set to 0.

- clocks : link phandles of parent clocks, first entry lists reference clock

  and second entry bypass clock

- reg : offsets for the register set for controlling the DPLL.

  Registers are listed in following order:

	"control" - contains the control register base address

	"idlest" - contains the idle status register base address

	"mult-div1" - contains the multiplier / divider register base address

	"autoidle" - contains the autoidle register base address (optional)

  ti,am3-* dpll types do not have autoidle register

Optional properties:

- DPLL mode setting - defining any one or more of the following overrides

  default setting.

	- ti,low-power-stop : DPLL supports low power stop mode, gating output

	- ti,low-power-bypass : DPLL output matches rate of parent bypass clock

	- ti,lock : DPLL locks in programmed rate

Examples:

	dpll_core_ck: dpll_core_ck@44e00490 {

		#clock-cells = <0>;

		compatible = "ti,omap4-dpll-core-clock";

		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;

		reg = <0x490>, <0x45c>, <0x488>, <0x468>;

	};

	dpll2_ck: dpll2_ck@48004004 {

		#clock-cells = <0>;

		compatible = "ti,omap3-dpll-clock";

		clocks = <&sys_ck>, <&dpll2_fck>;

		ti,low-power-stop;

		ti,low-power-bypass;

		ti,lock;

		reg = <0x4>, <0x24>, <0x34>, <0x40>;

	};

	dpll_core_ck: dpll_core_ck@44e00490 {

		#clock-cells = <0>;

		compatible = "ti,am3-dpll-core-clock";

		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;

		reg = <0x90>, <0x5c>, <0x68>;

	};

#include <linux/clkdev.h>

#include <linux/clk-provider.h>

#include <linux/clk/ti.h>

struct omap_clk {

	u16				cpu;

	}

struct clockdomain;

#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)

#define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name)	\

	static struct clk _name = {				\

	const struct clksel_rate *rates;

};

/**

 * struct dpll_data - DPLL registers and integration data

 * @mult_div1_reg: register containing the DPLL M and N bitfields

 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg

 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg

 * @clk_bypass: struct clk pointer to the clock's bypass clock input

 * @clk_ref: struct clk pointer to the clock's reference clock input

 * @control_reg: register containing the DPLL mode bitfield

 * @enable_mask: mask of the DPLL mode bitfield in @control_reg

 * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()

 * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()

 * @last_rounded_m4xen: cache of the last M4X result of

 *			omap4_dpll_regm4xen_round_rate()

 * @last_rounded_lpmode: cache of the last lpmode result of

 *			 omap4_dpll_lpmode_recalc()

 * @max_multiplier: maximum valid non-bypass multiplier value (actual)

 * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()

 * @min_divider: minimum valid non-bypass divider value (actual)

 * @max_divider: maximum valid non-bypass divider value (actual)

 * @modes: possible values of @enable_mask

 * @autoidle_reg: register containing the DPLL autoidle mode bitfield

 * @idlest_reg: register containing the DPLL idle status bitfield

 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg

 * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg

 * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg

 * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg

 * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg

 * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg

 * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs

 * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs

 * @flags: DPLL type/features (see below)

 *

 * Possible values for @flags:

 * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)

 *

 * @freqsel_mask is only used on the OMAP34xx family and AM35xx.

 *

 * XXX Some DPLLs have multiple bypass inputs, so it's not technically

 * correct to only have one @clk_bypass pointer.

 *

 * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,

 * @last_rounded_n) should be separated from the runtime-fixed fields

 * and placed into a different structure, so that the runtime-fixed data

 * can be placed into read-only space.

 */

struct dpll_data {

	void __iomem		*mult_div1_reg;

	u32			mult_mask;

	u32			div1_mask;

	struct clk		*clk_bypass;

	struct clk		*clk_ref;

	void __iomem		*control_reg;

	u32			enable_mask;

	unsigned long		last_rounded_rate;

	u16			last_rounded_m;

	u8			last_rounded_m4xen;

	u8			last_rounded_lpmode;

	u16			max_multiplier;

	u8			last_rounded_n;

	u8			min_divider;

	u16			max_divider;

	u8			modes;

	void __iomem		*autoidle_reg;

	void __iomem		*idlest_reg;

	u32			autoidle_mask;

	u32			freqsel_mask;

	u32			idlest_mask;

	u32			dco_mask;

	u32			sddiv_mask;

	u32			lpmode_mask;

	u32			m4xen_mask;

	u8			auto_recal_bit;

	u8			recal_en_bit;

	u8			recal_st_bit;

	u8			flags;

};

/*

 * struct clk.flags possibilities

 *

 * XXX document the rest of the clock flags here

 *

 * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL

 *     bits share the same register.  This flag allows the

 *     omap4_dpllmx*() code to determine which GATE_CTRL bit field

 *     should be used.  This is a temporary solution - a better approach

 *     would be to associate clock type-specific data with the clock,

 *     similar to the struct dpll_data approach.

 */

#define ENABLE_REG_32BIT	(1 << 0)	/* Use 32-bit access */

#define CLOCK_IDLE_CONTROL	(1 << 1)

#define CLOCK_NO_IDLE_PARENT	(1 << 2)

#define ENABLE_ON_INIT		(1 << 3)	/* Enable upon framework init */

#define INVERT_ENABLE		(1 << 4)	/* 0 enables, 1 disables */

#define CLOCK_CLKOUTX2		(1 << 5)

/**

 * struct clk_hw_omap - OMAP struct clk

 * @node: list_head connecting this clock into the full clock list

 * @enable_reg: register to write to enable the clock (see @enable_bit)

 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)

 * @flags: see "struct clk.flags possibilities" above

 * @clksel_reg: for clksel clks, register va containing src/divisor select

 * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector

 * @clksel: for clksel clks, pointer to struct clksel for this clock

 * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock

 * @clkdm_name: clockdomain name that this clock is contained in

 * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime

 * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)

 * @src_offset: bitshift for source selection bitfield (OMAP1 only)

 *

 * XXX @rate_offset, @src_offset should probably be removed and OMAP1

 * clock code converted to use clksel.

 *

 */

struct clk_hw_omap_ops;

struct clk_hw_omap {

	struct clk_hw		hw;

	struct list_head	node;

	unsigned long		fixed_rate;

	u8			fixed_div;

	void __iomem		*enable_reg;

	u8			enable_bit;

	u8			flags;

	void __iomem		*clksel_reg;

	u32			clksel_mask;

	const struct clksel	*clksel;

	struct dpll_data	*dpll_data;

	const char		*clkdm_name;

	struct clockdomain	*clkdm;

	const struct clk_hw_omap_ops	*ops;

};

struct clk_hw_omap_ops {

	void			(*find_idlest)(struct clk_hw_omap *oclk,

					void __iomem **idlest_reg,

#define OMAP4XXX_EN_DPLL_FRBYPASS		0x6

#define OMAP4XXX_EN_DPLL_LOCKED			0x7

/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */

#define DPLL_LOW_POWER_STOP	0x1

#define DPLL_LOW_POWER_BYPASS	0x5

#define DPLL_LOCKED		0x7

/* DPLL Type and DCO Selection Flags */

#define DPLL_J_TYPE		0x1

long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,

			unsigned long *parent_rate);

unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);

int omap3_noncore_dpll_enable(struct clk_hw *hw);

void omap3_noncore_dpll_disable(struct clk_hw *hw);

int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,

				unsigned long parent_rate);

u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);

void omap3_dpll_allow_idle(struct clk_hw_omap *clk);

void omap3_dpll_deny_idle(struct clk_hw_omap *clk);

unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,

				    unsigned long parent_rate);

int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);

void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);

void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);

unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,

				unsigned long parent_rate);

long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,

				    unsigned long target_rate,

				    unsigned long *parent_rate);

void omap2_init_clk_clkdm(struct clk_hw *clk);

void __init omap2_clk_disable_clkdm_control(void);

/* clkt_clksel.c public functions */

extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);

extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);

u8 omap2_init_dpll_parent(struct clk_hw *hw);

unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);

int omap2_dflt_clk_enable(struct clk_hw *hw);

void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,

				void __iomem **idlest_reg,

				u8 *idlest_bit, u8 *idlest_val);

void omap2_init_clk_hw_omap_clocks(struct clk *clk);

int omap2_clk_enable_autoidle_all(void);

int omap2_clk_disable_autoidle_all(void);

int omap2_clk_allow_idle(struct clk *clk);

extern const struct clksel_rate dsp_ick_rates[];

extern struct clk dummy_ck;

extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;

extern const struct clk_hw_omap_ops clkhwops_iclk_wait;

extern const struct clk_hw_omap_ops clkhwops_wait;

extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;

extern const struct clk_hw_omap_ops clkhwops_iclk;

extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;

extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;

#define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H

int omap3xxx_clk_init(void);

int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,

					unsigned long parent_rate);

int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,

					unsigned long parent_rate);

void omap3_clk_lock_dpll5(void);

ifneq ($(CONFIG_OF),)

obj-y					+= clk.o

clk-common				= dpll.o

endif