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Commit f29ad10d authored by Kelvin Cheung's avatar Kelvin Cheung Committed by Ralf Baechle
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MIPS: Loongson1B: Some fixes/updates for LS1B 



- Fix hanging ethernet issue of LS1B v2.0 by adding pbl field in plat data.
   (It seems that the MAC controller of LS1B v2.0 can only accept pbl=1)
 - Add GMAC1 support and setup MUX in terms of PHY mode.
 - Add CPUFreq support.
 - Add MUX Register Definitions.
 - Add PWM Register Definitions.
 - Update clock register bitfields according to the latest spec.
 - Update clock related stuff.

Signed-off-by: default avatarKelvin Cheung <keguang.zhang@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8024/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 813c1410

arch/mips/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -1573,6 +1573,7 @@ config CPU_LOONGSON1 
	select CPU_HAS_PREFETCH

	select CPU_SUPPORTS_32BIT_KERNEL

	select CPU_SUPPORTS_HIGHMEM

	select CPU_SUPPORTS_CPUFREQ



config CPU_BMIPS32_3300

	select SMP_UP if SMP

arch/mips/include/asm/mach-loongson1/cpufreq.h

0 → 100644
+23 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2014 Zhang, Keguang <keguang.zhang@gmail.com>

 *

 * Loongson 1 CPUFreq platform support.

 *

 * This program is free software; you can redistribute	it and/or modify it

 * under  the terms of	the GNU General	 Public License as published by the

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 */





#ifndef __ASM_MACH_LOONGSON1_CPUFREQ_H

#define __ASM_MACH_LOONGSON1_CPUFREQ_H



struct plat_ls1x_cpufreq {

	const char	*clk_name;	/* CPU clk */

	const char	*osc_clk_name;	/* OSC clk */

	unsigned int	max_freq;	/* in kHz */

	unsigned int	min_freq;	/* in kHz */

};



#endif /* __ASM_MACH_LOONGSON1_CPUFREQ_H */

arch/mips/include/asm/mach-loongson1/loongson1.h

+7 −1
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 
#define DEFAULT_MEMSIZE			256	/* If no memsize provided */



/* Loongson 1 Register Bases */

#define LS1X_MUX_BASE			0x1fd00420

#define LS1X_INTC_BASE			0x1fd01040

#define LS1X_EHCI_BASE			0x1fe00000

#define LS1X_OHCI_BASE			0x1fe08000
@@ -31,7 +32,10 @@ 
#define LS1X_I2C0_BASE			0x1fe58000

#define LS1X_I2C1_BASE			0x1fe68000

#define LS1X_I2C2_BASE			0x1fe70000

#define LS1X_PWM_BASE			0x1fe5c000

#define LS1X_PWM0_BASE			0x1fe5c000

#define LS1X_PWM1_BASE			0x1fe5c010

#define LS1X_PWM2_BASE			0x1fe5c020

#define LS1X_PWM3_BASE			0x1fe5c030

#define LS1X_WDT_BASE			0x1fe5c060

#define LS1X_RTC_BASE			0x1fe64000

#define LS1X_AC97_BASE			0x1fe74000
@@ -39,6 +43,8 @@ 
#define LS1X_CLK_BASE			0x1fe78030



#include <regs-clk.h>

#include <regs-mux.h>

#include <regs-pwm.h>

#include <regs-wdt.h>



#endif /* __ASM_MACH_LOONGSON1_LOONGSON1_H */

arch/mips/include/asm/mach-loongson1/platform.h

+6 −4
Original line number Diff line number Diff line
@@ -13,10 +13,12 @@ 


#include <linux/platform_device.h>



extern struct platform_device ls1x_uart_device;

extern struct platform_device ls1x_eth0_device;

extern struct platform_device ls1x_ehci_device;

extern struct platform_device ls1x_rtc_device;

extern struct platform_device ls1x_uart_pdev;

extern struct platform_device ls1x_cpufreq_pdev;

extern struct platform_device ls1x_eth0_pdev;

extern struct platform_device ls1x_eth1_pdev;

extern struct platform_device ls1x_ehci_pdev;

extern struct platform_device ls1x_rtc_pdev;



extern void __init ls1x_clk_init(void);

extern void __init ls1x_serial_setup(struct platform_device *pdev);

arch/mips/include/asm/mach-loongson1/regs-clk.h

+20 −3
Original line number Diff line number Diff line
@@ -20,15 +20,32 @@ 


/* Clock PLL Divisor Register Bits */

#define DIV_DC_EN			(0x1 << 31)

#define DIV_DC_RST			(0x1 << 30)

#define DIV_CPU_EN			(0x1 << 25)

#define DIV_CPU_RST			(0x1 << 24)

#define DIV_DDR_EN			(0x1 << 19)

#define DIV_DDR_RST			(0x1 << 18)

#define RST_DC_EN			(0x1 << 5)

#define RST_DC				(0x1 << 4)

#define RST_DDR_EN			(0x1 << 3)

#define RST_DDR				(0x1 << 2)

#define RST_CPU_EN			(0x1 << 1)

#define RST_CPU				0x1



#define DIV_DC_SHIFT			26

#define DIV_CPU_SHIFT			20

#define DIV_DDR_SHIFT			14



#define DIV_DC_WIDTH			5

#define DIV_CPU_WIDTH			5

#define DIV_DDR_WIDTH			5

#define DIV_DC_WIDTH			4

#define DIV_CPU_WIDTH			4

#define DIV_DDR_WIDTH			4



#define BYPASS_DC_SHIFT			12

#define BYPASS_DDR_SHIFT		10

#define BYPASS_CPU_SHIFT		8



#define BYPASS_DC_WIDTH			1

#define BYPASS_DDR_WIDTH		1

#define BYPASS_CPU_WIDTH		1



#endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */