Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f2654a47 authored by Fahad Kunnathadi's avatar Fahad Kunnathadi Committed by David S. Miller
Browse files

net: phy: Fix mask value write on gmii2rgmii converter speed register 



To clear Speed Selection in MDIO control register(0x10),
ie, clear bits 6 and 13 to zero while keeping other bits same.
Before AND operation,The Mask value has to be perform with bitwise NOT
operation (ie, ~ operator)

This patch clears current speed selection before writing the
new speed settings to gmii2rgmii converter

Fixes: f411a616 ("net: phy: Add gmiitorgmii converter support")

Signed-off-by: default avatarFahad Kunnathadi <fahad.kunnathadi@dexceldesigns.com>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 76cc0d32

drivers/net/phy/xilinx_gmii2rgmii.c

+1 −1
Original line number Diff line number Diff line
@@ -44,7 +44,7 @@ static int xgmiitorgmii_read_status(struct phy_device *phydev) 
	priv->phy_drv->read_status(phydev);



	val = mdiobus_read(phydev->mdio.bus, priv->addr, XILINX_GMII2RGMII_REG);

	val &= XILINX_GMII2RGMII_SPEED_MASK;

	val &= ~XILINX_GMII2RGMII_SPEED_MASK;



	if (phydev->speed == SPEED_1000)

		val |= BMCR_SPEED1000;