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Commit f24940e0 authored by Ping Gao's avatar Ping Gao Committed by Zhenyu Wang
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drm/i915/gvt: correct the emulation in TLB control handler 



Need a explicit write_vreg in TLB MMIO write handler, beside that
TLB vreg should update correspondingly following HW status to do
correct emulation.

Signed-off-by: default avatarPing Gao <ping.a.gao@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent 5f399f11

drivers/gpu/drm/i915/gvt/handlers.c

+2 −0
Original line number Diff line number Diff line
@@ -1370,6 +1370,8 @@ static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu, 
	int rc = 0;

	unsigned int id = 0;



	write_vreg(vgpu, offset, p_data, bytes);



	switch (offset) {

	case 0x4260:

		id = RCS;

drivers/gpu/drm/i915/gvt/render.c

+2 −0
Original line number Diff line number Diff line
@@ -152,6 +152,8 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id) 


	if (wait_for_atomic((I915_READ_FW(reg) == 0), 50))

		gvt_err("timeout in invalidate ring (%d) tlb\n", ring_id);

	else

		vgpu_vreg(vgpu, regs[ring_id]) = 0;



	intel_uncore_forcewake_put(dev_priv, fw);