diff --git a/.cocciconfig b/.cocciconfig old mode 100644 new mode 100755 diff --git a/.get_maintainer.ignore b/.get_maintainer.ignore old mode 100644 new mode 100755 diff --git a/.gitattributes b/.gitattributes old mode 100644 new mode 100755 diff --git a/.gitignore b/.gitignore old mode 100644 new mode 100755 diff --git a/.mailmap b/.mailmap old mode 100644 new mode 100755 diff --git a/Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt b/Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt index c8fb809a5a0fd380e1e11195f5e6ba6b81f8837b..697ff8672a9dede52964044a52c410e35eb1c26c 100644 --- a/Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt +++ b/Documentation/devicetree/bindings/drm/msm/mdss-dsi-panel.txt @@ -164,10 +164,7 @@ Optional properties: "dfps_immediate_porch_mode_vfp" = FPS change request is implemented immediately by changing panel vertical front porch values. -- qcom,min-refresh-rate: Minimum refresh rate supported by the panel. -- qcom,max-refresh-rate: Maximum refresh rate supported by the panel. If max refresh - rate is not specified, then the frame rate of the panel in - qcom,mdss-dsi-panel-framerate is used. +- qcom,dsi-supported-dfps-list: List containing all the supported refresh rates. - qcom,mdss-dsi-bl-pmic-control-type: A string that specifies the implementation of backlight control for this panel. "bl_ctrl_pwm" = Backlight controlled by PWM gpio. @@ -545,6 +542,10 @@ Optional properties: - qcom,mdss-dsi-ext-bridge-mode: External bridge chip is connected instead of panel. - qcom,mdss-dsi-dma-schedule-line: An integer value indicates the line number after vertical active region, at which command DMA needs to be triggered. +- qcom,dsi-dyn-clk-enable: Boolean to indicate dsi dynamic clock switch feature + is supported. +- qcom,dsi-dyn-clk-list: An u32 array which lists all the supported dsi bit clock + frequencies in Hz for the given panel. Required properties for sub-nodes: None Optional properties: @@ -669,8 +670,7 @@ Example: qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_suspend_resume_mode"; - qcom,min-refresh-rate = <30>; - qcom,max-refresh-rate = <60>; + qcom,dsi-supported-dfps-list = <48 55 60>; qcom,mdss-dsi-bl-pmic-bank-select = <0>; qcom,mdss-dsi-bl-pmic-pwm-frequency = <0>; qcom,mdss-dsi-pwm-gpio = <&pm8941_mpps 5 0>; @@ -807,5 +807,7 @@ Example: <2 2 1>; qcom,default-topology-index = <0>; qcom,mdss-dsi-dma-schedule-line = <5>; + qcom,dsi-dyn-clk-enable; + qcom,dsi-dyn-clk-list = <798240576 801594528 804948480>; }; }; diff --git a/Documentation/devicetree/bindings/input/tri_state_key.txt b/Documentation/devicetree/bindings/input/tri_state_key.txt new file mode 100644 index 0000000000000000000000000000000000000000..37f9d47a8da8008252d6270130ff650661c97493 --- /dev/null +++ b/Documentation/devicetree/bindings/input/tri_state_key.txt @@ -0,0 +1,21 @@ +Tri-state key + +Required Properties: +- compatible: Must be "ompatible = "oneplus,tri-state-key". + + +Example: + + tri_state_key { + compatible = "oneplus, tri-state-key"; + status = "okay"; + interrupt-parent = <&tlmm>; + tristate,gpio_key1 = <&tlmm 125 0x00>; + tristate,gpio_key2 = <&tlmm 134 0x00>; + tristate,gpio_key3 = <&tlmm 27 0x00>; + pinctrl-names = + "pmx_tri_state_key_active", + "pmx_tri_state_key_suspend"; + pinctrl-0 = <&tri_state_key_active>; + pinctrl-1 = <&tri_state_key_suspend>; + }; diff --git a/Documentation/devicetree/bindings/sound/tfa98xx.txt b/Documentation/devicetree/bindings/sound/tfa98xx.txt new file mode 100644 index 0000000000000000000000000000000000000000..cf43fd717d5ba4f333b18b85267eb3b48e9403fe --- /dev/null +++ b/Documentation/devicetree/bindings/sound/tfa98xx.txt @@ -0,0 +1,23 @@ +Tfa98xx device + +Required Properties +- compatible Must be "compatible = "nxp,tfa98xx". + +Example: + + + &qupv3_se4_i2c { + tfa98xx_right: tfa98xx_right@34 { + compatible = "nxp,tfa98xx"; + reg = <0x34>; + reset-gpio = <&tlmm 37 0>; + status = "ok"; + }; + + tfa98xx_left: tfa98xx_left@35 { + compatible = "nxp,tfa98xx"; + reg = <0x35>; + reset-gpio = <&tlmm 37 0>; + status = "ok"; + }; + }; diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index ef8c3fd46c3f29853d0511a667f567f04221ad4e..64a51025791965878ed58d8265dea687e53f9ba5 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY_QCOM),y) dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb @@ -61,6 +62,28 @@ sm8150-sdx50m-mtp-2.5k-panel-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm815 sm8150-sdx50m-qrd-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb sm8150-sdxprairie-cdp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb sm8150-sdxprairie-mtp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +endif +endif + +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) + dtbo-$(CONFIG_ARCH_SM8150) += \ + sm8150-mtp-overlay.dtbo \ + guacamole-overlay-t0.dtbo \ + guacamole-overlay-evt1.dtbo \ + guacamole-overlay-evt2.dtbo \ + guacamole-overlay-evt2-second.dtbo \ + guacamole-overlay-evt3.dtbo \ + guacamole-overlay-dvt.dtbo \ + guacamole-overlay-pvt.dtbo + +sm8150-mtp-overlay.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-t0.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-evt1.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-evt2.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-evt2-second.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-evt3.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-dvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb +guacamole-overlay-pvt.dtbo-base := sm8150.dtb sm8150-v2.dtb sm8150p.dtb sm8150p-v2.dtb else dtb-$(CONFIG_ARCH_SM8150) += sm8150-rumi.dtb \ sm8150-mtp.dtb \ diff --git a/arch/arm64/boot/dts/qcom/OP-fg-batterydata-3700mah.dtsi b/arch/arm64/boot/dts/qcom/OP-fg-batterydata-3700mah.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..131fb2dc9e0dc730ec1799455de1d4b1caac1582 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/OP-fg-batterydata-3700mah.dtsi @@ -0,0 +1,144 @@ +/* Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +qcom,OP_3700mAh { + qcom,max-voltage-uv = <4370000>; + qcom,fastchg-current-ma = <3000>; + qcom,jeita-fcc-ranges = <0 100 2500000 + 110 400 5400000 + 410 450 2500000>; + qcom,jeita-fv-ranges = <0 100 4250000 + 110 400 4350000 + 410 450 4250000>; + qcom,step-chg-ranges = <3600000 3800000 5400000 + 3801000 4300000 3600000 + 4301000 4350000 2500000>; + qcom,ocv-based-step-chg; + qcom,batt-id-kohm = <200>; + qcom,battery-beta = <4250>; + qcom,therm-room-temp = <100000>; + qcom,fg-cc-cv-threshold-mv = <4340>; + qcom,battery-type = "OP_3700mAh"; + qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; + qcom,therm-center-offset = <0x70>; + qcom,therm-pull-up = <100>; + qcom,rslow-normal-coeffs = <0xdf 0x02 0x77 0x1a>; + qcom,rslow-low-coeffs = <0x51 0x04 0xd0 0x13>; + qcom,checksum = <0x1538>; + qcom,gui-version = "PM855GUI - 1.0.0.10"; + qcom,fg-profile-data = [ + 09 00 C7 EA + C4 DC 8E E2 + 3A DD 00 00 + 15 BC A5 8A + 02 80 D1 92 + AB 9D 47 80 + 10 00 DF 02 + 77 1A 85 EC + E1 FD CE 07 + 32 00 75 EB + AA ED F3 CD + 0C 0A 7A E4 + ED C5 40 1B + D0 02 1F CA + FF 00 52 00 + 4D 00 4A 00 + 3C 00 35 00 + 38 00 39 00 + 48 00 43 00 + 3F 00 FF 00 + 38 00 40 00 + 46 00 50 00 + 45 00 5C 00 + 7E 64 60 00 + 50 08 50 10 + FF 00 6A 00 + 5F 00 63 00 + 6E 00 60 00 + 7D 20 96 40 + 75 50 6B 13 + 63 00 D8 00 + 14 22 7E 0D + 21 02 AA 04 + ED 1C D4 09 + 64 0C D3 23 + A4 18 D3 42 + B5 55 91 02 + 90 12 2A 1F + 02 06 1F 0A + A3 06 AE 1C + 8D 02 96 04 + D2 03 D1 17 + 51 23 3F 45 + 28 53 69 14 + 93 20 8E EC + 18 CB C8 C5 + DB 1C 7B C9 + 7C 05 E6 C2 + B9 17 2C 93 + 87 85 A2 92 + 91 A8 09 80 + 92 F2 1A 0D + F4 FC 5E EB + 00 F8 FB ED + 15 E2 F6 0F + 75 02 72 05 + 49 01 10 00 + FA E5 E2 03 + 8D 05 85 02 + CE 07 32 00 + 23 03 46 02 + 9C 04 03 02 + 48 07 0A 00 + BA 03 97 02 + 65 05 50 00 + 3A 00 41 00 + 43 64 45 00 + 45 10 45 18 + 46 08 44 00 + 47 00 3A 08 + 4B 08 37 00 + 47 20 4E 40 + 54 58 60 10 + 57 00 5F 00 + 57 08 55 00 + 4B 00 50 00 + 3E 08 52 08 + 52 00 5C 20 + 6F 40 7D 58 + 67 10 63 00 + 69 08 4F 10 + D8 00 8C 2A + DB 04 28 02 + AD 04 0B 1D + 50 22 A7 45 + 0D 52 A2 18 + 74 03 AD 04 + 35 02 AE 13 + 3F 0A 5A 20 + DD 04 F1 02 + D8 05 C7 1C + DD 02 3D 04 + EB 03 97 18 + 52 03 D5 04 + 19 02 72 00 + 14 22 7E 05 + 21 02 AA 04 + ED 1C D4 01 + 64 04 D3 03 + A4 18 D3 02 + B5 05 91 02 + 90 00 7C 01 + C0 00 FA 00 + 04 0E 00 00 + ]; +}; diff --git a/arch/arm64/boot/dts/qcom/OP-fg-batterydata-4000mah.dtsi b/arch/arm64/boot/dts/qcom/OP-fg-batterydata-4000mah.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..3f0116c033bab78eecd8028b4b4181c19cfd6f67 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/OP-fg-batterydata-4000mah.dtsi @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +qcom,OP_4000mAh { + qcom,max-voltage-uv = <4370000>; + qcom,fastchg-current-ma = <3000>; + qcom,jeita-fcc-ranges = <0 100 2500000 + 110 400 5400000 + 410 450 2500000>; + qcom,jeita-fv-ranges = <0 100 4250000 + 110 400 4350000 + 410 450 4250000>; + qcom,step-chg-ranges = <3600000 3800000 5400000 + 3801000 4300000 3600000 + 4301000 4350000 2500000>; + qcom,ocv-based-step-chg; + qcom,batt-id-kohm = <200>; + qcom,battery-beta = <4250>; + qcom,therm-room-temp = <100000>; + qcom,fg-cc-cv-threshold-mv = <4340>; + qcom,battery-type = "OP_4000mAh "; + qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>; + qcom,therm-center-offset = <0x70>; + qcom,therm-pull-up = <100>; + qcom,rslow-normal-coeffs = <0xdf 0x02 0x77 0x1a>; + qcom,rslow-low-coeffs = <0x51 0x04 0xd0 0x13>; + qcom,checksum = <0x1538>; + qcom,gui-version = "PM855GUI - 1.0.0.10"; + qcom,fg-profile-data = [ + 09 00 C7 EA + C4 DC 8E E2 + 3A DD 00 00 + 15 BC A5 8A + 02 80 D1 92 + AB 9D 47 80 + 10 00 DF 02 + 77 1A 85 EC + E1 FD CE 07 + 32 00 75 EB + AA ED F3 CD + 0C 0A 7A E4 + ED C5 40 1B + D0 02 1F CA + FF 00 52 00 + 4D 00 4A 00 + 3C 00 35 00 + 38 00 39 00 + 48 00 43 00 + 3F 00 FF 00 + 38 00 40 00 + 46 00 50 00 + 45 00 5C 00 + 7E 64 60 00 + 50 08 50 10 + FF 00 6A 00 + 5F 00 63 00 + 6E 00 60 00 + 7D 20 96 40 + 75 50 6B 13 + 63 00 D8 00 + 14 22 7E 0D + 21 02 AA 04 + ED 1C D4 09 + 64 0C D3 23 + A4 18 D3 42 + B5 55 91 02 + 90 12 2A 1F + 02 06 1F 0A + A3 06 AE 1C + 8D 02 96 04 + D2 03 D1 17 + 51 23 3F 45 + 28 53 69 14 + 93 20 8E EC + 18 CB C8 C5 + DB 1C 7B C9 + 7C 05 E6 C2 + B9 17 2C 93 + 87 85 A2 92 + 91 A8 09 80 + 92 F2 1A 0D + F4 FC 5E EB + 00 F8 FB ED + 15 E2 F6 0F + 75 02 72 05 + 49 01 10 00 + FA E5 E2 03 + 8D 05 85 02 + CE 07 32 00 + 23 03 46 02 + 9C 04 03 02 + 48 07 0A 00 + BA 03 97 02 + 65 05 50 00 + 3A 00 41 00 + 43 64 45 00 + 45 10 45 18 + 46 08 44 00 + 47 00 3A 08 + 4B 08 37 00 + 47 20 4E 40 + 54 58 60 10 + 57 00 5F 00 + 57 08 55 00 + 4B 00 50 00 + 3E 08 52 08 + 52 00 5C 20 + 6F 40 7D 58 + 67 10 63 00 + 69 08 4F 10 + D8 00 8C 2A + DB 04 28 02 + AD 04 0B 1D + 50 22 A7 45 + 0D 52 A2 18 + 74 03 AD 04 + 35 02 AE 13 + 3F 0A 5A 20 + DD 04 F1 02 + D8 05 C7 1C + DD 02 3D 04 + EB 03 97 18 + 52 03 D5 04 + 19 02 72 00 + 14 22 7E 05 + 21 02 AA 04 + ED 1C D4 01 + 64 04 D3 03 + A4 18 D3 02 + B5 05 91 02 + 90 00 7C 01 + C0 00 FA 00 + 04 0E 00 00 + ]; +}; diff --git a/arch/arm64/boot/dts/qcom/dsi-panel-samsung-sofef00_m-fhd-video.dtsi b/arch/arm64/boot/dts/qcom/dsi-panel-samsung-sofef00_m-fhd-video.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..106155b52befb3bc42195d4874a528c13831da34 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/dsi-panel-samsung-sofef00_m-fhd-video.dtsi @@ -0,0 +1,103 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_samsung_sofef00_m_video: qcom,mdss_dsi_samsung_sofef00_m_video { + qcom,mdss-dsi-panel-name = "samsung sofef00_m video mode dsi panel"; + qcom,mdss-dsi-panel-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-version = "SOFEF00M"; + qcom,mdss-dsi-backlight-version = "SAMSUNG"; + qcom,mdss-dsi-backlight-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-reset-sequence = <1 5>, <0 2>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <145>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-high-brightness-panel; + qcom,mdss-bl-high2bit; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2280>; + qcom,mdss-dsi-h-front-porch = <100>; + qcom,mdss-dsi-h-back-porch = <24>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <18>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-on-command = [ + 05 01 00 00 0A 00 02 11 00 + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 F0 A5 A5 + 15 01 00 00 00 00 02 53 20 + 15 01 00 00 00 00 02 55 00 + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 28 00 01 28 + 05 01 00 00 82 00 01 10 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + }; + }; + }; +}; + +&dsi_samsung_sofef00_m_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&soc { + dsi_samsung_sofef00_m_video_display { + qcom,dsi-display-active; + }; +}; + +&dsi_samsung_sofef00_m_video { + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 25 23 + 09 09 06 03 04 00 1C 19]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/qcom/dsi-panel-samsung_oneplus_dsc.dtsi b/arch/arm64/boot/dts/qcom/dsi-panel-samsung_oneplus_dsc.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..c0f4d1573c25f7b7826f8f256d9bb92e03511e90 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/dsi-panel-samsung_oneplus_dsc.dtsi @@ -0,0 +1,2573 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_samsung_oneplus_dsc_cmd: qcom,mdss_dsi_samsung_oneplus_dsc_cmd { + qcom,mdss-dsi-panel-name = "samsung dsc cmd mode oneplus dsi panel"; + qcom,mdss-dsi-panel-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-version = "DSC"; + qcom,mdss-dsi-backlight-version = "SAMSUNG"; + qcom,mdss-dsi-backlight-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-reset-sequence = <1 10>, <0 2>, <1 5>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-color-order = "rgb_swap_rgb"; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-lane-map = "lane_map_0123"; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-default-val = <200>; + qcom,mdss-brightness-max-level = <1023>; + qcom,mdss-pan-physical-width-dimension = <71>; + qcom,mdss-pan-physical-height-dimension = <154>; + qcom,mdss-dsi-init-delay-us = <1000>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-high-brightness-panel; + qcom,mdss-dsi-acl-cmd-index = <0>; + qcom,mdss-dsi-acl-mode-index = <1>; + qcom,mdss-bl-high2bit; + qcom,mdss-dsi-panel-jitter = <0x8 0xa>; + qcom,dynamic-mode-switch-enabled; + qcom,dynamic-mode-switch-type = "dynamic-resolution-switch-immediate"; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + /* HDR Setting */ + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15635 16450 34000 16000 13250 34500 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <5400000>; + qcom,mdss-dsi-panel-average-brightness = <2000000>; + qcom,mdss-dsi-panel-blackness-level = <2000>; + qcom,mdss-dsi-panel-seria-num-year-index = <12>; + qcom,mdss-dsi-panel-seria-num-mon-index = <12>; + qcom,mdss-dsi-panel-seria-num-day-index = <13>; + qcom,mdss-dsi-panel-seria-num-hour-index = <14>; + qcom,mdss-dsi-panel-seria-num-min-index = <15>; + qcom,mdss-dsi-panel-seria-num-sec-index = <16>; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 00]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9F>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-id1-command = [06 01 00 00 00 00 02 0A 00]; + qcom,mdss-dsi-panel-id2-command = [06 01 00 00 00 00 02 0E 00]; + qcom,mdss-dsi-panel-id3-command = [06 01 00 00 00 00 02 0F 00]; + qcom,mdss-dsi-panel-id4-command = [06 01 00 00 00 00 02 C4 00]; + qcom,mdss-dsi-panel-id5-command = [06 01 00 00 00 00 02 E7 00]; + qcom,mdss-dsi-panel-id6-command = [06 01 00 00 00 00 02 EA 00]; + qcom,mdss-dsi-panel-id7-command = [06 01 00 00 00 00 02 FB 00]; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-read-esd-registed-longread-command = [ + 37 01 00 00 05 00 02 22 00 + ]; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id4-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id5-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id6-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id7-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-esd-registed-longread-command-state = "dsi_lp_mode"; + + /* + * ************************************************************************************************************************ + * DMS (Dynamic Mode Switch) + * ************************************************************************************************************************ + */ + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,mdss-mdp-transfer-time-us = <8000>; //for 60fps + qcom,mdss-dsi-timing-default; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-clockrate = <1107000000>; + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 24 0A 0A 06 02 04 00 1E 1A]; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3120>; + qcom,mdss-dsi-h-front-porch = <16>; + qcom,mdss-dsi-h-back-porch = <8>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <1156>; + qcom,mdss-dsi-v-front-porch = <400>; + qcom,mdss-dsi-v-pulse-width = <28>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x8 0xa>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 00]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9F>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-id1-command = [06 01 00 00 00 00 02 0A 00]; + qcom,mdss-dsi-panel-id2-command = [06 01 00 00 00 00 02 0E 00]; + qcom,mdss-dsi-panel-id3-command = [06 01 00 00 00 00 02 0F 00]; + qcom,mdss-dsi-panel-id4-command = [06 01 00 00 00 00 02 C4 00]; + qcom,mdss-dsi-panel-id5-command = [06 01 00 00 00 00 02 E7 00]; + qcom,mdss-dsi-panel-id6-command = [06 01 00 00 00 00 02 EA 00]; + qcom,mdss-dsi-panel-id7-command = [06 01 00 00 00 00 02 FB 00]; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-read-esd-registed-longread-command = [ + 37 01 00 00 05 00 02 22 00 + ]; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id4-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id5-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id6-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id7-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-esd-registed-longread-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-timing-switch-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + //29 01 00 00 00 00 03 9F A5 A5 + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 00 /* Scaler disable */ + 29 01 00 00 00 00 05 2A 00 00 05 9F /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 0C 2F /* PASET */ + 39 01 00 00 00 00 5A 0A /* PPS Setting (1440 x 3120) (initial value) */ + 10 00 00 89 30 80 0C 30 + 05 A0 00 41 02 D0 02 D0 + 02 00 02 C2 00 20 06 58 + 00 0A 00 0F 01 E0 01 2D + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A B6 + 2A F4 2A F4 4B 34 63 74 + 00 + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + //29 01 00 00 00 00 03 9F 5A 5A + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-t-clk-pre = <0x1E>; + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-on-command = [ + /* DSC Setting */ + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 00 /* Scaler disable */ + 39 01 00 00 00 00 5A 0A /* PPS Setting (1440 x 3120) (initial value) */ + 10 00 00 89 30 80 0C 30 + 05 A0 00 41 02 D0 02 D0 + 02 00 02 C2 00 20 06 58 + 00 0A 00 0F 01 E0 01 2D + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A B6 + 2A F4 2A F4 4B 34 63 74 + 00 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 39 01 00 00 00 00 05 2A 00 00 05 9F /* CASET */ + 39 01 00 00 00 00 05 2B 00 00 0C 2F /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 09 10 B4 24 D9 /* FFC Setting; 0x09 : Enable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame*/ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-113mhz-osc-dsi-on-command = [ + /* DSC Setting */ + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 00 /* Scaler disable */ + 39 01 00 00 00 00 5A 0A /* PPS Setting (1440 x 3120) (initial value) */ + 10 00 00 89 30 80 0C 30 + 05 A0 00 41 02 D0 02 D0 + 02 00 02 C2 00 20 06 58 + 00 0A 00 0F 01 E0 01 2D + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A B6 + 2A F4 2A F4 4B 34 63 74 + 00 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 39 01 00 00 00 00 05 2A 00 00 05 9F /* CASET */ + 39 01 00 00 00 00 05 2B 00 00 0C 2F /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 09 10 B4 24 D9 /* FFC Setting; 0x09 : Enable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame*/ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-113mhz-osc-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-off-command=[ + 05 01 00 00 0A 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + ]; + qcom,mdss-dsi-panel-hbm-brightness-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 53 /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM Mode ON */ + 15 01 00 00 11 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-brightness-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 53 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 11 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-hbm-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-3 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-4 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-5 = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 14 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 29 01 00 00 0D 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* 90Hz Setting */ + 15 01 00 00 11 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + ]; + qcom,mdss-dsi-panel-serial-num-pre-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 37 01 00 00 05 00 02 10 00 + ]; + qcom,mdss-dsi-panel-serial-num-command = [ + 06 01 00 00 00 00 01 A1 00 + ]; + qcom,mdss-dsi-panel-stage-info-command = [ + 06 01 00 00 00 00 01 DB 00 + ]; + qcom,mdss-dsi-panel-production-info-command = [ + 06 01 00 00 00 00 01 DC 00 + ]; + qcom,mdss-dsi-panel-serial-num-post-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-aod-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-aod-off-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-samsung-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-new-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-hbm-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 29 01 00 00 00 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-aod-on-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command = [ + /*Level2 key Enable*/ + 29 01 00 00 00 00 03 F0 5A 5A + //07 01 00 00 00 00 01 01 + //29 00 00 00 00 00 05 2A 00 00 05 9F + //29 00 00 00 00 00 05 2B 00 00 0C 2F + /*OTP key Enable*/ + 29 01 00 00 00 00 03 F1 F1 A2 + 29 01 00 00 00 00 0D C1 00 00 00 06 00 00 00 00 00 00 00 05 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0C C1 00 00 00 01 40 02 00 00 00 00 10 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0E C1 00 00 00 6B 00 00 00 0A 00 00 00 05 01 + 15 01 00 00 00 00 02 B0 07 + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command = [ + 15 01 00 00 00 00 02 C0 03 + 15 01 00 00 00 00 02 B0 08 + ]; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command = [ + /*13th Parameter : 1byte Read value*/ + 06 01 00 00 00 00 02 FB 00 + ]; + qcom,mdss-dsi-panel-level2-key-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command = [ + 37 01 00 00 05 00 02 87 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command = [ + 06 01 00 00 00 00 02 C8 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command = [ + 37 01 00 00 00 00 02 B4 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command = [ + 06 01 00 00 00 00 02 C9 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command = [ + 37 01 00 00 00 00 02 2F 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command = [ + 06 01 00 00 00 00 02 B3 00 + ]; + qcom,mdss-dsi-panel-level2-key-disable-command = [ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-night-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 E5 08 00 86 FF 00 04 03 F8 1B F0 E8 E9 03 ED DD F0 00 FF FE E4 + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-p3-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 D3 03 00 11 E4 01 0B 06 F0 1A FA FC E5 09 F6 EA F3 01 FC FF EA + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-dci-p3-off-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 03 67 00 01 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-laoding-effect-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 81 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 FF 6D + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-laoding-effect-disable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 A1 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 28 28 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-srgb-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 0A 00 02 B0 02 + 29 01 00 00 0A 00 16 67 EA 12 06 4A F4 14 09 02 BF 47 FC DC D3 0B E5 D2 F6 14 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 0A 00 02 B0 02 + 29 01 00 00 0A 00 16 67 FF 05 00 0B EB 00 07 00 FF 14 F8 EA F0 03 F5 DE F5 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-customer-srgb-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-laoding-effect-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-laoding-effect-disable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-p3-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-night-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-dci-p3-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-new-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-samsung-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-hbm-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-aod-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-pre-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-state-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-production-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-post-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-brightness-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-brightness-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-3-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-4-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-5-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-disable-command-state = "dsi_lp_mode"; + qcom,panel-roi-alignment=<720 65 720 65 720 65>; + qcom,compression-mode = "dsc"; + qcom,lm-split = <720 720>; + qcom,mdss-dsc-encoders = <2>; + qcom,mdss-dsc-slice-height = <65>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@1{ + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,mdss-mdp-transfer-time-us = <8000>; //for 90fps + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-clockrate = <1107000000>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2336>; + qcom,mdss-dsi-h-front-porch = <16>; + qcom,mdss-dsi-h-back-porch = <8>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <4>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x8 0xa>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 00]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9F>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-id1-command = [06 01 00 00 00 00 02 0A 00]; + qcom,mdss-dsi-panel-id2-command = [06 01 00 00 00 00 02 0E 00]; + qcom,mdss-dsi-panel-id3-command = [06 01 00 00 00 00 02 0F 00]; + qcom,mdss-dsi-panel-id4-command = [06 01 00 00 00 00 02 C4 00]; + qcom,mdss-dsi-panel-id5-command = [06 01 00 00 00 00 02 E7 00]; + qcom,mdss-dsi-panel-id6-command = [06 01 00 00 00 00 02 EA 00]; + qcom,mdss-dsi-panel-id7-command = [06 01 00 00 00 00 02 FB 00]; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 F0 5A 5A]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-panel-read-esd-registed-longread-command = [ + 37 01 00 00 05 00 02 22 00 + ]; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id4-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id5-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id6-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id7-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-esd-registed-longread-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-timing-switch-command = [ + 29 01 00 00 00 00 03 F0 5A 5A /* Level2 key Access Enable */ + //29 01 00 00 00 00 03 9F A5 A5 /* Level1 key Access Enable */ + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 01 /* Scaler enable(x1.78) */ + 29 01 00 00 00 00 05 2A 00 00 04 37 /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 09 1F /* PASET */ + 39 01 00 00 00 00 59 0A /* PPS Setting (1080 x 2336) */ + 11 00 00 89 30 80 09 20 + 04 38 00 49 02 1C 02 1C + 02 00 02 0E 00 20 07 16 + 00 07 00 0C 01 56 01 65 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + //29 01 00 00 00 00 03 9F 5A 5A + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 24 0A 0A 06 02 04 00 1E 1A]; + qcom,mdss-dsi-t-clk-pre = <0x1E>; + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-on-command = [ + /* DSC Setting */ + 29 01 00 00 00 00 03 F0 5A 5A + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 01 /* Scaler enable(x1.78) */ + 39 01 00 00 00 00 59 0A /* PPS Setting (1080 x 2336) */ + 11 00 00 89 30 80 09 20 + 04 38 00 49 02 1C 02 1C + 02 00 02 0E 00 20 07 16 + 00 07 00 0C 01 56 01 65 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 29 01 00 00 00 00 03 F0 A5 A5 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 29 01 00 00 00 00 05 2A 00 00 04 37 /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 09 1F /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 09 10 B4 24 D9 /* FFC Setting; 0x09 : Enable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame */ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-113mhz-osc-dsi-on-command = [ + /* DSC Setting */ + 29 01 00 00 00 00 03 F0 5A 5A + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 01 /* Scaler enable(x1.78) */ + 39 01 00 00 00 00 59 0A /* PPS Setting (1080 x 2336) */ + 11 00 00 89 30 80 09 20 + 04 38 00 49 02 1C 02 1C + 02 00 02 0E 00 20 07 16 + 00 07 00 0C 01 56 01 65 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 29 01 00 00 00 00 03 F0 A5 A5 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 29 01 00 00 00 00 05 2A 00 00 04 37 /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 09 1F /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 09 10 B4 24 D9 /* FFC Setting; 0x09 : Enable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame */ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-113mhz-osc-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-off-command=[ + 05 01 00 00 0A 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + ]; + qcom,mdss-dsi-panel-hbm-brightness-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 53 /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM Mode ON */ + 15 01 00 00 0C 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-brightness-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 53 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 0C 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-hbm-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-3 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-4 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-5 = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 10 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 29 01 00 00 0C 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* 90Hz Setting */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-serial-num-pre-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 37 01 00 00 05 00 02 10 00 + ]; + qcom,mdss-dsi-panel-serial-num-command = [ + 06 01 00 00 00 00 01 A1 00 + ]; + qcom,mdss-dsi-panel-stage-info-command = [ + 06 01 00 00 00 00 01 DB 00 + ]; + qcom,mdss-dsi-panel-production-info-command = [ + 06 01 00 00 00 00 01 DC 00 + ]; + qcom,mdss-dsi-panel-serial-num-post-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-aod-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-aod-off-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-samsung-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-new-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-hbm-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 29 01 00 00 00 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* 90Hz Setting */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-off-aod-on-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command = [ + /*Level2 key Enable*/ + 29 01 00 00 00 00 03 F0 5A 5A + //07 01 00 00 00 00 01 01 + //29 00 00 00 00 00 05 2A 00 00 05 9F + //29 00 00 00 00 00 05 2B 00 00 0C 2F + /*OTP key Enable*/ + 29 01 00 00 00 00 03 F1 F1 A2 + 29 01 00 00 00 00 0D C1 00 00 00 06 00 00 00 00 00 00 00 05 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0C C1 00 00 00 01 40 02 00 00 00 00 10 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0E C1 00 00 00 6B 00 00 00 0A 00 00 00 05 01 + 15 01 00 00 00 00 02 B0 07 + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command = [ + 15 01 00 00 00 00 02 C0 03 + 15 01 00 00 00 00 02 B0 08 + ]; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command = [ + /*13th Parameter : 1byte Read value*/ + 06 01 00 00 00 00 02 FB 00 + ]; + qcom,mdss-dsi-panel-level2-key-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command = [ + 37 01 00 00 00 00 02 87 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command = [ + 06 01 00 00 00 00 02 C8 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command = [ + 37 01 00 00 00 00 02 B4 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command = [ + 06 01 00 00 00 00 02 C9 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command = [ + 37 01 00 00 00 00 02 2F 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command = [ + 06 01 00 00 00 00 02 B3 00 + ]; + qcom,mdss-dsi-panel-level2-key-disable-command = [ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-night-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 E5 08 00 86 FF 00 04 03 F8 1B F0 E8 E9 03 ED DD F0 00 FF FE E4 + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-p3-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 D3 03 00 11 E4 01 0B 06 F0 1A FA FC E5 09 F6 EA F3 01 FC FF EA + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-dci-p3-off-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 03 67 00 01 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-laoding-effect-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 81 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 FF 6D + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-laoding-effect-disable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 A1 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 28 28 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-srgb-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 0A 00 02 B0 02 + 29 01 00 00 0A 00 16 67 EA 12 06 4A F4 14 09 02 BF 47 FC DC D3 0B E5 D2 F6 14 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 0A 00 02 B0 02 + 29 01 00 00 0A 00 16 67 FF 05 00 0B EB 00 07 00 FF 14 F8 EA F0 03 F5 DE F5 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-customer-srgb-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-laoding-effect-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-laoding-effect-disable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-p3-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-night-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-dci-p3-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-new-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-samsung-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-hbm-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-aod-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-pre-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-state-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-production-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-post-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-brightness-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-brightness-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-3-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-4-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-5-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-disable-command-state = "dsi_lp_mode"; + qcom,panel-roi-alignment=<540 73 540 73 540 73>; + qcom,compression-mode = "dsc"; + qcom,lm-split = <540 540>; + qcom,mdss-dsc-encoders = <2>; + qcom,mdss-dsc-slice-height = <73>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@2{ + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,mdss-mdp-transfer-time-us = <8000>; //for 60fps + qcom,mdss-dsi-timing-default; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-clockrate = <1107000000>; + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 24 0A 0A 06 02 04 00 1E 1A]; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2336>; + qcom,mdss-dsi-h-front-porch = <16>; + qcom,mdss-dsi-h-back-porch = <8>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <1156>; + qcom,mdss-dsi-v-front-porch = <400>; + qcom,mdss-dsi-v-pulse-width = <28>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x8 0xa>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 00]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9F>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-id1-command = [06 01 00 00 00 00 02 0A 00]; + qcom,mdss-dsi-panel-id2-command = [06 01 00 00 00 00 02 0E 00]; + qcom,mdss-dsi-panel-id3-command = [06 01 00 00 00 00 02 0F 00]; + qcom,mdss-dsi-panel-id4-command = [06 01 00 00 00 00 02 C4 00]; + qcom,mdss-dsi-panel-id5-command = [06 01 00 00 00 00 02 E7 00]; + qcom,mdss-dsi-panel-id6-command = [06 01 00 00 00 00 02 EA 00]; + qcom,mdss-dsi-panel-id7-command = [06 01 00 00 00 00 02 FB 00]; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-read-esd-registed-longread-command = [ + 37 01 00 00 05 00 02 22 00 + ]; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id4-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id5-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id6-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id7-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-esd-registed-longread-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-timing-switch-command = [ + 29 01 00 00 00 00 03 F0 5A 5A /* Level2 key Access Enable */ + //29 01 00 00 00 00 03 9F A5 A5 /* Level1 key Access Enable */ + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 01 /* Scaler enable(x1.78) */ + 29 01 00 00 00 00 05 2A 00 00 04 37 /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 09 1F /* PASET */ + 39 01 00 00 00 00 59 0A /* PPS Setting (1080 x 2336) */ + 11 00 00 89 30 80 09 20 + 04 38 00 49 02 1C 02 1C + 02 00 02 0E 00 20 07 16 + 00 07 00 0C 01 56 01 65 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + //29 01 00 00 00 00 03 9F 5A 5A + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-t-clk-pre = <0x1E>; + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-on-command = [ + /* DSC Setting */ + 29 01 00 00 00 00 03 F0 5A 5A + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 01 /* Scaler enable(x1.78) */ + 39 01 00 00 00 00 59 0A /* PPS Setting (1080 x 2336) */ + 11 00 00 89 30 80 09 20 + 04 38 00 49 02 1C 02 1C + 02 00 02 0E 00 20 07 16 + 00 07 00 0C 01 56 01 65 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 29 01 00 00 00 00 03 F0 A5 A5 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 29 01 00 00 00 00 05 2A 00 00 04 37 /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 09 1F /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 09 10 B4 24 D9 /* FFC Setting; 0x09 : Enable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame */ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-113mhz-osc-dsi-on-command = [ + /* DSC Setting */ + 29 01 00 00 00 00 03 F0 5A 5A + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 01 /* Scaler enable(x1.78) */ + 39 01 00 00 00 00 59 0A /* PPS Setting (1080 x 2336) */ + 11 00 00 89 30 80 09 20 + 04 38 00 49 02 1C 02 1C + 02 00 02 0E 00 20 07 16 + 00 07 00 0C 01 56 01 65 + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A F6 + 2B 34 2B 74 3B 74 6B F4 + 29 01 00 00 00 00 03 F0 A5 A5 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 29 01 00 00 00 00 05 2A 00 00 04 37 /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 09 1F /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 09 10 B4 24 D9 /* FFC Setting; 0x09 : Enable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame */ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-113mhz-osc-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-off-command=[ + 05 01 00 00 0A 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + ]; + qcom,mdss-dsi-panel-hbm-brightness-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 53 /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM Mode ON */ + 15 01 00 00 11 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-brightness-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 53 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 11 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-hbm-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-3 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-4 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-5 = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 14 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 29 01 00 00 0D 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* 90Hz Setting */ + 15 01 00 00 11 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + 15 01 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + ]; + qcom,mdss-dsi-panel-serial-num-pre-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 37 01 00 00 05 00 02 10 00 + ]; + qcom,mdss-dsi-panel-serial-num-command = [ + 06 01 00 00 00 00 01 A1 00 + ]; + qcom,mdss-dsi-panel-stage-info-command = [ + 06 01 00 00 00 00 01 DB 00 + ]; + qcom,mdss-dsi-panel-production-info-command = [ + 06 01 00 00 00 00 01 DC 00 + ]; + qcom,mdss-dsi-panel-serial-num-post-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-aod-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-aod-off-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-samsung-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-new-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-hbm-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 20 /* 0x20 Normal transition(60Hz) */ + 29 01 00 00 00 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-aod-on-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command = [ + /*Level2 key Enable*/ + 29 01 00 00 00 00 03 F0 5A 5A + //07 01 00 00 00 00 01 01 + //29 00 00 00 00 00 05 2A 00 00 05 9F + //29 00 00 00 00 00 05 2B 00 00 0C 2F + /*OTP key Enable*/ + 29 01 00 00 00 00 03 F1 F1 A2 + 29 01 00 00 00 00 0D C1 00 00 00 06 00 00 00 00 00 00 00 05 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0C C1 00 00 00 01 40 02 00 00 00 00 10 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0E C1 00 00 00 6B 00 00 00 0A 00 00 00 05 01 + 15 01 00 00 00 00 02 B0 07 + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command = [ + 15 01 00 00 00 00 02 C0 03 + 15 01 00 00 00 00 02 B0 08 + ]; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command = [ + /*13th Parameter : 1byte Read value*/ + 06 01 00 00 00 00 02 FB 00 + ]; + qcom,mdss-dsi-panel-level2-key-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command = [ + 37 01 00 00 05 00 02 87 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command = [ + 06 01 00 00 00 00 02 C8 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command = [ + 37 01 00 00 00 00 02 B4 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command = [ + 06 01 00 00 00 00 02 C9 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command = [ + 37 01 00 00 00 00 02 2F 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command = [ + 06 01 00 00 00 00 02 B3 00 + ]; + qcom,mdss-dsi-panel-level2-key-disable-command = [ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-night-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 E5 08 00 86 FF 00 04 03 F8 1B F0 E8 E9 03 ED DD F0 00 FF FE E4 + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-p3-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 D3 03 00 11 E4 01 0B 06 F0 1A FA FC E5 09 F6 EA F3 01 FC FF EA + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-dci-p3-off-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 03 67 00 01 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-laoding-effect-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 81 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 FF 6D + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-laoding-effect-disable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 A1 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 28 28 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-srgb-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 0A 00 02 B0 02 + 29 01 00 00 0A 00 16 67 EA 12 06 4A F4 14 09 02 BF 47 FC DC D3 0B E5 D2 F6 14 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 0A 00 02 B0 02 + 29 01 00 00 0A 00 16 67 FF 05 00 0B EB 00 07 00 FF 14 F8 EA F0 03 F5 DE F5 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-customer-srgb-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-laoding-effect-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-laoding-effect-disable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-p3-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-night-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-dci-p3-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-new-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-samsung-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-hbm-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-aod-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-pre-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-state-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-production-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-post-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-brightness-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-brightness-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-3-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-4-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-5-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-disable-command-state = "dsi_lp_mode"; + qcom,panel-roi-alignment=<540 73 540 73 540 73>; + qcom,compression-mode = "dsc"; + qcom,lm-split = <540 540>; + qcom,mdss-dsc-encoders = <2>; + qcom,mdss-dsc-slice-height = <73>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + timing@3{ + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,mdss-mdp-transfer-time-us = <8000>; //for 90fps + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-clockrate = <1107000000>; + qcom,mdss-dsi-panel-width = <1440>; + qcom,mdss-dsi-panel-height = <3120>; + qcom,mdss-dsi-h-front-porch = <16>; + qcom,mdss-dsi-h-back-porch = <8>; + qcom,mdss-dsi-h-pulse-width = <8>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <8>; + qcom,mdss-dsi-v-front-porch = <4>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x8 0xa>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 00]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9F>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-id1-command = [06 01 00 00 00 00 02 0A 00]; + qcom,mdss-dsi-panel-id2-command = [06 01 00 00 00 00 02 0E 00]; + qcom,mdss-dsi-panel-id3-command = [06 01 00 00 00 00 02 0F 00]; + qcom,mdss-dsi-panel-id4-command = [06 01 00 00 00 00 02 C4 00]; + qcom,mdss-dsi-panel-id5-command = [06 01 00 00 00 00 02 E7 00]; + qcom,mdss-dsi-panel-id6-command = [06 01 00 00 00 00 02 EA 00]; + qcom,mdss-dsi-panel-id7-command = [06 01 00 00 00 00 02 FB 00]; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 F0 5A 5A]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 F0 A5 A5]; + qcom,mdss-dsi-panel-read-esd-registed-longread-command = [ + 37 01 00 00 05 00 02 22 00 + ]; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id4-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id5-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id6-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id7-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-esd-registed-longread-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-timing-switch-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + //29 01 00 00 00 00 03 9F A5 A5 + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 00 /* Scaler disable */ + 29 01 00 00 00 00 05 2A 00 00 05 9F /* CASET */ + 29 01 00 00 00 00 05 2B 00 00 0C 2F /* PASET */ + 39 01 00 00 00 00 5A 0A /* PPS Setting (1440 x 3120) (initial value) */ + 10 00 00 89 30 80 0C 30 + 05 A0 00 41 02 D0 02 D0 + 02 00 02 C2 00 20 06 58 + 00 0A 00 0F 01 E0 01 2D + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A B6 + 2A F4 2A F4 4B 34 63 74 + 00 + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + //29 01 00 00 00 00 03 9F 5A 5A + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 24 0A 0A 06 02 04 00 1E 1A]; + qcom,mdss-dsi-t-clk-pre = <0x1E>; + qcom,mdss-dsi-t-clk-post = <0x1A>; + qcom,mdss-dsi-on-command = [ + /* DSC Setting */ + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 00 /* Scaler disable */ + 39 01 00 00 00 00 5A 0A /* PPS Setting (1440 x 3120) (initial value) */ + 10 00 00 89 30 80 0C 30 + 05 A0 00 41 02 D0 02 D0 + 02 00 02 C2 00 20 06 58 + 00 0A 00 0F 01 E0 01 2D + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A B6 + 2A F4 2A F4 4B 34 63 74 + 00 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 39 01 00 00 00 00 05 2A 00 00 05 9F /* CASET */ + 39 01 00 00 00 00 05 2B 00 00 0C 2F /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 09 10 B4 24 D9 /* FFC Setting; 0x09 : Enable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame*/ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-113mhz-osc-dsi-on-command = [ + /* DSC Setting */ + 07 01 00 00 00 00 01 01 /* DSC enable */ + 15 01 00 00 00 00 02 C3 00 /* Scaler disable */ + 39 01 00 00 00 00 5A 0A /* PPS Setting (1440 x 3120) (initial value) */ + 10 00 00 89 30 80 0C 30 + 05 A0 00 41 02 D0 02 D0 + 02 00 02 C2 00 20 06 58 + 00 0A 00 0F 01 E0 01 2D + 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 0E 1C 2A 38 + 46 54 62 69 70 77 79 7B + 7D 7E 01 02 01 00 09 40 + 09 BE 19 FC 19 FA 19 F8 + 1A 38 1A 78 1A B6 2A B6 + 2A F4 2A F4 4B 34 63 74 + 00 + /* Sleep Out(11h) */ + 05 01 00 00 0A 00 01 11 + /* Common Setting */ + 15 00 00 00 00 00 02 35 00 /* TE On(Vsync) */ + /* CASET/PASET Setting */ + 39 01 00 00 00 00 05 2A 00 00 05 9F /* CASET */ + 39 01 00 00 00 00 05 2B 00 00 0C 2F /* PASET */ + /* TSP SYNC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0A B9 01 C0 3C 0B 00 00 00 11 03 /* SYNC ENABLE */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* FD(Fast Discharge) Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 45 /* FD setting (Normal mode) */ + 15 01 00 00 00 00 02 B5 48 + 39 01 00 00 00 00 03 F0 A5 A5 + /* FFC Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 1E + 39 01 00 00 00 00 06 C5 09 10 B4 24 D9 /* FFC Setting; 0x09 : Enable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* OSC Spread Setting */ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 37 + 39 01 00 00 00 00 06 C5 04 FF 00 01 64 /* FFC Setting; 0x04 : Disable */ + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 FC A5 A5 + /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC 5A 5A + 15 01 00 00 00 00 02 B0 86 /* Global para */ + 15 01 00 00 00 00 02 EB 01 /* Dither IP Setting */ + 39 01 00 00 00 00 03 FC A5 A5 + /* Brightness Control */ + 39 01 00 00 00 00 03 F0 5A 5A /* Dimming Setting */ + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 /* Dimming Speed Setting : 0x01 : 1Frame*/ + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 D3 /* 0xD3 : ELVSS DIM ON */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 39 01 00 00 00 00 03 F0 A5 A5 + /* Display On */ + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-113mhz-osc-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,mdss-dsi-off-command=[ + 05 01 00 00 0A 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + ]; + qcom,mdss-dsi-panel-hbm-brightness-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 53 /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 00 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM Mode ON */ + 15 01 00 00 0C 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-brightness-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 53 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 0C 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-hbm-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-3 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-4 = [ + ]; + qcom,mdss-dsi-panel-hbm-on-command-5 = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 10 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 29 01 00 00 0C 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* 90Hz Setting */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-off-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-serial-num-pre-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 37 01 00 00 05 00 02 10 00 + ]; + qcom,mdss-dsi-panel-serial-num-command = [ + 06 01 00 00 00 00 01 A1 00 + ]; + qcom,mdss-dsi-panel-stage-info-command = [ + 06 01 00 00 00 00 01 DB 00 + ]; + qcom,mdss-dsi-panel-production-info-command = [ + 06 01 00 00 00 00 01 DC 00 + ]; + qcom,mdss-dsi-panel-serial-num-post-command = [ + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-on-command-1 = [ + ]; + qcom,mdss-dsi-panel-aod-on-command-2 = [ + ]; + qcom,mdss-dsi-panel-aod-off-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-samsung-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-new-command = [ + ]; + qcom,mdss-dsi-panel-aod-off-hbm-on-command = [ + /* ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 /* ELVSS Dim Setting */ + 15 00 00 00 00 00 02 B5 93 /* 0x93 : ELVSS DIM OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode Setting */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 27 /* HMB setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 4B + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 10 + 00 00 0F 03 06 02 0C 18 24 + 3C 77 00 FF 00 00 00 00 00 + 10 02 0C 18 24 3C 59 77 9B + BE E2 06 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 14 14 14 14 14 + 14 14 14 14 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 30 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + /* HBM MODE ON */ + 15 00 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + 29 01 00 00 00 00 03 51 0F FF /* 600nit */ + /* HBM 670 ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 00 /* HBM_670 ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* 90Hz Setting */ + 15 01 00 00 00 00 02 53 30 /* 0x30 Normal transition(90Hz) */ + ]; + qcom,mdss-dsi-panel-hbm-off-aod-on-command = [ + /* DLY ON */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 02 + 15 00 00 00 00 00 02 B5 13 /* DLY ON */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM 670 OFF */ + 29 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 92 02 /* HBM_670 OFF */ + 29 00 00 00 00 00 03 F0 A5 A5 + /* HBM Mode OFF */ + 29 00 00 00 00 00 03 51 03 FF /* 430nit */ + 29 00 00 00 00 00 03 F0 5A 5A /* Level2 key Access */ + 15 00 00 00 00 00 02 C7 23 /* Normal setting */ + 15 00 00 00 00 00 02 B0 34 + 15 00 00 00 00 00 02 B1 6D + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 20 B1 40 + 00 00 1F 0F 18 08 30 60 90 + F0 DC FC FC 00 00 01 12 23 + 40 08 30 60 90 F0 66 DC 6C + FA 8A 18 + 15 00 00 00 00 00 02 B0 06 + 29 00 00 00 00 00 18 B5 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 50 50 50 50 50 + 50 50 50 50 + 15 00 00 00 00 00 02 B0 17 + 15 00 00 00 00 00 02 95 00 + 29 01 00 00 00 00 03 F0 A5 A5 /* Level2 key Access Disable */ + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command = [ + /*Level2 key Enable*/ + 29 01 00 00 00 00 03 F0 5A 5A + //07 01 00 00 00 00 01 01 + //29 00 00 00 00 00 05 2A 00 00 05 9F + //29 00 00 00 00 00 05 2B 00 00 0C 2F + /*OTP key Enable*/ + 29 01 00 00 00 00 03 F1 F1 A2 + 29 01 00 00 00 00 0D C1 00 00 00 06 00 00 00 00 00 00 00 05 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0C C1 00 00 00 01 40 02 00 00 00 00 10 + 15 01 00 00 00 00 02 C0 03 + 29 01 00 00 00 00 0E C1 00 00 00 6B 00 00 00 0A 00 00 00 05 01 + 15 01 00 00 00 00 02 B0 07 + ]; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command = [ + 15 01 00 00 00 00 02 C0 03 + 15 01 00 00 00 00 02 B0 08 + ]; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command = [ + /*13th Parameter : 1byte Read value*/ + 06 01 00 00 00 00 02 FB 00 + ]; + qcom,mdss-dsi-panel-level2-key-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command = [ + 37 01 00 00 00 00 02 87 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command = [ + 06 01 00 00 00 00 02 C8 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command = [ + 37 01 00 00 00 00 02 B4 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command = [ + 06 01 00 00 00 00 02 C9 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command = [ + 37 01 00 00 00 00 02 2F 00 + ]; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command = [ + 06 01 00 00 00 00 02 B3 00 + ]; + qcom,mdss-dsi-panel-level2-key-disable-command = [ + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 F8 00 00 00 F0 00 05 00 EC 0A EA ED FD 01 F7 F1 EA 00 FF FE FE + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-night-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 E5 08 00 86 FF 00 04 03 F8 1B F0 E8 E9 03 ED DD F0 00 FF FE E4 + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-p3-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 D3 03 00 11 E4 01 0B 06 F0 1A FA FC E5 09 F6 EA F3 01 FC FF EA + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 02 + 29 01 00 00 00 00 16 67 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-dci-p3-off-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 03 67 00 01 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-laoding-effect-enable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 81 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 FF 6D + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-laoding-effect-disable-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 00 00 02 B0 01 + 29 01 00 00 00 00 02 95 A1 + 29 01 00 00 00 00 02 B0 14 + 29 01 00 00 00 00 03 95 28 28 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-srgb-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 0A 00 02 B0 02 + 29 01 00 00 0A 00 16 67 EA 12 06 4A F4 14 09 02 BF 47 FC DC D3 0B E5 D2 F6 14 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command = [ + 29 01 00 00 00 00 02 81 80 + 29 01 00 00 00 00 03 F0 5A 5A + 29 01 00 00 0A 00 02 B0 02 + 29 01 00 00 0A 00 16 67 FF 05 00 0B EB 00 07 00 FF 14 F8 EA F0 03 F5 DE F5 00 FF FF FF + 29 01 00 00 00 00 03 67 00 00 + 29 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-customer-srgb-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-laoding-effect-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-laoding-effect-disable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-p3-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-night-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-dci-p3-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-new-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-samsung-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-hbm-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-aod-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-pre-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-state-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-production-info-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-post-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-brightness-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-brightness-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-1-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-3-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-4-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-on-command-5-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-pre-read-2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-flash-read-fb-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-enable-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c8-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-c9-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-smrps-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-gamma-otp-read-b3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-level2-key-disable-command-state = "dsi_lp_mode"; + qcom,panel-roi-alignment=<720 65 720 65 720 65>; + qcom,compression-mode = "dsc"; + qcom,lm-split = <720 720>; + qcom,mdss-dsc-encoders = <2>; + qcom,mdss-dsc-slice-height = <65>; + qcom,mdss-dsc-slice-width = <720>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + + }; + }; +}; + +&dsi_samsung_oneplus_dsc_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&soc { + dsi_samsung_oneplus_dsc_cmd_display { + qcom,dsi-display-active; + }; +}; + +&dsi_samsung_oneplus_dsc_cmd { + qcom,mdss-dsi-display-timings { + timing@0 { /* wqhd 60hz */ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 24 0A 0A 06 02 04 00 1E 1A]; + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment=<720 65 720 65 720 65>; + }; + timing@1 { /* fhd 90hz */ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 24 0A 0A 06 02 04 00 1E 1A]; + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment=<540 73 540 73 540 73>; + }; + timing@2 { /* fhd 60hz */ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 24 0A 0A 06 02 04 00 1E 1A]; + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment=<540 73 540 73 540 73>; + }; + timing@3 { /* wqhd 90hz */ + qcom,mdss-dsi-panel-phy-timings = [00 24 0A 0A 26 24 0A 0A 06 02 04 00 1E 1A]; + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,panel-roi-alignment=<720 65 720 65 720 65>; + }; + }; +}; + + diff --git a/arch/arm64/boot/dts/qcom/dsi-panel-samsung_s6e3fc2x01.dtsi b/arch/arm64/boot/dts/qcom/dsi-panel-samsung_s6e3fc2x01.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..81325e406b41285844e8b7bd1c5762fd390124c4 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/dsi-panel-samsung_s6e3fc2x01.dtsi @@ -0,0 +1,404 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_samsung_s6e3fc2x01_cmd: qcom,mdss_dsi_samsung_s6e3fc2x01_cmd { + qcom,mdss-dsi-panel-name = "samsung s6e3fc2x01 cmd mode dsi panel"; + qcom,mdss-dsi-panel-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-version = "S6E3FC2X01"; + qcom,mdss-dsi-backlight-version = "SAMSUNG"; + qcom,mdss-dsi-backlight-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-reset-sequence = <1 5>, <0 2>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <145>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + //qcom,mdss-dsi-te-check-enable; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 08]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9F>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-high-brightness-panel; + qcom,mdss-dsi-acl-cmd-index = <0>; + qcom,mdss-dsi-acl-mode-index = <1>; + qcom,mdss-bl-high2bit; + //qcom,mdss-dsi-panel-status-check-mode = "te_signal_check"; + qcom,mdss-dsi-panel-seria-num-year-index = <12>; + qcom,mdss-dsi-panel-seria-num-mon-index = <12>; + qcom,mdss-dsi-panel-seria-num-day-index = <13>; + qcom,mdss-dsi-panel-seria-num-hour-index = <14>; + qcom,mdss-dsi-panel-seria-num-min-index = <15>; + qcom,mdss-dsi-panel-seria-num-sec-index = <16>; + qcom,ulps-enabled; + qcom,mdss-brightness-max-level = <1023>; + /* HDR Setting */ + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15635 16450 34000 16000 13250 34500 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <8000000>; + qcom,mdss-dsi-panel-average-brightness = <2000000>; + qcom,mdss-dsi-panel-blackness-level = <5>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <72>; + qcom,mdss-dsi-h-back-porch = <36>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <32>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <1037000000>;// 518.5MHZ + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 0A 00 02 11 00 + 39 01 00 00 00 00 03 9F 5A 5A + /*FD setting*/ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 01 + 15 01 00 00 00 00 02 CD 01 + 39 01 00 00 0F 00 03 F0 A5 A5 + /*TE ON*/ + 39 01 00 00 00 00 03 9F A5 A5 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 9F 5A 5A + /*MIC Setting*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 08 EB 17 41 92 0E 10 82 5A + 39 01 00 00 00 00 03 F0 A5 A5 + /*CASET/PASET*/ + 39 01 00 00 00 00 05 2A 00 00 04 37 + 39 01 00 00 00 00 05 2B 00 00 09 23 + /*TSP H_sync Setting*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 09 + 39 01 00 00 00 00 03 E8 10 30 + 39 01 00 00 00 00 03 F0 A5 A5 + /*Dimming Setting*/ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 00 00 02 B7 01 + 15 01 00 00 00 00 02 B0 08 + 15 01 00 00 00 00 02 B7 12 + 39 01 00 00 00 00 03 F0 A5 A5 + /*ESD improvement Setting*/ + 39 01 00 00 00 00 03 FC 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 02 E3 88 + 39 01 00 00 00 00 02 B0 07 + 39 01 00 00 00 00 02 ED 67 + 39 01 00 00 00 00 03 FC A5 A5 + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 F0 A5 A5 + /*ACL off*/ + 39 01 00 00 01 00 02 55 00 + /*SEED OFF*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 B1 00 01 + 39 01 00 00 00 00 03 F0 A5 A5 + /*SEED TCS OFF*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 B3 00 C1 + 39 01 00 00 00 00 03 F0 A5 A5 + /*Display on*/ + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 00 00 02 29 00 + 39 01 00 00 00 00 03 9F 5A 5A + ]; + qcom,mdss-dsi-off-command = [ + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 0A 00 01 28 + 05 01 00 00 00 00 01 10 + 39 01 00 00 00 00 03 9F 5A 5A + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 F4 01 + 39 01 00 00 96 00 03 F0 A5 A5 + ]; + //qcom,mdss-dsi-post-on-backlight=[ + // 39 01 00 00 00 00 03 9F A5 A5 + // 05 01 00 00 00 00 01 29 + // 39 01 00 00 00 00 03 9F 5A 5A + //]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + /**************************************************************/ + qcom,mdss-dsi-panel-hbm-brightness-on-command = [ + /*HBM ON */ + 39 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 53 E0 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-brightness-off-command = [ + /* DLY ON */ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 04 B7 00 01 5B + 39 00 00 00 00 00 03 F0 A5 A5 + + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-on-command-5 = [ + /*ELVSS OFF*/ + 39 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 08 + 15 00 00 00 00 00 02 B7 12 + 39 01 00 00 10 00 03 F0 A5 A5 + /*DLY OFF*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 04 B7 00 01 5B + 39 00 00 00 00 00 03 F0 A5 A5 + /*HBM ON */ + 15 00 00 00 00 00 02 53 E0 + 39 01 00 00 0E 00 03 51 03 FF + /*HBM 670nit*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 BD 00 00 + 39 00 00 00 00 00 03 F0 A5 A5 + /*DLY OFF*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 04 B7 00 01 53 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-command = [ + /*HBM 670nit off*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 BD 00 02 + 39 00 00 00 00 00 03 F0 A5 A5 + /*HBM off */ + 15 01 00 00 00 00 02 53 20 + ]; + qcom,mdss-dsi-panel-hbm-max-brightness-command-on = [ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 00 00 02 B7 7F + 15 01 00 00 00 00 02 B0 08 + 15 01 00 00 80 00 02 B7 92 + 39 01 00 00 40 00 02 53 E8 + 39 01 00 00 80 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 51 03 FF + ]; + qcom,mdss-dsi-panel-hbm-max-brightness-command-off = [ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 40 00 02 B7 7F + 15 01 00 00 00 00 02 B0 08 + 15 01 00 00 40 00 02 B7 92 + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 10 00 02 53 28 + ]; + qcom,mdss-dsi-panel-hbm-brightness-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-brightness-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-hbm-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-5-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-max-brightness-command-on-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-max-brightness-command-off-state = "dsi_lp_mode"; + qcom,mdss-dsi-hbm-off-command-state = "dsi_hs_mode"; + + qcom,mdss-dsi-panel-aod-on-command-1 = [ + + ]; + qcom,mdss-dsi-panel-aod-on-command-2 = [ + + ]; + + qcom,mdss-dsi-panel-aod-off-command = [ + + ]; + qcom,mdss-dsi-panel-aod-off-samsung-command = [ + + ]; + qcom,mdss-dsi-panel-aod-off-new-command = [ + + ]; + qcom,mdss-dsi-panel-aod-off-new-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-samsung-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-hbm-on-command = [ + /*ELVSS OFF*/ + 39 00 00 00 00 00 03 F0 5A 5A + 15 00 00 00 00 00 02 B0 08 + 15 00 00 00 00 00 02 B7 12 + 39 00 00 00 00 00 03 F0 A5 A5 + /*DL0 OFF*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 04 B7 00 01 5B + 39 00 00 00 00 00 03 F0 A5 A5 + /*HB0 ON */ + 15 00 00 00 00 00 02 53 E0 + 39 00 00 00 00 00 03 51 03 FF + /*HB0 670nit*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 BD 00 00 + 39 00 00 00 00 00 03 F0 A5 A5 + /*DL0 OFF*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 04 B7 00 01 53 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-off-hbm-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command = [ + /*HBM 670nit off*/ + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 03 BD 00 02 + 39 00 00 00 00 00 03 F0 A5 A5 + /*HBM off */ + 15 01 00 00 00 00 02 53 20 + ]; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command = [ + + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 16 B1 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF + 39 01 00 00 00 00 03 B1 00 00 + 39 01 00 00 00 00 03 f0 A5 A5 + + ]; + qcom,mdss-dsi-panel-display-p3-mode-on-command = [ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 16 B1 CE 01 02 1D E3 00 07 0D E9 28 FD F0 D3 0A E2 EA EA 01 FF FF F2 + 39 01 00 00 00 00 03 B1 00 00 + 39 01 00 00 00 00 03 f0 A5 A5 + ]; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command = [ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 16 B1 FF 00 00 00 FF 00 00 00 FF 00 FF FF FF 00 FF FF FF 00 FF FF FF + 39 01 00 00 00 00 03 B1 00 00 + 39 01 00 00 00 00 03 f0 A5 A5 + ]; + qcom,mdss-dsi-panel-dci-p3-off-command = [ + + ]; + qcom,mdss-dsi-customer-srgb-enable-command = [ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 16 B1 AF 06 0A 48 DF 10 05 08 C0 4D EF EA BD 0F DB F2 F0 18 FF FF FF + 39 01 00 00 00 00 03 B1 00 00 + 39 01 00 00 00 00 03 f0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command = [ + 39 01 00 00 00 00 02 81 90 + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 16 B1 CE 00 00 19 E5 00 06 09 C2 22 FA F3 DB 00 E6 EC E9 00 FF FF FF + 39 01 00 00 00 00 03 B1 00 00 + 39 01 00 00 00 00 03 f0 A5 A5 + ]; + qcom,mdss-dsi-customer-p3-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-customer-srgb-enable-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-display-srgb-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-p3-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-display-wide-color-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-aod-mode-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-command = [ + 06 01 00 00 00 00 01 A1 + ]; + + qcom,mdss-dsi-panel-serial-num-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0E 08]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id-command = [06 01 00 01 05 00 02 DC 08]; + qcom,mdss-dsi-panel-id-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id1-command = [06 01 00 01 05 00 02 0A 08]; + qcom,mdss-dsi-panel-id1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id2-command = [06 01 00 01 05 00 02 0E 08]; + qcom,mdss-dsi-panel-id2-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id3-command = [06 01 00 01 05 00 02 E0 08]; + qcom,mdss-dsi-panel-id3-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id4-command = [06 01 00 01 05 00 02 0F 08]; + qcom,mdss-dsi-panel-id4-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id5-command = [06 01 00 01 05 00 02 E3 08]; + qcom,mdss-dsi-panel-id5-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id6-command = [06 01 00 01 05 00 02 E5 08]; + qcom,mdss-dsi-panel-id6-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id7-command = [06 01 00 01 05 00 02 FB 08]; + qcom,mdss-dsi-panel-id7-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-level1-command = [15 01 00 00 00 00 02 B0 08]; + qcom,mdss-dsi-panel-hbm-level1-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-read-command = [06 01 00 01 05 00 02 B7 08]; + qcom,mdss-dsi-panel-hbm-read-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-open-command = [ + 39 01 00 00 00 00 03 FC 5A 5A]; + qcom,mdss-dsi-panel-read-register-close-command = [ + 39 01 00 00 00 00 03 FC A5 A5]; + qcom,mdss-dsi-panel-read-register-open-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-read-register-close-command-state = "dsi_lp_mode"; + }; + }; + }; +}; + +&dsi_samsung_s6e3fc2x01_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&soc { + dsi_samsung_s6e3fc2x01_cmd_display { + qcom,dsi-display-active; + }; +}; + +&dsi_samsung_s6e3fc2x01_cmd { + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 25 23 + 09 09 06 03 04 00 1C 19]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + + diff --git a/arch/arm64/boot/dts/qcom/dsi-panel-samsung_s6e3fc2x01_ed173.dtsi b/arch/arm64/boot/dts/qcom/dsi-panel-samsung_s6e3fc2x01_ed173.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..0d40a8769153da52b2279e3c5d51d0310b5dda27 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/dsi-panel-samsung_s6e3fc2x01_ed173.dtsi @@ -0,0 +1,543 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_samsung_s6e3fc2x01_ed173_cmd: qcom,mdss_dsi_samsung_s6e3fc2x01_ed173_cmd { + qcom,mdss-dsi-panel-name = "samsung s6e3fc2x01 ed173 cmd mode dsi panel"; + qcom,mdss-dsi-panel-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-version = "S6E3FC2X01_ED173"; + qcom,mdss-dsi-backlight-version = "SAMSUNG"; + qcom,mdss-dsi-backlight-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-reset-sequence = <1 5>, <0 2>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <145>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + //qcom,mdss-dsi-te-check-enable; + //qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 08]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9F>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-high-brightness-panel; + qcom,mdss-dsi-acl-cmd-index = <0>; + qcom,mdss-dsi-acl-mode-index = <1>; + qcom,mdss-bl-high2bit; + //qcom,mdss-dsi-panel-status-check-mode = "te_signal_check"; + qcom,mdss-dsi-panel-seria-num-year-index = <12>; + qcom,mdss-dsi-panel-seria-num-mon-index = <12>; + qcom,mdss-dsi-panel-seria-num-day-index = <13>; + qcom,mdss-dsi-panel-seria-num-hour-index = <14>; + qcom,mdss-dsi-panel-seria-num-min-index = <15>; + qcom,ulps-enabled; + /* HDR Setting */ + qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-hdr-color-primaries = <15635 16450 34000 16000 13250 34500 7500 3000>; + qcom,mdss-dsi-panel-peak-brightness = <5400000>; + qcom,mdss-dsi-panel-average-brightness = <2000000>; + qcom,mdss-dsi-panel-blackness-level = <2000>; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2340>; + qcom,mdss-dsi-h-front-porch = <72>; + qcom,mdss-dsi-h-back-porch = <36>; + qcom,mdss-dsi-h-pulse-width = <16>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <18>; + qcom,mdss-dsi-v-front-porch = <32>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x4 0x1>; + qcom,mdss-dsi-panel-clockrate = <1037000000>;// 518.5MHZ + qcom,mdss-dsi-on-command = [ + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 0A 00 02 11 00 + 39 01 00 00 00 00 03 9F 5A 5A + /*FD setting*/ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 01 + 15 01 00 00 00 00 02 CD 01 + 39 01 00 00 0F 00 03 F0 A5 A5 + /*TE ON*/ + 39 01 00 00 00 00 03 9F A5 A5 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 9F 5A 5A + /*MIC Setting*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 08 EB 17 41 92 0E 10 82 5A + 39 01 00 00 00 00 03 F0 A5 A5 + /*CASET/PASET*/ + 39 01 00 00 00 00 05 2A 00 00 04 37 + 39 01 00 00 00 00 05 2B 00 00 09 23 + /*TSP H_sync Setting*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 09 + 39 01 00 00 00 00 03 E8 10 30 + 39 01 00 00 00 00 03 F0 A5 A5 + /*Dimming Setting*/ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 00 00 02 B7 01 + 15 01 00 00 00 00 02 B0 08 + 15 01 00 00 00 00 02 B7 12 + 39 01 00 00 00 00 03 F0 A5 A5 + /*ESD improvement Setting*/ + 39 01 00 00 00 00 03 FC 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 02 E3 88 + 39 01 00 00 00 00 02 B0 07 + 39 01 00 00 00 00 02 ED 67 + 39 01 00 00 00 00 03 FC A5 A5 + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 F0 A5 A5 + /*ACL off*/ + 39 01 00 00 01 00 02 55 00 + /*SEED OFF*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 B1 00 01 + 39 01 00 00 00 00 03 F0 A5 A5 + /*SEED TCS OFF*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 B3 00 C1 + 39 01 00 00 00 00 03 F0 A5 A5 + /*Display on*/ + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 00 00 02 29 00 + 39 01 00 00 00 00 03 9F 5A 5A + ]; + qcom,mdss-dsi-off-command = [ + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 0A 00 01 28 + 05 01 00 00 00 00 01 10 + 39 01 00 00 00 00 03 9F 5A 5A + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 F4 01 + 39 01 00 00 96 00 03 F0 A5 A5 + ]; + //qcom,mdss-dsi-post-panel-on-command=[ + // 39 01 00 00 00 00 03 9F A5 A5 + // 05 01 00 00 00 00 01 29 + // 39 01 00 00 00 00 03 9F 5A 5A + //]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + /**************************************************************/ + qcom,mdss-dsi-panel-hbm-on-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 00 00 02 B7 7F + 15 01 00 00 00 00 02 B0 08 + 15 01 00 00 80 00 02 B7 92 + 39 01 00 00 00 00 02 53 E8 + 39 01 00 00 23 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 51 00 26 + ]; + qcom,mdss-dsi-panel-hbm-on-command-2 = [ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 00 00 02 B7 7F + 15 01 00 00 00 00 02 B0 08 + 15 01 00 00 80 00 02 B7 92 + 39 01 00 00 00 00 02 53 E8 + 39 01 00 00 23 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 51 00 78 + ]; + qcom,mdss-dsi-panel-hbm-on-command-3 = [ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 00 00 02 B7 7F + 15 01 00 00 00 00 02 B0 08 + 15 01 00 00 80 00 02 B7 92 + 39 01 00 00 00 00 02 53 E8 + 39 01 00 00 23 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 51 00 CA + ]; + qcom,mdss-dsi-panel-hbm-on-command-4 = [ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 00 00 02 B7 7F + 15 01 00 00 00 00 02 B0 08 + 15 01 00 00 80 00 02 B7 92 + 39 01 00 00 00 00 02 53 E8 + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 51 01 2A + + ]; + qcom,mdss-dsi-panel-hbm-on-command-5 = [ + /*ELVSS OFF*/ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 00 00 02 B7 01 + 15 01 00 00 00 00 02 B0 08 + 15 01 00 00 00 00 02 B7 12 + 39 01 00 00 00 00 03 F0 A5 A5 + /*DLY OFF*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 04 B7 00 01 5B + 39 01 00 00 00 00 03 F0 A5 A5 + 15 01 00 00 0A 00 02 53 E0 + 39 01 00 00 00 00 03 51 03 FF + /*DLY ON*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 04 B7 00 01 53 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-command = [ + /*DLY OFF*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 04 B7 00 01 5B + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 02 53 20 + /*DLY ON*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 04 B7 00 01 53 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-max-brightness-command-on = [ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 00 00 02 B7 7F + 15 01 00 00 00 00 02 B0 08 + 15 01 00 00 80 00 02 B7 92 + 39 01 00 00 40 00 02 53 E8 + 39 01 00 00 80 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 51 03 FF + ]; + qcom,mdss-dsi-panel-hbm-max-brightness-command-off = [ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 40 00 02 B7 7F + 15 01 00 00 00 00 02 B0 08 + 15 01 00 00 40 00 02 B7 92 + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 10 00 02 53 28 + ]; + qcom,mdss-dsi-hbm-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command-5-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-max-brightness-command-on-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-max-brightness-command-off-state = "dsi_lp_mode"; + qcom,mdss-dsi-hbm-off-command-state = "dsi_hs_mode"; + + qcom,mdss-dsi-panel-aod-on-command-1 = [ + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 0A 00 01 28 + 05 01 00 00 78 00 01 10 + 05 01 00 00 05 00 01 11 + 39 01 00 00 00 00 03 9F 5A 5A + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 01 + 15 01 00 00 64 00 02 CD 02 + 15 01 00 00 00 00 02 53 23 + 15 01 00 00 00 00 02 B0 A5 + 15 01 00 00 00 00 02 C7 00 + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 00 00 01 29 + 39 01 00 00 00 00 03 9F 5A 5A + ]; + qcom,mdss-dsi-panel-aod-on-command-2 = [ + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 05 00 01 11 + 39 01 00 00 00 00 03 9F 5A 5A + 39 01 00 00 00 00 03 f0 5a 5a + 15 01 00 00 00 00 02 b0 01 + 15 01 00 00 53 00 02 cd 02 + 15 01 00 00 00 00 02 53 20 + 15 01 00 00 00 00 02 b0 a5 + 15 01 00 00 00 00 02 c7 00 + 15 01 00 00 00 00 02 53 22 + 39 01 00 00 00 00 03 f0 a5 a5 + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 00 00 01 29 + 39 01 00 00 00 00 03 9F 5A 5A + ]; + qcom,mdss-dsi-panel-aod-on-command-3 = [ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 01 + 15 01 00 00 00 00 02 CD 01 + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 00 00 02 B7 01 + 15 01 00 00 00 00 02 B0 08 + 15 01 00 00 00 00 02 B7 12 + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 02 53 20 + ]; + qcom,mdss-dsi-panel-aod-off-command = [ + /*ELVSS OFF*/ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 08 + 15 01 00 00 00 00 02 B7 12 + 39 01 00 00 00 00 03 F0 A5 A5 + /*DLY OFF*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 04 B7 00 01 5B + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 01 + 15 01 00 00 00 00 02 CD 01 + 39 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 F0 A5 A5 + /*DLY ON*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 04 B7 00 01 53 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-off-samsung-command = [ + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 0A 00 01 28 + 05 01 00 00 80 00 01 10 + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 F4 01 + 39 01 00 00 32 00 03 F0 A5 A5 + 05 01 00 00 07 00 01 11 + 39 01 00 00 00 00 03 9F 5A 5A + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 01 + 15 01 00 00 00 00 02 CD 01 + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 00 00 02 B7 01 + 15 01 00 00 00 00 02 B0 08 + 15 01 00 00 00 00 02 B7 12 + 39 01 00 00 00 00 03 F0 A5 A5 + 15 01 00 00 00 00 02 53 28 + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 00 00 01 13 + 05 01 00 00 00 00 01 29 + 39 01 00 00 00 00 03 9F 5A 5A + ]; + qcom,mdss-dsi-panel-aod-off-new-command = [ + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 0A 00 01 28 + 05 01 00 00 00 00 01 10 + 39 01 00 00 00 00 03 9F 5A 5A + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 F4 01 + 39 01 00 00 96 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 0A 00 02 11 00 + 39 01 00 00 00 00 03 9F 5A 5A + /*FD setting*/ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 01 + 15 01 00 00 00 00 02 CD 01 + 39 01 00 00 0F 00 03 F0 A5 A5 + /*TE ON*/ + 39 01 00 00 00 00 03 9F A5 A5 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 9F 5A 5A + /*MIC Setting*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 08 EB 17 41 92 0E 10 82 5A + 39 01 00 00 00 00 03 F0 A5 A5 + /*CASET/PASET*/ + 39 01 00 00 00 00 05 2A 00 00 04 37 + 39 01 00 00 00 00 05 2B 00 00 09 23 + /*TSP H_sync Setting*/ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 09 + 39 01 00 00 00 00 03 E8 10 30 + 39 01 00 00 00 00 03 F0 A5 A5 + /*Dimming Setting*/ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 00 00 02 B7 01 + 15 01 00 00 00 00 02 B0 08 + 15 01 00 00 00 00 02 B7 12 + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 53 20 + 39 01 00 00 00 00 03 F0 A5 A5 + /*Display on*/ + 39 01 00 00 00 00 03 9F A5 A5 + 05 01 00 00 00 00 02 29 00 + 39 01 00 00 00 00 03 9F 5A 5A + ]; + qcom,mdss-dsi-panel-aod-off-new-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-samsung-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-hbm-on-command = [ + + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 07 + 39 01 00 00 00 00 02 B7 01 + 39 01 00 00 00 00 02 B0 08 + 39 01 00 00 00 00 02 B7 12 + 39 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 03 51 03 FF + 39 01 00 00 00 00 02 53 E0 + ]; + qcom,mdss-dsi-panel-aod-off-hbm-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-hbm-off-aod-on-command = [ + 39 01 00 00 00 00 02 53 22 + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 00 00 02 B7 01 + 15 01 00 00 00 00 02 B0 08 + 15 01 00 00 00 00 02 B7 12 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-aod-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-on-command-2-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-aod-mode-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-serial-num-command = [ + 06 01 00 00 00 00 01 A1 + ]; + qcom,mdss-dsi-panel-serial-num-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-panel-srgb-on-command = [ + 39 01 00 00 12 00 02 81 90 + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 16 B1 a6 04 04 47 DF 10 05 05 C3 4C EF D4 Bb 0B BF f1 EB 18 fe f9 d8 + 39 01 00 00 00 00 03 B1 00 00 + 39 01 00 00 00 00 03 f0 A5 A5 + ]; + qcom,mdss-dsi-panel-srgb-off-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 B1 00 01 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-srgb-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-srgb-off-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-panel-dci-p3-on-command = [ + 39 01 00 00 12 00 02 81 90 + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 16 B1 C6 00 00 21 ED 02 08 06 c1 27 FC dC E4 00 D9 e6 e7 00 fe f9 d8 + 39 01 00 00 00 00 03 B1 00 00 + 39 01 00 00 00 00 03 f0 A5 A5 + ]; + qcom,mdss-dsi-panel-dci-p3-off-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 B1 00 01 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-dci-p3-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-dci-p3-off-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-panel-night-mode-on-command = [ + 39 01 00 00 12 00 02 81 90 + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 16 B1 a6 04 04 47 DF 10 05 05 C3 4C EF D4 Bb 0B BF f1 EB 18 FF FE FA + 39 01 00 00 00 00 03 B1 00 00 + 39 01 00 00 00 00 03 f0 A5 A5 + ]; + qcom,mdss-dsi-panel-night-mode-off-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 B1 00 01 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-night-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-night-mode-off-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-panel-oneplus-mode-on-command = [ + 39 01 00 00 12 00 02 81 90 + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 16 B1 b4 02 04 05 ff 02 00 00 ff 00 ff ff f0 00 f0 e0 e1 18 ff fe fB + 39 01 00 00 00 00 03 B1 00 00 + 39 01 00 00 00 00 03 f0 A5 A5 + ]; + qcom,mdss-dsi-panel-oneplus-mode-off-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 B1 00 01 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-oneplus-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-oneplus-mode-off-comman-state = "dsi_lp_mode"; + + qcom,mdss-dsi-panel-adaption-mode-on-command = [ + 39 01 00 00 12 00 02 81 90 + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 02 B0 02 + 39 01 00 00 00 00 16 B1 C6 00 00 12 f8 02 04 00 c1 13 e9 de d5 00 e0 e4 e7 00 fb ff ff + 39 01 00 00 00 00 03 B1 00 00 + 39 01 00 00 00 00 03 f0 A5 A5 + ]; + qcom,mdss-dsi-panel-adaption-mode-off-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 B1 00 01 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-adaption-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-adaption-mode-off-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0a 08]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-id-command = [06 01 00 01 05 00 02 dc 08]; + qcom,mdss-dsi-panel-id-command-state = "dsi_lp_mode"; + }; + }; + }; +}; + +&dsi_samsung_s6e3fc2x01_ed173_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&soc { + dsi_samsung_s6e3fc2x01_ed173_cmd_display { + qcom,dsi-display-active; + }; +}; + +&dsi_samsung_s6e3fc2x01_ed173_cmd { + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 25 23 + 09 09 06 03 04 00 1C 19]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + + diff --git a/arch/arm64/boot/dts/qcom/dsi-panel-samsung_sofef00_m_cmd.dtsi b/arch/arm64/boot/dts/qcom/dsi-panel-samsung_sofef00_m_cmd.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..3f7a9df2d7f0afd578707c7e9a5e6c07de7793d9 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/dsi-panel-samsung_sofef00_m_cmd.dtsi @@ -0,0 +1,406 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_samsung_sofef00_m_cmd: qcom,mdss_dsi_samsung_sofef00_m_cmd { + qcom,mdss-dsi-panel-name = "samsung sofef00_m cmd mode dsi panel"; + qcom,mdss-dsi-panel-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-version = "SOFEF00_M"; + qcom,mdss-dsi-backlight-version = "SAMSUNG"; + qcom,mdss-dsi-backlight-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-reset-sequence = <1 20>, <0 10>, <1 20>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <145>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + //qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-tx-eot-append; + qcom,mdss-dsi-post-init-delay = <1>; + //qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; + qcom,mdss-dsi-panel-status-command = + [06 01 00 01 05 00 02 0A 08]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,mdss-dsi-panel-status-value-2 = <0xdc>; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-high-brightness-panel; + qcom,mdss-dsi-acl-cmd-index = <0>; + qcom,mdss-dsi-acl-mode-index = <1>; + qcom,mdss-bl-high2bit; + //qcom,mdss-dsi-panel-status-check-mode = "te_signal_check"; + qcom,mdss-dsi-panel-seria-num-year-index = <12>; + qcom,mdss-dsi-panel-seria-num-mon-index = <12>; + qcom,mdss-dsi-panel-seria-num-day-index = <13>; + qcom,mdss-dsi-panel-seria-num-hour-index = <14>; + qcom,mdss-dsi-panel-seria-num-min-index = <15>; + qcom,ulps-enabled; + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2280>; + + qcom,mdss-dsi-h-front-porch = <124>; + qcom,mdss-dsi-h-back-porch = <36>; + qcom,mdss-dsi-h-pulse-width = <12>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <2>; + qcom,mdss-dsi-v-front-porch = <12>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x8 0xa>; + qcom,mdss-dsi-on-command = [ + 05 01 00 00 0A 00 02 11 00 + 15 01 00 00 00 00 02 B0 1C + 15 01 00 00 0F 00 02 B5 24 + 15 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 03 FC 5A 5A + 39 01 00 00 00 00 04 E8 64 08 0C + 39 01 00 00 00 00 03 FC A5 A5 + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 02 B0 01 + 39 01 00 00 00 00 02 ED 04 + 39 01 00 00 00 00 03 F0 A5 A5 + 15 01 00 00 00 00 02 53 20 + 15 01 00 00 78 00 02 55 00 + 05 01 00 00 00 00 02 29 00 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 28 00 02 28 00 + 05 01 00 00 A0 00 02 10 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + /**************************************************************/ + qcom,mdss-dsi-panel-acl-command = [15 01 00 00 00 00 02 55 00]; + qcom,mdss-dsi-acl-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-hbm-on-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 53 E8 + 39 01 00 00 00 00 03 B2 02 D4 + 15 01 00 00 00 00 02 F7 03 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-on-command-2 = [ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 53 E8 + 39 01 00 00 00 00 03 B2 02 3C + 15 01 00 00 00 00 02 F7 03 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-on-command-3 = [ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 53 E8 + 39 01 00 00 00 00 03 B2 01 9C + 15 01 00 00 00 00 02 F7 03 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-on-command-4 = [ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 53 E8 + 39 01 00 00 00 00 03 B2 00 F0 + 15 01 00 00 00 00 02 F7 03 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-on-command-5 = [ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 53 E8 + 39 01 00 00 00 00 03 B2 00 40 + 15 01 00 00 00 00 02 F7 03 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-hbm-off-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 53 28 + 15 01 00 00 00 00 02 F7 03 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-hbm-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-hbm-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-aod-on-command-1 = [ + 05 01 00 00 23 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + 05 01 00 00 0A 00 02 11 00 + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 35 00 + 15 01 00 00 00 00 02 55 00 + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 00 00 02 B6 22 + 15 01 00 00 00 00 02 53 23 + 05 01 00 00 01 00 02 39 00 + 39 01 00 00 00 00 03 F0 A5 A5 + 05 01 00 00 00 00 02 29 00 + ]; + qcom,mdss-dsi-panel-aod-on-command-2 = [ + 05 01 00 00 23 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + 05 01 00 00 0A 00 02 11 00 + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 35 00 + 15 01 00 00 00 00 02 55 00 + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 00 00 02 B6 22 + 15 01 00 00 00 00 02 53 22 + 05 01 00 00 01 00 02 39 00 + 39 01 00 00 00 00 03 F0 A5 A5 + 05 01 00 00 00 00 02 29 00 + ]; + qcom,mdss-dsi-panel-aod-on-command-3 = [ + 05 01 00 00 23 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + 05 01 00 00 0A 00 02 11 00 + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 35 00 + 15 01 00 00 00 00 02 55 00 + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 00 00 02 B6 22 + 15 01 00 00 00 00 02 53 23 + 05 01 00 00 01 00 02 38 00 + 39 01 00 00 00 00 03 F0 A5 A5 + 05 01 00 00 00 00 02 29 00 + ]; + qcom,mdss-dsi-panel-aod-on-command-4 = [ + 05 01 00 00 23 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + 05 01 00 00 0A 00 02 11 00 + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 35 00 + 15 01 00 00 00 00 02 55 00 + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 00 00 02 B6 22 + 15 01 00 00 00 00 02 53 22 + 05 01 00 00 01 00 02 38 00 + 39 01 00 00 00 00 03 F0 A5 A5 + 05 01 00 00 00 00 02 29 00 + ]; + qcom,mdss-dsi-panel-aod-off-command = [ + 05 01 00 00 23 00 02 28 00 + 05 01 00 00 78 00 02 10 00 + 05 01 00 00 0A 00 02 11 00 + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 35 00 + 15 01 00 00 00 00 02 55 00 + 15 01 00 00 00 00 02 B0 07 + 15 01 00 00 00 00 02 B6 12 + 15 01 00 00 00 00 02 53 20 + 05 01 00 00 01 00 02 38 00 + 39 01 00 00 00 00 03 F0 A5 A5 + 05 01 00 00 00 00 02 29 00 + ]; + qcom,mdss-dsi-panel-aod-mode-command-1 = [ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 53 23 + 05 01 00 00 01 00 02 39 00 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-mode-command-2 = [ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 53 22 + 05 01 00 00 01 00 02 39 00 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-mode-command-3 = [ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 53 23 + 05 01 00 00 01 00 02 38 00 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-aod-mode-command-4 = [ + 39 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 53 22 + 05 01 00 00 01 00 02 38 00 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-aod-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-aod-off-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-aod-mode-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-panel-serial-num-command = [ + 06 01 00 00 00 00 01 A1 + ]; + qcom,mdss-dsi-panel-serial-num-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-panel-srgb-on-command = [ + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 03 E2 00 85 + 39 01 00 00 00 00 02 B0 2C + 39 01 00 00 00 00 16 E2 B1 07 06 3E CD 14 07 08 B0 4D E6 C9 C1 0B B9 E5 DA 18 FE F6 D7 + 39 01 00 00 00 00 02 b0 49 + 39 01 00 00 00 00 02 E2 00 + 39 01 00 00 00 00 02 b0 4A + 39 01 00 00 00 00 02 E2 00 + 39 01 00 00 00 00 02 b0 4B + 39 01 00 00 00 00 02 E2 00 + 39 01 00 00 00 00 02 b0 4C + 39 01 00 00 00 00 02 E2 00 + 39 01 00 00 00 00 02 b0 4D + 39 01 00 00 00 00 02 E2 00 + 39 01 00 00 00 00 03 f0 A5 A5 + ]; + qcom,mdss-dsi-panel-srgb-off-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 E2 00 40 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-srgb-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-srgb-off-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-panel-dci-p3-on-command = [ + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 03 E2 00 85 + 39 01 00 00 00 00 02 B0 2C + 39 01 00 00 00 00 16 E2 D0 00 00 12 D4 00 0A 08 C3 1D EE CF E8 02 C8 E7 DE 00 FF F6 D7 + 39 01 00 00 00 00 02 b0 49 + 39 01 00 00 00 00 02 E2 00 + 39 01 00 00 00 00 02 b0 4A + 39 01 00 00 00 00 02 E2 00 + 39 01 00 00 00 00 02 b0 4B + 39 01 00 00 00 00 02 E2 00 + 39 01 00 00 00 00 02 b0 4C + 39 01 00 00 00 00 02 E2 00 + 39 01 00 00 00 00 02 b0 4D + 39 01 00 00 00 00 02 E2 00 + 39 01 00 00 00 00 03 f0 A5 A5 + ]; + qcom,mdss-dsi-panel-dci-p3-off-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 E2 00 40 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-dci-p3-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dci-p3-off-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-panel-night-mode-on-command = [ + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 03 E2 00 85 + 39 01 00 00 00 00 02 B0 2C + 39 01 00 00 00 00 16 E2 B1 07 06 3E CD 14 07 08 B0 4D E6 C9 C1 0B B9 E5 DA 18 FE FD F5 + 39 01 00 00 00 00 02 b0 49 + 39 01 00 00 00 00 02 E2 00 + 39 01 00 00 00 00 03 f0 A5 A5 + ]; + qcom,mdss-dsi-panel-night-mode-off-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 E2 00 40 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-night-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-night-mode-off-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-panel-oneplus-mode-on-command = [ + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 03 E2 00 85 + 39 01 00 00 00 00 02 B0 2C + 39 01 00 00 00 00 16 E2 b4 + 02 04 05 ff 02 00 00 ff 00 + ff ff f0 00 f0 e0 e1 18 ff fe fB + 39 01 00 00 00 00 02 b0 49 + 39 01 00 00 00 00 02 E2 00 + 39 01 00 00 00 00 02 b0 4A + 39 01 00 00 00 00 02 E2 00 + 39 01 00 00 00 00 02 b0 4B + 39 01 00 00 00 00 02 E2 01 + 39 01 00 00 00 00 02 b0 4C + 39 01 00 00 00 00 02 E2 01 + 39 01 00 00 00 00 03 f0 a5 a5 + ]; + qcom,mdss-dsi-panel-oneplus-mode-off-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 E2 00 40 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-panel-oneplus-mode-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-panel-oneplus-mode-off-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-panel-adaption-mode-on-command = [ + 39 01 00 00 00 00 03 f0 5A 5A + 39 01 00 00 00 00 03 E2 00 85 + 39 01 00 00 00 00 02 B0 2C + 39 01 00 00 00 00 16 E2 B4 02 04 05 FF 02 00 00 FF 00 FF FF F0 00 F0 E0 E1 18 FE FD F1 + 39 01 00 00 00 00 02 b0 49 + 39 01 00 00 00 00 02 E2 00 + 39 01 00 00 00 00 03 f0 A5 A5 + ]; + qcom,mdss-dsi-panel-adaption-mode-off-command = [ + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 03 E2 00 40 + 39 01 00 00 00 00 03 F0 A5 A5 + ]; + qcom,mdss-dsi-adaption-mode-on-command-state = + "dsi_lp_mode"; + qcom,mdss-dsi-adaption-mode-off-command-state = + "dsi_lp_mode"; + + qcom,mdss-dsi-panel-status-command = + [06 01 00 01 05 00 02 0a 08]; + qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; + + qcom,mdss-dsi-panel-id-command = [06 01 00 01 05 00 02 dc 08]; + qcom,mdss-dsi-panel-id-command-state = "dsi_lp_mode"; + }; + }; + }; + }; + + +&dsi_samsung_sofef00_m_cmd { + + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&soc { + dsi_samsung_sofef00_m_cmd_display { + qcom,dsi-display-active; + }; +}; + +&dsi_samsung_sofef00_m_cmd { + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 25 23 + 09 09 06 03 04 00 1C 19]; + qcom,display-topology = <1 0 1>; + qcom,default-topology-index = <0>; + }; + }; +}; + + diff --git a/arch/arm64/boot/dts/qcom/dsi_samsung_oneplus_fhd_dsc.dtsi b/arch/arm64/boot/dts/qcom/dsi_samsung_oneplus_fhd_dsc.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..6bb60bc40ff336414bdc5bf83a11805a20e20d60 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/dsi_samsung_oneplus_fhd_dsc.dtsi @@ -0,0 +1,270 @@ +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&mdss_mdp { + dsi_samsung_oneplus_fhd_dsc_cmd: qcom,mdss_dsi_samsung_oneplus_fhd_dsc_cmd { + qcom,mdss-dsi-panel-name = "samsung oneplus dsc fhd cmd mode dsi panel"; + qcom,mdss-dsi-panel-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-version = "DSC"; + qcom,mdss-dsi-backlight-version = "SAMSUNG"; + qcom,mdss-dsi-backlight-manufacture = "SAMSUNG"; + qcom,mdss-dsi-panel-type = "dsi_cmd_mode"; + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-underflow-color = <0xff>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-reset-sequence = <1 5>, <0 2>, <1 10>; + qcom,mdss-pan-physical-width-dimension = <68>; + qcom,mdss-pan-physical-height-dimension = <145>; + qcom,mdss-dsi-traffic-mode = "burst_mode"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-te-pin-select = <1>; + qcom,mdss-dsi-wr-mem-start = <0x2c>; + qcom,mdss-dsi-wr-mem-continue = <0x3c>; + qcom,mdss-dsi-te-dcs-command = <1>; + qcom,mdss-dsi-te-check-enable; + qcom,mdss-dsi-te-using-te-pin; + qcom,mdss-dsi-lp11-init; + qcom,mdss-dsi-high-brightness-panel; + qcom,mdss-dsi-acl-cmd-index = <0>; + qcom,mdss-dsi-acl-mode-index = <1>; + qcom,mdss-bl-high2bit; + qcom,mdss-dsi-panel-seria-num-year-index = <12>; + qcom,mdss-dsi-panel-seria-num-mon-index = <12>; + qcom,mdss-dsi-panel-seria-num-day-index = <13>; + qcom,mdss-dsi-panel-seria-num-hour-index = <14>; + qcom,mdss-dsi-panel-seria-num-min-index = <15>; + qcom,ulps-enabled; + + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2336>; + qcom,mdss-dsi-h-front-porch = <116>; + qcom,mdss-dsi-h-back-porch = <120>; + qcom,mdss-dsi-h-pulse-width = <44>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <124>; + qcom,mdss-dsi-v-front-porch = <120>; + qcom,mdss-dsi-v-pulse-width = <80>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x8 0xa>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + qcom,mdss-dsi-timing-switch-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 07 01 00 00 00 00 01 01 + //29 01 00 00 00 00 02 C3 01 + 29 01 00 00 00 00 05 2A 00 00 04 37 + 29 01 00 00 00 00 05 2B 00 00 09 1F + 29 01 00 00 00 00 02 53 20 + 29 01 00 00 00 00 03 F0 A5 A5 + + + ]; + qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 20 1f 06 06 03 03 04 00 13 15]; + qcom,mdss-dsi-t-clk-pre = <0x13>; + qcom,mdss-dsi-t-clk-post = <0x15>; + qcom,mdss-dsi-on-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 07 01 00 00 00 00 01 01 + 29 01 00 00 00 00 02 C3 01 + 29 01 00 00 00 00 05 2A 00 00 04 37 + 29 01 00 00 00 00 05 2B 00 00 09 1F + 29 01 00 00 00 00 5A 0A 11 00 00 89 30 80 09 20 04 38 00 + 49 02 1C 02 1C 02 00 02 0E 00 20 + 07 16 00 07 00 0C 01 56 01 65 18 + 00 10 F0 03 0C 20 00 06 0B 0B 33 + 0E 1C 2A 38 46 54 62 69 70 77 79 + 7B 7D 7E 01 02 01 00 09 40 09 BE + 19 FC 19 FA 19 F8 1A 38 1A 78 1A + B6 2A F6 2B 34 2B 74 3B 74 6B F4 + 00 + 39 01 00 00 00 00 02 53 20 + 29 01 00 00 00 00 03 F0 A5 A5 + 05 01 00 00 0A 00 01 11 + 15 01 00 00 00 00 02 35 00 + 29 01 00 00 00 00 05 2A 00 00 04 37 + 29 01 00 00 00 00 05 2B 00 00 09 1F + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0a B9 01 B0 81 09 00 00 00 11 03 + 39 01 00 00 00 00 03 F0 A5 A5 + 29 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 d3 + 29 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 02 53 20 + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-off-command = [ + + /*Display off Delay 20ms*/ + 05 01 00 00 14 00 02 28 00 + /*Sleep in*/ + 05 01 00 00 00 00 02 10 00 + + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + + qcom,panel-roi-alignment=<540 73 540 73 540 73>; + qcom,compression-mode = "dsc"; + qcom,lm-split = <540 540>; + qcom,mdss-dsc-encoders = <2>; + qcom,mdss-dsc-slice-height = <73>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; +timing@1{ + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-width = <1080>; + qcom,mdss-dsi-panel-height = <2336>; + qcom,mdss-dsi-h-front-porch = <116>; + qcom,mdss-dsi-h-back-porch = <120>; + qcom,mdss-dsi-h-pulse-width = <44>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <124>; + qcom,mdss-dsi-v-front-porch = <120>; + qcom,mdss-dsi-v-pulse-width = <80>; + qcom,mdss-dsi-h-right-border = <0>; + qcom,mdss-dsi-v-top-border = <0>; + qcom,mdss-dsi-v-bottom-border = <0>; + qcom,mdss-dsi-panel-jitter = <0x8 0xa>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-panel-clockrate = <1100000000>; + qcom,mdss-dsi-timing-switch-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 07 01 00 00 00 00 01 01 + //29 01 00 00 00 00 02 C3 01 + 29 01 00 00 00 00 05 2A 00 00 04 37 + 29 01 00 00 00 00 05 2B 00 00 09 1F + 29 01 00 00 00 00 02 53 30 + 29 01 00 00 00 00 03 F0 A5 A5 + + ]; + qcom,mdss-dsi-panel-phy-timings = [00 1F 08 08 24 22 08 08 05 03 04 00 1A 18]; + qcom,mdss-dsi-t-clk-pre = <0x1A>; + qcom,mdss-dsi-t-clk-post = <0x18>; + qcom,mdss-dsi-on-command = [ + 29 01 00 00 00 00 03 F0 5A 5A + 07 01 00 00 00 00 01 01 + 29 01 00 00 00 00 02 C3 01 + 29 01 00 00 00 00 05 2A 00 00 04 37 + 29 01 00 00 00 00 05 2B 00 00 09 1F + 29 01 00 00 00 00 5A 0A 11 00 00 89 30 80 09 20 04 38 00 + 49 02 1C 02 1C 02 00 02 0E 00 20 + 07 16 00 07 00 0C 01 56 01 65 18 + 00 10 F0 03 0C 20 00 06 0B 0B 33 + 0E 1C 2A 38 46 54 62 69 70 77 79 + 7B 7D 7E 01 02 01 00 09 40 09 BE + 19 FC 19 FA 19 F8 1A 38 1A 78 1A + B6 2A F6 2B 34 2B 74 3B 74 6B F4 + 00 + 29 01 00 00 00 00 03 F0 A5 A5 + 05 01 00 00 0A 00 01 11 + 15 01 00 00 00 00 02 35 00 + 29 01 00 00 00 00 05 2A 00 00 04 37 + 29 01 00 00 00 00 05 2B 00 00 09 1F + 39 01 00 00 00 00 03 F0 5A 5A + 39 01 00 00 00 00 0a B9 01 B0 81 09 00 00 00 11 03 + 39 01 00 00 00 00 03 F0 A5 A5 + 29 01 00 00 00 00 03 F0 5A 5A + 15 01 00 00 00 00 02 B0 05 + 15 01 00 00 00 00 02 B1 01 + 15 01 00 00 00 00 02 B0 02 + 15 01 00 00 00 00 02 B5 d3 + 29 01 00 00 00 00 03 F0 A5 A5 + 39 01 00 00 00 00 02 53 30 + 05 01 00 00 00 00 01 29 + ]; + qcom,mdss-dsi-off-command = [ + + /*Display off Delay 20ms*/ + 05 01 00 00 14 00 02 28 00 + /*Sleep in*/ + 05 01 00 00 00 00 02 10 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,panel-roi-alignment=<540 73 540 73 540 73>; + qcom,compression-mode = "dsc"; + qcom,lm-split = <540 540>; + qcom,mdss-dsc-encoders = <2>; + qcom,mdss-dsc-slice-height = <73>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + + }; + + + }; + }; +}; + +&dsi_samsung_oneplus_fhd_dsc_cmd { + + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-te-gpio = <&tlmm 8 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; +}; + +&soc { + dsi_samsung_oneplus_fhd_dsc_cmd_display { + qcom,dsi-display-active; + }; +}; + +&dsi_samsung_oneplus_fhd_dsc_cmd{ + qcom,mdss-dsi-display-timings { + timing@0{ + qcom,mdss-dsi-panel-phy-timings = [00 16 05 05 20 1f 06 06 03 03 04 00 13 15]; + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + }; + timing@1{ + qcom,mdss-dsi-panel-phy-timings = [00 1F 08 08 24 22 08 08 05 03 04 00 1A 18]; + qcom,display-topology = <1 1 1>,<2 2 1>; + qcom,default-topology-index = <1>; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamole-overlay-dvt.dts b/arch/arm64/boot/dts/qcom/guacamole-overlay-dvt.dts new file mode 100644 index 0000000000000000000000000000000000000000..e273cc611f3f47474508b6b03e82996c89ea217e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-overlay-dvt.dts @@ -0,0 +1,43 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +#include "guacamole_evt3.dtsi" +#include "guacamole_dvt.dtsi" + +/ { + model = "MTP 18821 18831 15"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0 >; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <15>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamole-overlay-evt1.dts b/arch/arm64/boot/dts/qcom/guacamole-overlay-evt1.dts new file mode 100644 index 0000000000000000000000000000000000000000..68749dd8d7956f6dfa2f6508e82e15fb2d3588bc --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-overlay-evt1.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +/ { + model = "MTP 18821 18831 12"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <12>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamole-overlay-evt2-second.dts b/arch/arm64/boot/dts/qcom/guacamole-overlay-evt2-second.dts new file mode 100644 index 0000000000000000000000000000000000000000..a6e084d6c298056c3730d1314f01ac76f6b56195 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-overlay-evt2-second.dts @@ -0,0 +1,75 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +/ { + model = "MTP 18821 18831 second 55"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <55>; +}; + +&qupv3_se8_i2c { + oneplus_fastchg@26{ + status = "disable"; + }; + + oneplus_fastchg@52{ + status = "ok"; + compatible = "microchip,oneplus_fastchg"; + reg = <0x52>; + microchip,mcu-en-gpio = <&tlmm 10 0x00>; + microchip,usb-sw-1-gpio = <&tlmm 94 0x00>; + microchip,usb-sw-2-gpio = <&tlmm 59 0x00>; + microchip,ap-clk = <&tlmm 92 0x00>; + microchip,ap-data = <&tlmm 93 0x00>; + op,fw-erase-count = <959>; + op,fw-addr-low = <0>; + op,fw-addr-high = <0>; + op,n76e_support; + op,mcl_verion; + + pinctrl-names = "mux_fastchg_active", + "mux_fastchg_suspend", + "mcu_data_active", + "mcu_data_suspend"; + pinctrl-0 = <&fastchg_active + &usb_sw_active + &ap_clk_active >; + pinctrl-1 = <&usb_sw_suspend + &fastchg_suspend + &ap_clk_suspend>; + pinctrl-2 =<&ap_data_active>; + pinctrl-3 =<&ap_data_suspend>; + }; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamole-overlay-evt2.dts b/arch/arm64/boot/dts/qcom/guacamole-overlay-evt2.dts new file mode 100644 index 0000000000000000000000000000000000000000..d75754eb4b0f771d1b4af104c7832506065e15f5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-overlay-evt2.dts @@ -0,0 +1,40 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +/ { + model = "MTP 18821 18831 13 54 evt2"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <13 54>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamole-overlay-evt3.dts b/arch/arm64/boot/dts/qcom/guacamole-overlay-evt3.dts new file mode 100644 index 0000000000000000000000000000000000000000..070ed1c5453c17fe8c3646109a982765dfe9a756 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-overlay-evt3.dts @@ -0,0 +1,41 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +#include "guacamole_evt3.dtsi" +/ { + model = "MTP 18821 18831 14 52 53"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <14 52 53>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamole-overlay-pvt.dts b/arch/arm64/boot/dts/qcom/guacamole-overlay-pvt.dts new file mode 100644 index 0000000000000000000000000000000000000000..1a3299e5dfed8706b05294b4037a4e1751cc8734 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-overlay-pvt.dts @@ -0,0 +1,44 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" +#include "guacamole_evt1.dtsi" +#include "guacamole_evt2.dtsi" +#include "guacamole_evt3.dtsi" +#include "guacamole_dvt.dtsi" +#include "guacamole_pvt.dtsi" + +/ { + model = "MTP 18821 18831 21 22"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0 >; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <21 22>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamole-overlay-t0.dts b/arch/arm64/boot/dts/qcom/guacamole-overlay-t0.dts new file mode 100644 index 0000000000000000000000000000000000000000..ef389e47a2751975099ae13ccb2800e0d140699c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole-overlay-t0.dts @@ -0,0 +1,39 @@ +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "sm8150-mtp.dtsi" +#include "sm8150-mtp-audio-overlay.dtsi" + +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-t0.dtsi" +#include "guacamole.dtsi" +#include "guacamole_sm8150.dtsi" +#include "guacamole_t0.dtsi" + +/ { + model = "MTP 18821 18831 T0 11"; + compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; + qcom,board-id = <8 0>; + /*we can add project id to this array,uefi can auto read it,if new project,we add to this array */ + oem,project-id = <18821 18831>; + /*we can add hw id to this array,uefi can auto read it,if new hw,we add to this array */ + oem,hw-id = <11>; +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamole.dtsi b/arch/arm64/boot/dts/qcom/guacamole.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..0e3a5bf663875884d0138935c1804f66ffb47398 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole.dtsi @@ -0,0 +1,189 @@ + +&pm8150_adc_tm { + skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1 { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&thermal_zones { + skin-therm { + polling-delay-passive = <2000>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>; + trips { + freq_config1: freq_config1 { + temperature = <52000>; + hysteresis = <2000>; + type = "passive"; + }; + freq_config2: freq_config2 { + temperature = <54000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + cooling-maps { + freq_dev0 { + trip = <&freq_config1>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-1)>;/*345*/ + }; + freq_dev1 { + trip = <&freq_config1>; + cooling-device = + <&CPU0 9 9>;/*1036*/ + }; + freq_dev2 { + trip = <&freq_config1>; + cooling-device = + <&CPU4 13 13>;/*1056*/ + }; + freq_dev3 { + trip = <&freq_config1>; + cooling-device = + <&CPU7 16 16>;/*1171*/ + }; + freq_dev4 { + trip = <&freq_config2>; + cooling-device = + <&CPU0 11 11>;/*844*/ + }; + freq_dev5 { + trip = <&freq_config2>; + cooling-device = + <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + freq_dev6 { + trip = <&freq_config2>; + cooling-device = + <&CPU5 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + freq_dev7 { + trip = <&freq_config2>; + cooling-device = + <&CPU6 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + freq_dev8 { + trip = <&freq_config2>; + cooling-device = + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + pa-therm1 { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-msm-therm { + trips { + freq_config3: freq_config3 { + temperature = <62000>; + hysteresis = <2000>; + type = "passive"; + }; + freq_config4: freq_config4 { + temperature = <64000>; + hysteresis = <2000>; + type = "passive"; + }; + freq_config5: freq_config5 { + temperature = <66000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + cooling-maps { + freq_dev0 { + trip = <&freq_config3>; + cooling-device = + <&CPU0 2 2>;/*1632 18*/ + }; + freq_dev1 { + trip = <&freq_config3>; + cooling-device = + <&CPU4 8 8>;/*1612 17*/ + }; + freq_dev2 { + trip = <&freq_config3>; + cooling-device = + <&CPU7 9 9>;/*1920 20*/ + }; + freq_dev3 { + trip = <&freq_config4>; + cooling-device = + <&CPU0 4 4>;/*1478*/ + }; + freq_dev4 { + trip = <&freq_config4>; + cooling-device = + <&CPU4 11 11>;/*1286*/ + }; + freq_dev5 { + trip = <&freq_config4>; + cooling-device = + <&CPU7 13 13>;/*1497*/ + }; + freq_dev6 { + trip = <&freq_config4>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-3)>;/*499*/ + }; + freq_dev7 { + trip = <&freq_config5>; + cooling-device = + <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-2)>;/*427*/ + }; + }; + }; +}; + +&pm8150b_charger { + /* for verify test adjust 530->500 */ + hot-bat-decidegc = <500>; +}; + +&vendor { + haptics_boost_vreg { + status = "disabled"; + }; +}; + +&pm8150b_haptics { + status = "disabled"; + vdd-supply = <&haptics_boost_vreg>; +}; + +&mtp_batterydata { + #include "OP-fg-batterydata-4000mah.dtsi" +}; + +&wdog{ + qcom,bark-time = <15000>; +}; diff --git a/arch/arm64/boot/dts/qcom/guacamole_dvt.dtsi b/arch/arm64/boot/dts/qcom/guacamole_dvt.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..18b79ae52abaee1b2905554c37a4abb1f2b35a21 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole_dvt.dtsi @@ -0,0 +1 @@ +/*this is for one project different hw version */ \ No newline at end of file diff --git a/arch/arm64/boot/dts/qcom/guacamole_evt1.dtsi b/arch/arm64/boot/dts/qcom/guacamole_evt1.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..09b750d1e74da338197aadb3c88734b8a8ce9c54 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole_evt1.dtsi @@ -0,0 +1,4 @@ +/*this is for one project different hw version */ +&motor_pl { + structure,id = <2>;//EVT1 +}; diff --git a/arch/arm64/boot/dts/qcom/guacamole_evt2.dtsi b/arch/arm64/boot/dts/qcom/guacamole_evt2.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..fb46b0abdd74229c7b7321578076210829aef6be --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole_evt2.dtsi @@ -0,0 +1,6 @@ +/*this is for one project different hw version */ + +&motor_pl { + structure,id = <3>;//EVT2 +}; + diff --git a/arch/arm64/boot/dts/qcom/guacamole_evt3.dtsi b/arch/arm64/boot/dts/qcom/guacamole_evt3.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..8f699bb7f92226a6738f092d41e20a7f5bec7f1e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole_evt3.dtsi @@ -0,0 +1,2 @@ +/*this is for one project different hw version */ + diff --git a/arch/arm64/boot/dts/qcom/guacamole_pvt.dtsi b/arch/arm64/boot/dts/qcom/guacamole_pvt.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..18b79ae52abaee1b2905554c37a4abb1f2b35a21 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole_pvt.dtsi @@ -0,0 +1 @@ +/*this is for one project different hw version */ \ No newline at end of file diff --git a/arch/arm64/boot/dts/qcom/guacamole_sm8150.dtsi b/arch/arm64/boot/dts/qcom/guacamole_sm8150.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..5ae1c7029a3bd9ed2126c145320d3d73787cc013 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole_sm8150.dtsi @@ -0,0 +1,8 @@ +/*this is for sm8150 version */ + +&ois_rear_0 { + ois_gyro,id = <1>;//18821 +}; +&ois_rear_1 { + ois_gyro,id = <1>;//18821 +}; diff --git a/arch/arm64/boot/dts/qcom/guacamole_t0.dtsi b/arch/arm64/boot/dts/qcom/guacamole_t0.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..69eda8ced7fed84fd48c8ba84f3d05f98c9ed3db --- /dev/null +++ b/arch/arm64/boot/dts/qcom/guacamole_t0.dtsi @@ -0,0 +1,293 @@ +/*this is for one project different hw version */ + +/*tp 1.8v power change to gpio119 for T0 hw*/ +&qupv3_se17_i2c { + sec-s6sy761@48 { + //enable1v8_gpio = <&tlmm 119 0x00>; + pinctrl-0 = <&tp_irq_active &tp_rst_active &tp_1v8_t0_active>; + pinctrl-1 = <&tp_rst_suspend &tp_1v8_t0_suspend>; + }; +}; + +&qupv3_se17_i2c { + st_fts@49 { + //enable1v8_gpio = <&tlmm 119 0x00>; + pinctrl-0 = <&tp_irq_active &tp_rst_active &tp_1v8_t0_active>; + pinctrl-1 = <&tp_rst_suspend &tp_1v8_t0_suspend>; + }; +}; + +/*fingerprint reset gpio change to gpio131 on T0*/ +&soc { + fingerprint_detect { + compatible = "oneplus,fpdetect"; + fp-gpio-id0 = <&tlmm 90 0>; + fp-gpio-id1 = <&pm8150_gpios 3 0>; + pinctrl-names = "fp_id_init"; + pinctrl-0 = <&fp_id0_init &fp_id1_init>; + }; + + silead_fp { + compatible = "sil,fingerprint"; + interrupt-parent = <&tlmm>; + //avdd-supply = <&pm8150_l17>; + avdd-gpios = <&tlmm 101 0x00>; + irq-gpios = <&tlmm 118 0x00>; + rst-gpios = <&tlmm 131 0x00>; + pinctrl-names = "fp_en_init"; + pinctrl-0 = <&fp_reset_init &fp_irq_init &fp_vdd_init>; + status = "okay"; + }; + + goodix_fp { + compatible = "goodix,fingerprint"; + interrupt-parent = <&tlmm>; + //vdd-3v2-supply = <&pm8998_l22>; + //vdd-voltage = <3200000 3200000>; + //vdd-current = <50000>; + fp-gpio-irq = <&tlmm 118 0x00>; + fp-gpio-reset = <&tlmm 131 0x00>; + fp-gpio-enable = <&tlmm 101 0x00>; + pinctrl-names = "fp_en_init", "fp_dis_init"; + pinctrl-0 = <&fp_vdd_init &fp_irq_init>; + pinctrl-1 = <&fp_vdd_dis_init>; + status = "okay"; + }; +}; +&tlmm { + aw_irq: aw_irq { + mux { + pins = "gpio116"; + function = "gpio"; + }; + + config { + pins = "gpio116"; + drive-strength = <2>; + }; + }; + + aw_reset: aw_reset { + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + drive-strength = <2>; + bias-disable; + }; + }; + + fp_id0_init: fp_id0_init { + mux { + pins = "gpio90"; + function = "gpio"; + }; + + config { + pins = "gpio90"; + drive-strength = <2>; + bias-disable; /* No Pull */ + input-enable; + }; + }; + + tp_1v8_t0_active: tp_1v8_t0_active { + mux { + pins = "gpio119"; + function = "gpio"; + }; + config { + pins = "gpio119"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + tp_1v8_t0_suspend: tp_1v8_t0_suspend { + mux { + pins = "gpio119"; + function = "gpio"; + }; + config { + pins = "gpio119"; + drive-strength = <8>; + bias-pull-down; + }; + }; +}; + +/*for aw haptic start*/ +&qupv3_se7_i2c { + status = "ok"; + aw8697_haptic@5A { + compatible = "awinic,aw8697_haptic"; + reg = <0x5A>; + reset-gpio = <&tlmm 116 0x00>; + irq-gpio = <&tlmm 24 0x00>; + pinctrl-names = "default"; + pinctrl-0 = <&aw_irq &aw_reset>; + status = "okay"; + }; +}; +/*for aw haptic end*/ + + +/* for Battery & Charging STRAT */ +&qupv3_se8_i2c { + oneplus_fastchg@26{ + microchip,mcu-en-gpio = <&tlmm 10 0x00>; + microchip,usb-sw-2-gpio = <&tlmm 59 0x00>; + op,mcl_verion; + }; + +}; + +&pm8150b_charger { + /* for external ship mode suppot */ + op,stm-ctrl-gpio = <&tlmm 21 0x00>; + op,vbus-ctrl-gpio = <&pm8150_gpios 9 GPIO_ACTIVE_LOW>; +}; + +/* for Battery & Charging END */ + +/* @bsp,step motor START*/ +&pm8150b_gpios { + motor_mode0_gpio: motor_mode0_gpio { + pins = "gpio5"; /* GPIO 5 */ + function = "normal"; /* normal */ + output-high; + bias-disable; /* No Pull */ + }; + motor_mode0_hi_impedance: motor_mode0_hi_impedance { + pins = "gpio5"; /* GPIO 5 */ + function = "normal"; /* normal */ + bias-high-impedance; + }; + motor_boost_en: motor_boost_en { + pins = "gpio12"; /* GPIO 12 */ + function = "normal"; /* normal */ + output-low; + bias-disable; /* No Pull */ + }; +}; + +&pm8150l_gpios { + motor_pwm_config: motor_pwm_config { + pins = "gpio10"; + function = "func1"; + bias-disable; + power-source = <0>; + output-low; + qcom,drive-strength = <3>; + drive-push-pull; + }; + motor_mode1_gpio: motor_mode1_gpio { + pins = "gpio8"; + function = "normal"; + power-source = <0>; /* 3.6V */ + bias-disable; /* No Pull */ + output-low; /* digital output, no invert */ + qcom,drive-strength = <3>; /* LOW strength */ + }; + motor_dir_gpio: motor_dir_gpio { + pins = "gpio11"; + function = "normal"; + bias-disable; /* No Pull */ + power-source = <0>; /* VIN0 3.6V*/ + output-low; /* digital output, no invert */ + qcom,drive-strength = <3>; /* LOW strength */ + }; +}; + +&pm8150_gpios { + motor_sleep_gpio: motor_sleep_gpio { + pins = "gpio10"; + function = "normal"; + power-source = <0>; + bias-disable; + output-low; + }; + + fp_id1_init: fp_id1_init { + pins = "gpio3"; + function = "normal"; + power-source = <0>; + bias-disable; + input-enable; + }; +}; + +&vendor { + step_motor { + compatible = "oneplus,step-motor"; + status = "okay"; + + pwms = <&pm8150l_pwm 1 20000000>; + op,boost-en-pin = <&pm8150b_gpios 12 GPIO_ACTIVE_LOW>; + op,mode0-pin = <&pm8150b_gpios 5 GPIO_ACTIVE_LOW>; + op,mode1-pin = <&pm8150l_gpios 8 GPIO_ACTIVE_LOW>; + op,nsleep-pin = <&pm8150_gpios 10 GPIO_ACTIVE_LOW>; + op,dir-pin = <&pm8150l_gpios 11 GPIO_ACTIVE_LOW>; + op,step-pin = <&pm8150l_gpios 10 GPIO_ACTIVE_LOW>; + pinctrl-names = "boost", + "m0_gpio", + "m0_high_impedance", + "m1_gpio", + "sleep_gpio", + "dir_gpio", + "pwm_config"; + pinctrl-0 = <&motor_boost_en>; + pinctrl-1 = <&motor_mode0_gpio>; + pinctrl-2 = <&motor_mode0_hi_impedance>; + pinctrl-3 = <&motor_mode1_gpio>; + pinctrl-4 = <&motor_sleep_gpio>; + pinctrl-5 = <&motor_dir_gpio>; + pinctrl-6 = <&motor_pwm_config>; + }; +}; +/* @bsp, step motor END*/ + +/* @bsp, usb config START*/ +&usb2_phy0 { + qcom,param-override-seq = + <0x67 0x6c/*Disconnection voltage +21.56%*/ + 0x06 0x70/*Pre-emphasis:4x DC voltage level:+6.50%*/ + 0x28 0x74>; +}; + +&extcon_usb1 { + status = "disabled"; +}; + +&usb1 { + status = "disabled"; +}; + +/* @bsp, As QRD-DVT have this config, keep the same config + * for ldo18 power suspend + */ +&usb_qmp_dp_phy { + vdd-supply = <&pm8150_l18>; + qcom,vdd-voltage-level = <0 912000 912000>; +}; + +&sde_dp { + vdda-0p9-supply = <&pm8150_l18>; + qcom,phy-supply-entries { + qcom,phy-supply-entry@0 { + qcom,supply-min-voltage = <880000>; + qcom,supply-max-voltage = <912000>; + }; + }; +}; +/* @bsp, usb config END*/ + +&motor_pl { + structure,id = <1>;//T0 +}; + + + diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index 412b73e697f845babcbcb5940f06bd59625113ae..9cc532981ad64ed7464aa23d0d0224678491c674 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -91,14 +91,15 @@ <0x0 0xc2 0 IRQ_TYPE_NONE>, <0x0 0xc3 0 IRQ_TYPE_NONE>, <0x0 0xc5 0 IRQ_TYPE_NONE>, + <0x0 0xc6 0 IRQ_TYPE_NONE>, <0x0 0xc8 0 IRQ_TYPE_NONE>, <0x0 0xc9 0 IRQ_TYPE_NONE>; interrupt-names = "pm8150_gpio1", "pm8150_gpio3", "pm8150_gpio4", "pm8150_gpio6", - "pm8150_gpio9", "pm8150_gpio10"; + "pm8150_gpio7","pm8150_gpio9", "pm8150_gpio10"; gpio-controller; #gpio-cells = <2>; - qcom,gpios-disallowed = <2 5 7 8>; + qcom,gpios-disallowed = <2 5 8>; }; pm8150_sdam_2: sdam@b100 { diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi index 826ba938880105017d761e83afe09524fddefae7..bb303374a93991d206340a784f2cfa0f1e10c610 100644 --- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi @@ -544,6 +544,7 @@ qcom,wf-brake-pattern = [03 00 00 00]; qcom,lra-auto-resonance-disable; }; + }; }; }; @@ -667,7 +668,7 @@ }; soc { - polling-delay-passive = <100>; + polling-delay-passive = <1000>; polling-delay = <0>; thermal-governor = "low_limits_cap"; thermal-sensors = <&bcl_soc>; @@ -675,7 +676,12 @@ trips { soc_trip:soc-trip { - temperature = <10>; + temperature = <5>; + hysteresis = <0>; + type = "passive"; + }; + soc_trip2:soc-trip2 { + temperature = <15>; hysteresis = <0>; type = "passive"; }; diff --git a/arch/arm64/boot/dts/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/pm8150l.dtsi index 4ff7b0c35d36439d75e0ad3c2982f32eb1004cf9..78b9847f66f5bd7edf9781395bb99fd36eeba627 100644 --- a/arch/arm64/boot/dts/qcom/pm8150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150l.dtsi @@ -363,6 +363,14 @@ }; }; + pm8150l_pwm: qcom,pwms@bc00 { + compatible = "qcom,pwm-lpg"; + reg = <0xbc00 0x200>; + reg-names = "lpg-base"; + #pwm-cells = <2>; + qcom,num-lpg-channels = <2>; + }; + pm8150l_rgb_led: qcom,leds@d000 { compatible = "qcom,tri-led"; reg = <0xd000 0x100>; diff --git a/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi b/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi index 5c40e69040045b0c37681a6b8fbb28c792b06b5d..5f610c63e67c2ab9ec32787332ae16941e756a65 100644 --- a/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmmagpie-sde-display.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -104,7 +104,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sw43404_amoled_video>; }; @@ -115,7 +115,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sw43404_amoled_cmd>; }; @@ -126,7 +126,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sw43404_amoled_fhd_plus_cmd>; }; @@ -137,7 +137,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sim_vid>; }; @@ -148,7 +148,7 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_dual_sim_vid>; }; @@ -159,7 +159,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sim_cmd>; }; @@ -170,7 +170,7 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_dual_sim_cmd>; }; @@ -181,7 +181,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sim_dsc_375_cmd>; }; @@ -192,7 +192,7 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_dual_sim_dsc_375_cmd>; }; @@ -203,7 +203,7 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_dual_sharp_wqhd_video>; }; @@ -214,7 +214,7 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_dual_sharp_wqhd_cmd>; }; @@ -225,7 +225,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_rm69298_truly_amoled_video>; }; @@ -236,7 +236,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_rm69298_truly_amoled_cmd>; }; @@ -247,7 +247,7 @@ qcom,dsi-ctrl-num = <1>; qcom,dsi-phy-num = <1>; - qcom,dsi-select-clocks = "src_byte_clk1", "src_pixel_clk1"; + qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_video>; }; @@ -258,7 +258,7 @@ qcom,dsi-ctrl-num = <1>; qcom,dsi-phy-num = <1>; - qcom,dsi-select-clocks = "src_byte_clk1", "src_pixel_clk1"; + qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_cmd>; }; @@ -269,7 +269,7 @@ qcom,dsi-ctrl-num = <1>; qcom,dsi-phy-num = <1>; - qcom,dsi-select-clocks = "src_byte_clk1", "src_pixel_clk1"; + qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_video>; }; @@ -280,7 +280,7 @@ qcom,dsi-ctrl-num = <1>; qcom,dsi-phy-num = <1>; - qcom,dsi-select-clocks = "src_byte_clk1", "src_pixel_clk1"; + qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_cmd>; }; @@ -295,8 +295,8 @@ <&mdss_dsi0_pll PCLK_MUX_0_CLK>, <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, <&mdss_dsi1_pll PCLK_MUX_1_CLK>; - clock-names = "src_byte_clk0", "src_pixel_clk0", - "src_byte_clk1", "src_pixel_clk1"; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_te_active &disp_pins_default>; @@ -341,8 +341,8 @@ <&mdss_dsi0_pll PCLK_MUX_0_CLK>, <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, <&mdss_dsi1_pll PCLK_MUX_1_CLK>; - clock-names = "src_byte_clk0", "src_pixel_clk0", - "src_byte_clk1", "src_pixel_clk1"; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_te1_active>; @@ -386,8 +386,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,mdss-dsi-min-refresh-rate = <55>; - qcom,mdss-dsi-max-refresh-rate = <60>; + qcom,dsi-supported-dfps-list = <60 57 55>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp"; qcom,mdss-dsi-display-timings { @@ -456,8 +455,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - qcom,mdss-dsi-min-refresh-rate = <55>; - qcom,mdss-dsi-max-refresh-rate = <60>; + qcom,dsi-supported-dfps-list = <60 57 55>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp"; qcom,mdss-dsi-display-timings { @@ -666,9 +664,7 @@ qcom,mdss-dsi-panel-status-value = <0x9c>; qcom,mdss-dsi-panel-on-check-value = <0x9c>; qcom,mdss-dsi-panel-status-read-length = <1>; - - qcom,mdss-dsi-min-refresh-rate = <48>; - qcom,mdss-dsi-max-refresh-rate = <60>; + qcom,dsi-supported-dfps-list = <60 55 48>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; diff --git a/arch/arm64/boot/dts/qcom/sdmshrike-sde-display.dtsi b/arch/arm64/boot/dts/qcom/sdmshrike-sde-display.dtsi index 97ed20b4afbf1a1abd0ae493c377531a6f3e28dd..4687aa1a5dc6720b4dd4ab74de58d0dbd217f1f8 100644 --- a/arch/arm64/boot/dts/qcom/sdmshrike-sde-display.dtsi +++ b/arch/arm64/boot/dts/qcom/sdmshrike-sde-display.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -111,7 +111,7 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sharp_4k_dsc_video>; }; @@ -122,7 +122,7 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sharp_4k_dsc_cmd>; }; @@ -133,7 +133,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sharp_1080_cmd>; }; @@ -144,7 +144,7 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_dual_sharp_1080_120hz_cmd>; }; @@ -155,7 +155,7 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_dual_nt35597_truly_video>; }; @@ -166,7 +166,7 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_dual_nt35597_truly_cmd>; }; @@ -177,7 +177,7 @@ qcom,dsi-ctrl-num = <1>; qcom,dsi-phy-num = <1>; - qcom,dsi-select-clocks = "src_byte_clk1", "src_pixel_clk1"; + qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,dsi-panel = <&dsi_nt35597_truly_dsc_cmd>; }; @@ -188,7 +188,7 @@ qcom,dsi-ctrl-num = <1>; qcom,dsi-phy-num = <1>; - qcom,dsi-select-clocks = "src_byte_clk1", "src_pixel_clk1"; + qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,dsi-panel = <&dsi_nt35597_truly_dsc_video>; }; @@ -199,7 +199,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sim_vid>; }; @@ -210,7 +210,7 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_dual_sim_vid>; }; @@ -221,7 +221,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sim_cmd>; }; @@ -232,7 +232,7 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_dual_sim_cmd>; }; @@ -243,7 +243,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sim_dsc_375_cmd>; }; @@ -254,7 +254,7 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_dual_sim_dsc_375_cmd>; }; @@ -265,7 +265,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sw43404_amoled_cmd>; }; @@ -276,7 +276,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_cmd>; @@ -288,7 +288,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_video>; }; @@ -303,8 +303,8 @@ <&mdss_dsi0_pll PCLK_MUX_0_CLK>, <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, <&mdss_dsi1_pll PCLK_MUX_1_CLK>; - clock-names = "src_byte_clk0", "src_pixel_clk0", - "src_byte_clk1", "src_pixel_clk1"; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; diff --git a/arch/arm64/boot/dts/qcom/sm6150-sde-display.dtsi b/arch/arm64/boot/dts/qcom/sm6150-sde-display.dtsi index 068f9892ad2c2fdc3848b208b95268d3a7b61174..cb27472d675b512189f6f6693aa29b04e40eb349 100644 --- a/arch/arm64/boot/dts/qcom/sm6150-sde-display.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6150-sde-display.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -100,7 +100,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sim_vid>; }; @@ -111,7 +111,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sim_cmd>; }; @@ -122,7 +122,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_hx83112a_truly_video>; }; @@ -133,7 +133,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_td4328_truly_video>; }; @@ -144,7 +144,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_td4328_truly_cmd>; }; @@ -155,7 +155,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_rm69298_truly_amoled_video>; }; @@ -166,7 +166,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_rm69298_truly_amoled_cmd>; }; @@ -177,7 +177,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sharp_split_link_wuxga_video>; }; @@ -190,7 +190,7 @@ clocks = <&mdss_dsi0_pll BYTE0_MUX_CLK>, <&mdss_dsi0_pll PIX0_MUX_CLK>; - clock-names = "src_byte_clk0", "src_pixel_clk0"; + clock-names = "mux_byte_clk0", "mux_pixel_clk0"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; @@ -321,8 +321,9 @@ &dsi_hx83112a_truly_video { qcom,mdss-dsi-t-clk-post = <0x0e>; qcom,mdss-dsi-t-clk-pre = <0x31>; - qcom,mdss-dsi-min-refresh-rate = <48>; - qcom,mdss-dsi-max-refresh-rate = <60>; +// qcom,mdss-dsi-min-refresh-rate = <48>; +// qcom,mdss-dsi-max-refresh-rate = <60>; + qcom,dsi-supported-dfps-list = <60 55 53 43>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; diff --git a/arch/arm64/boot/dts/qcom/sm8150-audio.dtsi b/arch/arm64/boot/dts/qcom/sm8150-audio.dtsi index 61b45d2c279d730b7f6b8b1cb87df700cbf575e7..04dc1f1d22fd955a41c01a9bb6c3da96671263b7 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-audio.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-audio.dtsi @@ -155,9 +155,9 @@ &qupv3_se4_i2c { status = "ok"; - fsa4480: fsa4480@43 { + fsa4480: fsa4480@42 { compatible = "qcom,fsa4480-i2c"; - reg = <0x43>; + reg = <0x42>; pinctrl-names = "default"; pinctrl-0 = <&fsa_usbc_ana_en>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150-camera-sensor-mtp.dtsi b/arch/arm64/boot/dts/qcom/sm8150-camera-sensor-mtp.dtsi index 0803db1bce62be7bfbcb659695e86b7151ade9f8..83fe2e613aeae60b52a102e8a3cc787c4a6f3880 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-camera-sensor-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-camera-sensor-mtp.dtsi @@ -109,6 +109,7 @@ actuator_triple_rear_aux2_regulator: gpio-regulator@6 { compatible = "regulator-fixed"; + status = "disable"; reg = <0x06 0x00>; regulator-name = "actuator_triple_rear_aux2_regulator"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-cdp.dtsi b/arch/arm64/boot/dts/qcom/sm8150-cdp.dtsi index 84c11b5540db0b9b4c9f931c2b770177257d1184..417730a9295903e8b0ca9529ad5c385637425642 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-cdp.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-cdp.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -41,13 +41,13 @@ extcon_usb1: extcon_usb1 { compatible = "linux,extcon-usb-gpio"; vbus-gpio = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>; - id-gpio = <&tlmm 101 GPIO_ACTIVE_HIGH>; + /*id-gpio = <&tlmm 101 GPIO_ACTIVE_HIGH>; GPIO 101 for fingerprint VDD enable*/ vbus-out-gpio = <&pm8150_gpios 9 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; + /*pinctrl-names = "default"; pinctrl-0 = <&usb2_vbus_det_default &usb2_id_det_default - &usb2_vbus_boost_default>; + &usb2_vbus_boost_default>; GPIO 101 for fingerprint VDD enable*/ }; }; @@ -290,6 +290,7 @@ compatible = "qcom,ufs-phy-qmp-v4"; vdda-phy-supply = <&pm8150_l5>; + vdda-phy-always-on; vdda-pll-supply = <&pm8150l_l3>; vdda-phy-max-microamp = <90200>; vdda-pll-max-microamp = <19000>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp-overlay.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp-overlay.dts index 2f454362dfa6fa34f84ec889d8fc1ad667957ab6..aa13607213a47be80279e82a22eba0e15f6a6dba 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp-overlay.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp-overlay.dts @@ -21,6 +21,11 @@ #include "sm8150-mtp.dtsi" #include "sm8150-mtp-audio-overlay.dtsi" +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-v2.dtsi" +#include "guacamole.dtsi" +#include "guacamole_t0.dtsi" + / { model = "MTP"; compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi b/arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi index ae56d903b41aa196366b91d2f91acbd929f299ca..a2b1e5ac74654001b8d90ff2ca48b6552f42ddaa 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dtsi @@ -50,14 +50,15 @@ extcon_usb1: extcon_usb1 { compatible = "linux,extcon-usb-gpio"; - vbus-gpio = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>; - id-gpio = <&tlmm 101 GPIO_ACTIVE_HIGH>; + /*pm8150_gpios 10 is for step motor, use the dummy gpio 165 for driver probe */ + vbus-gpio = <&tlmm 165 GPIO_ACTIVE_HIGH>; + /*id-gpio = <&tlmm 101 GPIO_ACTIVE_HIGH>; GPIO 101 for fingerprint VDD enable */ vbus-out-gpio = <&pm8150_gpios 9 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; + /*pinctrl-names = "default"; pinctrl-0 = <&usb2_vbus_det_default &usb2_id_det_default - &usb2_vbus_boost_default>; + &usb2_vbus_boost_default>; GPIO 101 for fingerprint VDD enable*/ }; }; @@ -92,7 +93,7 @@ }; }; - qcom,qbt1000 { + qcomqbt1000:qcom,qbt1000 { compatible = "qcom,qbt1000"; clock-names = "core", "iface"; clock-frequency = <25000000>; @@ -265,6 +266,7 @@ compatible = "qcom,ufs-phy-qmp-v4"; vdda-phy-supply = <&pm8150_l5>; + vdda-phy-always-on; vdda-pll-supply = <&pm8150l_l3>; vdda-phy-max-microamp = <90200>; vdda-pll-max-microamp = <19000>; @@ -314,8 +316,9 @@ qcom,fg-esr-timer-dischg-fast = <0 7>; qcom,fg-esr-timer-chg-slow = <0 96>; qcom,fg-esr-timer-dischg-slow = <0 96>; - qcom,fg-esr-cal-soc-thresh = <26 230>; - qcom,fg-esr-cal-temp-thresh = <10 40>; + /*op disable ers calibration*/ + /*qcom,fg-esr-cal-soc-thresh = <26 230>;*/ + /*qcom,fg-esr-cal-temp-thresh = <10 40>;*/ }; &sdhc_2 { @@ -588,17 +591,10 @@ }; skin-msm-therm { - polling-delay-passive = <0>; + polling-delay-passive = <2000>; polling-delay = <0>; - thermal-governor = "user_space"; + thermal-governor = "step_wise"; thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; }; pa-therm2 { diff --git a/arch/arm64/boot/dts/qcom/sm8150-oem-camera-t0.dtsi b/arch/arm64/boot/dts/qcom/sm8150-oem-camera-t0.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..49c13398685db62d4d568f7438d87698b2ec7a63 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-oem-camera-t0.dtsi @@ -0,0 +1,1044 @@ +&pm8150_gpios{ + cam_sensor_laser { + cam_sensor_laser_xsdn_active: cam_sensor_laser_xsdn_active { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_laser_xsdn_suspend: cam_sensor_laser_xsdn_suspend{ + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; +}; + +&pm8150b_gpios{ + cam_sensor_laser { + cam_sensor_laser_intr_active: cam_sensor_laser_intr_active { + pins = "gpio10"; + function = "normal"; + power-source = <0>; + //bias-pull-up; + bias-disable; + output-high; + input-enable; + }; + + cam_sensor_laser_intr_suspend: cam_sensor_laser_intr_suspend{ + pins = "gpio10"; + function = "normal"; + power-source = <0>; + //bias-pull-down; + bias-disable; + output-low; + input-enable; + }; + }; +}; + +&pm8150l_gpios{ + cam_sensor_pmi_gpio { + cam_sensor_rear_0_dvdd_active: cam_sensor_rear_0_dvdd_active { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_0_dvdd_suspend: cam_sensor_rear_0_dvdd_suspend { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_rear_2_ana_active: cam_sensor_rear_2_ana_active { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_2_ana_suspend: cam_sensor_rear_2_ana_suspend { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_rear_2_af_active: cam_sensor_rear_2_af_active { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_2_af_suspend: cam_sensor_rear_2_af_suspend { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; + + cam_sensor_front_0_ana { + cam_sensor_front_0_ana_active: cam_sensor_front_0_ana_active { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_ana_suspend: cam_sensor_front_0_ana_suspend { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; +}; + +&soc { +//laser start + stmvl53l1: st,stmvl53l1@0 { + compatible = "st,stmvl53l1"; + //reg = <0x29>; + //avdd-supply = <&pm8150l_bob>; + laser_vdd-supply = <&pm8150l_l1>; + pinctrl-names = "laser_default", "laser_suspend"; + pinctrl-0 = <&cam_sensor_laser_xsdn_active + &cam_sensor_laser_pwren_active + &cam_sensor_laser_intr_active>; + pinctrl-1 = <&cam_sensor_laser_xsdn_suspend + &cam_sensor_laser_pwren_suspend + &cam_sensor_laser_intr_suspend>; + xsdn-gpio = <&pm8150_gpios 4 GPIO_ACTIVE_HIGH>; + pwren-gpio = <&tlmm 26 0>; + intr-gpio = <&pm8150b_gpios 10 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&spmi_bus>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + }; +//laser end + + led_flash_rear_0: qcom,camera-flash@7 { + cell-index = <7>; + reg = <0x07 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_rear_1: qcom,camera-flash@8 { + cell-index = <8>; + reg = <0x08 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; +}; + +&cam_cci0 { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + shared-gpios = <14 13>; + pinctrl-names = "cam_res_mgr_default", "cam_res_mgr_suspend"; + status = "ok"; + pinctrl-0 = <&cam_sensor_rear_0_mclk_active + &cam_sensor_rear_1_mclk_active>; + pinctrl-1 = <&cam_sensor_rear_0_mclk_suspend + &cam_sensor_rear_1_mclk_suspend>; + }; + + actuator_rear_0: qcom,actuator@7 { + cell-index = <7>; + reg = <0x7>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_0_vaf_suspend>; + gpios = <&tlmm 25 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_0"; + }; + + actuator_rear_1: qcom,actuator@8 { + cell-index = <8>; + reg = <0x8>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_1_vaf_suspend>; + gpios = <&tlmm 35 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + actuator_rear_2: qcom,actuator@9 { + cell-index = <9>; + reg = <0x9>; + compatible = "qcom,actuator"; + cci-device = <1>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_af_active>; + pinctrl-1 = <&cam_sensor_rear_2_af_suspend>; + gpios = <&pm8150l_gpios 4 GPIO_ACTIVE_HIGH>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + ois_rear_0: qcom,ois@02{ + cell-index = <2>; + reg = <2>; + compatible = "qcom,ois"; + cam_vio-supply = <&pm8150l_l1>; + cam_vdig-supply = <&pm8009_l6>;//s5k3m5 ois + cam_vaf-supply = <&pm8009_l5>; + regulator-names = "cam_vio", "cam_vdig", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2856000 2800000>; + rgltr-max-voltage = <0 2856000 2800000>; + rgltr-load-current = <0 80000 0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + }; + + ois_rear_1: qcom,ois@3 { + cell-index = <3>; + reg = <3>; + compatible = "qcom,ois"; + cam_vio-supply = <&pm8150l_l1>; + cam_vdig-supply = <&pm8009_l5>;//imx586 ois + cam_vaf-supply = <&pm8009_l6>; + regulator-names = "cam_vio", "cam_vdig", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2800000 2856000>; + rgltr-max-voltage = <0 2800000 2856000>; + rgltr-load-current = <0 80000 0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + }; + + eeprom_rear_0: qcom,eeprom@7 { + cell-index = <7>; + reg = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1104000 0>; + rgltr-max-voltage = <0 3300000 1104000 0>; + rgltr-load-current = <0 80000 1100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active>; + pinctrl-1 = <&cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_1: qcom,eeprom@8 { + cell-index = <8>; + reg = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active>; + pinctrl-1 = <&cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front_0: qcom,eeprom@9 { + cell-index = <9>; + reg = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_2: qcom,eeprom@10 { + cell-index = <10>; + reg = <0xA>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_mclk_active + &cam_sensor_rear_2_rest_active + &cam_sensor_rear_2_ana_active>; + pinctrl-1 = <&cam_sensor_rear_2_mclk_suspend + &cam_sensor_rear_2_rest_suspend + &cam_sensor_rear_2_ana_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2 >; + gpio-req-tbl-flags = <1 0 0 >; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA_3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_0>; + actuator-src = <&actuator_rear_0>; + ois-src = <&ois_rear_0>; + eeprom-src = <&eeprom_rear_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1104000 0>; + rgltr-max-voltage = <0 3300000 1104000 0>; + rgltr-load-current = <0 80000 1100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_ana2_active + &cam_sensor_rear_0_dvdd_active>; + pinctrl-1 = <&cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_ana2_suspend + &cam_sensor_rear_0_dvdd_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>, + <&tlmm 29 0>, + <&pm8150l_gpios 1 GPIO_ACTIVE_HIGH>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-custom1 = <3>; + gpio-custom2 = <4>; + gpio-req-tbl-num = <0 1 2 3 4>; + gpio-req-tbl-flags = <1 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_VANA2_0", + "CAM_PVDD"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_1>; + led-flash-src = <&led_flash_rear_1>; + eeprom-src = <&eeprom_rear_0>;//for imx586&s5k3m5 use same eeprom located on master imx586 + ois-src = <&ois_rear_1>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active>; + pinctrl-1 = <&cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + reg = <0x03>; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_rear_2>; + actuator-src = <&actuator_rear_2>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_mclk_active + &cam_sensor_rear_2_rest_active + &cam_sensor_rear_2_ana_active>; + pinctrl-1 = <&cam_sensor_rear_2_mclk_suspend + &cam_sensor_rear_2_rest_suspend + &cam_sensor_rear_2_ana_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2 >; + gpio-req-tbl-flags = <1 0 0 >; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA_3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; + +&tlmm { + cam_sensor_rear_0_mclk_active: cam_sensor_rear_0_mclk_active { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_mclk_suspend: cam_sensor_rear_0_mclk_suspend { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_active: cam_sensor_rear_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_suspend: cam_sensor_rear_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_active: cam_sensor_rear_0_ana_active { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_suspend: cam_sensor_rear_0_ana_suspend { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana2_active: cam_sensor_rear_0_ana2_active { + /* VANA */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana2_suspend: cam_sensor_rear_0_ana2_suspend { + /* VANA */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_active: cam_sensor_rear_0_vaf_active { + /* AF */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_suspend: cam_sensor_rear_0_vaf_suspend { + /* AF */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_active: cam_sensor_rear_1_mclk_active { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_suspend: cam_sensor_rear_1_mclk_suspend { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_active: cam_sensor_rear_1_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_suspend: cam_sensor_rear_1_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_active: cam_sensor_rear_1_ana_active { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_suspend: cam_sensor_rear_1_ana_suspend { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_active: cam_sensor_rear_1_vaf_active { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_suspend: cam_sensor_rear_1_vaf_suspend { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_active: cam_sensor_front_0_mclk_active { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_suspend: cam_sensor_front_0_mclk_suspend { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_active: cam_sensor_front_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_suspend: cam_sensor_front_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_mclk_active: cam_sensor_rear_2_mclk_active { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_mclk_suspend: cam_sensor_rear_2_mclk_suspend { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_rest_active: cam_sensor_rear_2_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_rest_suspend: cam_sensor_rear_2_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_pwren_active: cam_sensor_laser_pwren_active { + /* RESET, STANDBY */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_pwren_suspend: cam_sensor_laser_pwren_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150-oem-camera-v2.dtsi b/arch/arm64/boot/dts/qcom/sm8150-oem-camera-v2.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..e80107dee1c10dbca329b7305dce8f95d5cb1395 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-oem-camera-v2.dtsi @@ -0,0 +1,1035 @@ +&pm8150l_gpios{ + cam_sensor_pmi_gpio { + cam_sensor_rear_0_dvdd_active: cam_sensor_rear_0_dvdd_active { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_0_dvdd_suspend: cam_sensor_rear_0_dvdd_suspend { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_rear_2_ana_active: cam_sensor_rear_2_ana_active { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_2_ana_suspend: cam_sensor_rear_2_ana_suspend { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + + cam_sensor_rear_2_af_active: cam_sensor_rear_2_af_active { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_rear_2_af_suspend: cam_sensor_rear_2_af_suspend { + pins = "gpio4"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; + + cam_sensor_front_0_ana { + cam_sensor_front_0_ana_active: cam_sensor_front_0_ana_active { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + output-low; + input-disable; + }; + + cam_sensor_front_0_ana_suspend: cam_sensor_front_0_ana_suspend { + pins = "gpio12"; + function = "normal"; + power-source = <0>; + bias-pull-down; + input-disable; + }; + }; +}; + +&soc { +//laser start + stmvl53l1: st,stmvl53l1@0 { + compatible = "st,stmvl53l1"; + //reg = <0x29>; + //avdd-supply = <&pm8150l_bob>; + laser_vdd-supply = <&pm8150l_l1>; + pinctrl-names = "laser_default", "laser_suspend"; + pinctrl-0 = <&cam_sensor_laser_xsdn_active + &cam_sensor_laser_pwren_active + &cam_sensor_laser_intr_active>; + pinctrl-1 = <&cam_sensor_laser_xsdn_suspend + &cam_sensor_laser_pwren_suspend + &cam_sensor_laser_intr_suspend>; + xsdn-gpio = <&tlmm 24 0>; + pwren-gpio = <&tlmm 26 0>; + intr-gpio = <&tlmm 131 0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + }; +//laser end +}; + +&cam_cci0 { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + shared-gpios = <14 13>; + pinctrl-names = "cam_res_mgr_default", "cam_res_mgr_suspend"; + status = "ok"; + pinctrl-0 = <&cam_sensor_rear_0_mclk_active + &cam_sensor_rear_1_mclk_active>; + pinctrl-1 = <&cam_sensor_rear_0_mclk_suspend + &cam_sensor_rear_1_mclk_suspend>; + }; + + actuator_rear_0: qcom,actuator@7 { + cell-index = <7>; + reg = <0x7>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_0_vaf_suspend>; + gpios = <&tlmm 25 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_0"; + }; + + actuator_rear_1: qcom,actuator@8 { + cell-index = <8>; + reg = <0x8>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_vaf_active>; + pinctrl-1 = <&cam_sensor_rear_1_vaf_suspend>; + gpios = <&tlmm 35 0>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + actuator_rear_2: qcom,actuator@9 { + cell-index = <9>; + reg = <0x9>; + compatible = "qcom,actuator"; + cci-device = <1>; + cci-master = <1>; + cam_vaf-supply = <&pm8150l_bob>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <3300000>; + rgltr-max-voltage = <3300000>; + rgltr-load-current = <0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_af_active>; + pinctrl-1 = <&cam_sensor_rear_2_af_suspend>; + gpios = <&pm8150l_gpios 4 GPIO_ACTIVE_HIGH>; + gpio-vaf = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CAM_VAF_1"; + }; + + ois_rear_0: qcom,ois@2 { + cell-index = <2>; + reg = <2>; + compatible = "qcom,ois"; + cam_vio-supply = <&pm8150l_l1>; + cam_vdig-supply = <&pm8009_l6>;//s5k3m5 ois + cam_vaf-supply = <&pm8009_l5>; + regulator-names = "cam_vio", "cam_vdig", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2856000 2800000>; + rgltr-max-voltage = <0 2856000 2800000>; + rgltr-load-current = <0 80000 0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + }; + + ois_rear_1: qcom,ois@3 { + cell-index = <3>; + reg = <3>; + compatible = "qcom,ois"; + cam_vio-supply = <&pm8150l_l1>; + cam_vdig-supply = <&pm8009_l5>;//imx586 ois + cam_vaf-supply = <&pm8009_l6>; + regulator-names = "cam_vio", "cam_vdig", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 2800000 2856000>; + rgltr-max-voltage = <0 2800000 2856000>; + rgltr-load-current = <0 80000 0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + }; + + eeprom_rear_0: qcom,eeprom@7 { + cell-index = <7>; + reg = <7>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1104000 0>; + rgltr-max-voltage = <0 3300000 1104000 0>; + rgltr-load-current = <0 80000 1100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active>; + pinctrl-1 = <&cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_1: qcom,eeprom@8 { + cell-index = <8>; + reg = <8>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1050000 0>; + rgltr-max-voltage = <0 3300000 1050000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active>; + pinctrl-1 = <&cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front_0: qcom,eeprom@9 { + cell-index = <9>; + reg = <9>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_2: qcom,eeprom@10 { + cell-index = <10>; + reg = <0xA>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1050000 0>; + rgltr-max-voltage = <0 3300000 1050000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_mclk_active + &cam_sensor_rear_2_rest_active + &cam_sensor_rear_2_ana_active>; + pinctrl-1 = <&cam_sensor_rear_2_mclk_suspend + &cam_sensor_rear_2_rest_suspend + &cam_sensor_rear_2_ana_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2 >; + gpio-req-tbl-flags = <1 0 0 >; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA_3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + reg = <0x0>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear>; + actuator-src = <&actuator_rear_0>; + ois-src = <&ois_rear_0>; + eeprom-src = <&eeprom_rear_1>;//for imx586&s5k3m5 use same eeprom located on slave s5k3m5 + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1104000 0>; + rgltr-max-voltage = <0 3300000 1104000 0>; + rgltr-load-current = <0 80000 1100000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_0_rest_active + &cam_sensor_rear_0_ana_active + &cam_sensor_rear_0_ana2_active + &cam_sensor_rear_0_dvdd_active>; + pinctrl-1 = <&cam_sensor_rear_0_rest_suspend + &cam_sensor_rear_0_ana_suspend + &cam_sensor_rear_0_ana2_suspend + &cam_sensor_rear_0_dvdd_suspend>; + gpios = <&tlmm 14 0>, + <&tlmm 30 0>, + <&tlmm 11 0>, + <&tlmm 29 0>, + <&pm8150l_gpios 1 GPIO_ACTIVE_HIGH>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-custom1 = <3>; + gpio-custom2 = <4>; + gpio-req-tbl-num = <0 1 2 3 4>; + gpio-req-tbl-flags = <1 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET0", + "CAM_VANA_0", + "CAM_VANA2_0", + "CAM_PVDD"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + reg = <0x1>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_1>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&eeprom_rear_1>; + ois-src = <&ois_rear_1>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1050000 0>; + rgltr-max-voltage = <0 3300000 1050000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_1_rest_active + &cam_sensor_rear_1_ana_active>; + pinctrl-1 = <&cam_sensor_rear_1_rest_suspend + &cam_sensor_rear_1_ana_suspend>; + gpios = <&tlmm 13 0>, + <&tlmm 28 0>, + <&tlmm 148 0>; + use-shared-clk; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET1", + "CAM_VANA_1"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front_0>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1056000 0>; + rgltr-max-voltage = <0 3300000 1056000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_front_0_mclk_active + &cam_sensor_front_0_rest_active + &cam_sensor_front_0_ana_active>; + pinctrl-1 = <&cam_sensor_front_0_mclk_suspend + &cam_sensor_front_0_rest_suspend + &cam_sensor_front_0_ana_suspend>; + gpios = <&tlmm 15 0>, + <&tlmm 12 0>, + <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA_2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + qcom,cam-sensor@3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + reg = <0x03>; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_rear_2>; + actuator-src = <&actuator_rear_2>; + cam_vio-supply = <&pm8150l_l1>; + cam_vana-supply = <&pm8150l_bob>; + cam_vdig-supply = <&pm8009_l4>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3300000 1050000 0>; + rgltr-max-voltage = <0 3300000 1050000 0>; + rgltr-load-current = <0 80000 1050000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_rear_2_mclk_active + &cam_sensor_rear_2_rest_active + &cam_sensor_rear_2_ana_active>; + pinctrl-1 = <&cam_sensor_rear_2_mclk_suspend + &cam_sensor_rear_2_rest_suspend + &cam_sensor_rear_2_ana_suspend>; + gpios = <&tlmm 16 0>, + <&tlmm 23 0>, + <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2 >; + gpio-req-tbl-flags = <1 0 0 >; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA_3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; + +&tlmm { + cam_sensor_rear_0_mclk_active: cam_sensor_rear_0_mclk_active { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_mclk_suspend: cam_sensor_rear_0_mclk_suspend { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio14"; + function = "cam_mclk"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_active: cam_sensor_rear_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_rest_suspend: cam_sensor_rear_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio30"; + function = "gpio"; + }; + + config { + pins = "gpio30"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_active: cam_sensor_rear_0_ana_active { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana_suspend: cam_sensor_rear_0_ana_suspend { + /* VANA */ + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana2_active: cam_sensor_rear_0_ana2_active { + /* VANA */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_ana2_suspend: cam_sensor_rear_0_ana2_suspend { + /* VANA */ + mux { + pins = "gpio29"; + function = "gpio"; + }; + + config { + pins = "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_active: cam_sensor_rear_0_vaf_active { + /* AF */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_0_vaf_suspend: cam_sensor_rear_0_vaf_suspend { + /* AF */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_active: cam_sensor_rear_1_mclk_active { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_mclk_suspend: cam_sensor_rear_1_mclk_suspend { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio13"; + function = "cam_mclk"; + }; + + config { + pins = "gpio13"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_active: cam_sensor_rear_1_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_rest_suspend: cam_sensor_rear_1_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio28"; + function = "gpio"; + }; + config { + pins = "gpio28"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_active: cam_sensor_rear_1_ana_active { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_ana_suspend: cam_sensor_rear_1_ana_suspend { + /* VANA */ + mux { + pins = "gpio148"; + function = "gpio"; + }; + + config { + pins = "gpio148"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_active: cam_sensor_rear_1_vaf_active { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_1_vaf_suspend: cam_sensor_rear_1_vaf_suspend { + /* ACTUATOR POWER */ + mux { + pins = "gpio35"; + function = "gpio"; + }; + + config { + pins = "gpio35"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_active: cam_sensor_front_0_mclk_active { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_mclk_suspend: cam_sensor_front_0_mclk_suspend { + /* MCLK2 */ + mux { + /* CLK, DATA */ + pins = "gpio15"; + function = "cam_mclk"; + }; + + config { + pins = "gpio15"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_active: cam_sensor_front_0_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_0_rest_suspend: cam_sensor_front_0_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_mclk_active: cam_sensor_rear_2_mclk_active { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_mclk_suspend: cam_sensor_rear_2_mclk_suspend { + /* MCLK3 */ + mux { + /* CLK, DATA */ + pins = "gpio16"; + function = "cam_mclk"; + }; + + config { + pins = "gpio16"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_rest_active: cam_sensor_rear_2_rest_active { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_2_rest_suspend: cam_sensor_rear_2_rest_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_xsdn_active: cam_sensor_laser_xsdn_active { + /* RESET, STANDBY */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_xsdn_suspend: cam_sensor_laser_xsdn_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_pwren_active: cam_sensor_laser_pwren_active { + /* RESET, STANDBY */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_pwren_suspend: cam_sensor_laser_pwren_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_intr_active: cam_sensor_laser_intr_active { + /* RESET, STANDBY */ + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_laser_intr_suspend: cam_sensor_laser_intr_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150-oem.dtsi b/arch/arm64/boot/dts/qcom/sm8150-oem.dtsi new file mode 100755 index 0000000000000000000000000000000000000000..1b36b1a853fb8a868da5996b56dc0f1bba3d0fa2 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8150-oem.dtsi @@ -0,0 +1,1183 @@ +/*recommand add our code to this dtsi this part is oem code*/ +&soc { + dsi_samsung_sofef00_m_cmd_display: qcom,dsi-display@23 { + label = "dsi_samsung_sofef00_m_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-panel = <&dsi_samsung_sofef00_m_cmd>; + }; + + dsi_samsung_s6e3fc2x01_cmd_display: qcom,dsi-display@24 { + label = "dsi_samsung_s6e3fc2x01_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-panel = <&dsi_samsung_s6e3fc2x01_cmd>; + }; + + dsi_samsung_sofef00_m_video_display: qcom,dsi-display@26 { + label = "dsi_samsung_sofef00_m_video_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-panel = <&dsi_samsung_sofef00_m_video>; + }; + + dsi_samsung_oneplus_dsc_cmd_display: qcom,dsi-display@28 { + label = "dsi_samsung_oneplus_dsc_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-panel = <&dsi_samsung_oneplus_dsc_cmd>; + }; + + dsi_samsung_s6e3fc2x01_ed173_cmd_display: qcom,dsi-display@29 { + label = "dsi_samsung_s6e3fc2x01_ed173_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-panel = <&dsi_samsung_s6e3fc2x01_ed173_cmd>; + }; + + dsi_samsung_oneplus_fhd_dsc_cmd_display: qcom,dsi-display@31 { + label = "dsi_samsung_oneplus_fhd_dsc_cmd_display"; + qcom,display-type = "primary"; + qcom,dsi-ctrl-num = <0>; + qcom,dsi-phy-num = <0>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-panel = <&dsi_samsung_oneplus_fhd_dsc_cmd>; + }; + + fingerprint_detect { + compatible = "oneplus,fpdetect"; + fp-gpio-id0 = <&tlmm 90 0>; + fp-gpio-id1 = <&tlmm 21 0>; + }; + + silead_fp { + compatible = "sil,fingerprint"; + interrupt-parent = <&tlmm>; + //avdd-supply = <&pm8150_l17>; + avdd-gpios = <&tlmm 101 0x00>; + irq-gpios = <&tlmm 118 0x00>; + rst-gpios = <&tlmm 131 0x00>; + pinctrl-names = "fp_en_init"; + pinctrl-0 = <&fp_reset_init &fp_irq_init &fp_vdd_init>; + status = "okay"; + }; + + goodix_fp { + compatible = "goodix,fingerprint"; + interrupt-parent = <&tlmm>; + //vdd-3v2-supply = <&pm8998_l22>; + //vdd-voltage = <3200000 3200000>; + //vdd-current = <50000>; + fp-gpio-irq = <&tlmm 118 0x00>; + fp-gpio-reset = <&tlmm 9 0x00>; + fp-gpio-enable = <&tlmm 101 0x00>; + pinctrl-names = "fp_en_init", "fp_dis_init"; + pinctrl-0 = <&fp_vdd_init &fp_irq_init>; + pinctrl-1 = <&fp_vdd_dis_init>; + status = "okay"; + }; + + tri_state_key:tri_state_key { + compatible = "oneplus, tri-state-key"; + status = "okay"; + interrupt-parent = <&tlmm>; + tristate,gpio_key1 = <&tlmm 27 0x00>; + tristate,gpio_key2 = <&tlmm 134 0x00>; + tristate,gpio_key3 = <&tlmm 125 0x00>; + pinctrl-names = + "pmx_tri_state_key_active", + "pmx_tri_state_key_suspend"; + pinctrl-0 = <&tri_state_key_active>; + pinctrl-1 = <&tri_state_key_suspend>; + }; +}; + +&qcomqbt1000{ + /delete-property/ pinctrl-names; + /delete-property/ pinctrl-0; + qfp-int2 = <&tlmm 131 0x00>; + qcom,finger-detect-gpio = <&tlmm 101 0>; +}; + +&sde_dsi { + pinctrl-names = "panel_active", "panel_suspend","default"; + pinctrl-0 = <&sde_dsi_active &sde_te_active &display_panel_avdd_eldo_default>; + pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend &display_panel_avdd_eldo_off>; + /delete-property/ lab-supply; + /delete-property/ ibb-supply; + /delete-property/ vdd-supply; + qcom,dsi-display-list = + <&dsi_samsung_sofef00_m_cmd_display + &dsi_samsung_s6e3fc2x01_cmd_display + &dsi_samsung_s6e3fc2x01_ed173_cmd_display + &dsi_samsung_sofef00_m_video_display + &dsi_samsung_oneplus_dsc_cmd_display + &dsi_samsung_oneplus_fhd_dsc_cmd_display>; +}; + +&tlmm { + display_panel_avdd_eldo_off: display_panel_avdd_eldo_off { + mux { + pins = "gpio130"; + function = "gpio"; + }; + config { + pins = "gpio130"; + drive-strength = <8>; + bias-disable = <0>; + output-low; + }; + }; + + tri_state_key_active: tri_state_key_active { + mux { + pins = "gpio125", "gpio134", "gpio27"; + function = "gpio"; + }; + config { + pins = "gpio125", "gpio134", "gpio27"; + drive-strength = <2>; + bias-disable; + }; + }; + + tri_state_key_suspend: tri_state_key_suspend { + mux { + pins = "gpio125", "gpio134", "gpio27"; + function = "gpio"; + }; + config { + pins = "gpio125", "gpio134", "gpio27"; + drive-strength = <2>; + bias-disable; + }; + }; +}; + +&snd_9360 { + status = "disabled"; +}; +&wcd9360_cdc { + status = "disabled"; +}; +&clock_audio { + status = "disabled"; +}; + +&snd_934x { + qcom,audio-routing = + "AIF4 VI", "MCLK", + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "hifi amp", "LINEOUT1", + "hifi amp", "LINEOUT2", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC3", "MIC BIAS4", + "MIC BIAS4", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS1", + "MIC BIAS1", "ANCLeft Headset Mic", + "AMIC5", "MIC BIAS1", + "MIC BIAS1", "Handset Mic", + "DMIC0", "MIC BIAS1", + "MIC BIAS1", "Digital Mic0", + "DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "DMIC3", "MIC BIAS3", + "MIC BIAS3", "Digital Mic3", + "DMIC4", "MIC BIAS4", + "MIC BIAS4", "Digital Mic4", + "DMIC5", "MIC BIAS4", + "MIC BIAS4", "Digital Mic5", + "SpkrLeft IN", "SPK1 OUT", + "SpkrRight IN", "SPK2 OUT"; + + qcom,wsa-max-devs = <0>; + qcom,msm-mbhc-usbc-audio-supported = <1>; + pinctrl-names = "quat_mi2s_enable","quat_mi2s_disable", + "quat_tdm_enable","quat_tdm_disable"; + pinctrl-0 = <&quat_mi2s_active + &quat_mi2s_sd0_active &quat_mi2s_sd1_active>; + pinctrl-1 = <&quat_mi2s_sleep + &quat_mi2s_sd0_sleep &quat_mi2s_sd1_sleep>; + pinctrl-2 = <&quat_tdm_active + &quat_tdm_din_active &quat_tdm_dout_active>; + pinctrl-3 = <&quat_tdm_sleep + &quat_tdm_din_sleep &quat_tdm_dout_sleep>; +}; + +&wcd934x_cdc { + qcom,cdc-micbias1-mv = <2700>; + qcom,cdc-micbias2-mv = <2700>; + qcom,cdc-micbias4-mv = <2700>; +}; + +&wsa881x_70211{ + status = "disabled"; +}; + +&wsa881x_70212{ + status = "disabled"; +}; + +&wsa881x_70213{ + status = "disabled"; +}; + +&wsa881x_70214{ + status = "disabled"; +}; + +//quentin.lin add 2018/11/07 +&vendor { + motor_pl: motor_pl { + compatible = "oneplus-motor"; + interrupt-parent = <&tlmm>; + interrupts = <163 0x2>; + motor,irq-gpio = <&tlmm 163 0x2008>; + pinctrl-names = "free_fall_input"; + pinctrl-0 = <&free_fall_input>; + structure,id = <0>; + }; +}; + +&tlmm { + free_fall_input: free_fall_input { + mux { + pins = "gpio163"; + function = "gpio"; + }; + config { + pins = "gpio163"; + drive-strength = <2>; + input-enable; + bias-disable; //No Pull + }; + }; + +}; + + +&qupv3_se1_i2c { + status = "ok"; + magnachip@0C { + compatible = "magnachip,mxm1120,up"; + reg = <0x0C>; + vdd-supply = <&pm8150l_l7>; + vio-supply = <&pm8150l_l8>; + magnachip,init-interval = <200>; + interrupt-parent = <&tlmm>; + interrupts = <120 0x2>; + dhall,irq-gpio = <&tlmm 120 0x2008>; + mxm,id = <1>; + }; + magnachip@0D { + compatible = "magnachip,mxm1120,down"; + reg = <0x0D>; + vdd-supply = <&pm8150l_l7>; + vio-supply = <&pm8150l_l8>; + magnachip,init-interval = <200>; + interrupt-parent = <&tlmm>; + interrupts = <121 0x2>; + dhall,irq-gpio = <&tlmm 121 0x2008>; + mxm,id = <2>; + }; +}; + +&qupv3_se4_i2c { + //liuhaituo@MM.Audio add begain +tfa98xx_right: tfa98xx_right@34 { + compatible = "nxp,tfa98xx"; + reg = <0x34>; + reset-gpio = <&tlmm 37 0>; + status = "ok"; + }; + +tfa98xx_left: tfa98xx_left@35 { + compatible = "nxp,tfa98xx"; + reg = <0x35>; + reset-gpio = <&tlmm 37 0>; + status = "ok"; + }; + //liuhaituo@MM.Audio add end +}; + +//liuhaituo@MM.Audio add begain +&dai_mi2s3 { + qcom,msm-mi2s-rx-lines = <2>; + qcom,msm-mi2s-tx-lines = <1>; +}; +//wangdongdong@AudioDrv, add for 4M memory increase of adsp begain +&pil_adsp_mem { + reg = <0x0 0x8be00000 0x0 0x1e00000>; +}; + +&pil_modem_mem { + reg = <0x0 0x8dc00000 0x0 0x9600000>; +}; + +&pil_video_mem { + reg = <0x0 0x97200000 0x0 0x500000>; +}; + +&pil_slpi_mem { + reg = <0x0 0x97700000 0x0 0x1400000>; +}; + +&pil_ipa_fw_mem { + reg = <0x0 0x98b00000 0x0 0x10000>; +}; + +&pil_ipa_gsi_mem { + reg = <0x0 0x98b10000 0x0 0x5000>; +}; + +&pil_gpu_mem { + reg = <0x0 0x98b15000 0x0 0x2000>; +}; + +&pil_spss_mem { + reg = <0x0 0x98c00000 0x0 0x100000>; +}; + +&pil_cdsp_mem { + reg = <0x0 0x98d00000 0x0 0x1400000>; +}; + +//wangdongdong@AudioDrv, add for 4M memory increase of adsp end + +//Because pcie0 wakeup-gpio is same pa-gpio, so disabled it +&pcie0 { + status = "disabled"; +}; +//liuhaituo@MM.Audio add end + +&display_panel_avdd_eldo { + + compatible = "qcom,dsi-display"; + pinctrl-names = "default", "poweroff"; + status = "ok"; + pintctrl-0 = <&display_panel_avdd_eldo_default>; + pintctrl-1 = <&display_panel_avdd_eldo_off>; +}; + +&sde_dsi_active { + mux { + pins = "gpio6"; + function = "gpio"; + }; + + config { + pins = "gpio6"; + drive-strength = <8>; + bias-disable = <0>; + }; +}; +&sde_dsi_suspend { + mux { + pins = "gpio6"; + function = "gpio"; + }; + + config { + pins = "gpio6"; + drive-strength = <2>; + bias-pull-down; + }; +}; + +&qupv3_se17_i2c { + status = "ok"; + sec-s6sy761@48 { + compatible = "sec-s6sy761"; + reg = <0x48>; + project-name = "18821"; + chip-name = "SY761"; + module_id = <7>; + reset-gpio = <&tlmm 54 0x00>; + irq-gpio = <&tlmm 122 0x2008>; + vdd_2v8-supply = <&pm8150_l17>; //set 3.3 by ldo + vdd_2v8_volt = <3008000>; + //enable1v8_gpio = <&tlmm 59 0x00>; //set 1.8v by gpio + touchpanel,display-coords = <1439 3119>; + touchpanel,panel-coords = <1439 3119>; + touchpanel,tx-rx-num = <17 37>; + //edge_limit_support = <1>; + //spurious_fingerprint_support = <1>; + //charger_pump_support = <1>; + black_gesture_support = <1>; + //black_gesture_test_support = <1>; + //game_switch_support = <1>; + face_detect_support = <1>; + lcd_refresh_rate_switch = <1>; + touch_hold_support = <1>; + //lcd_trigger_fp_check = <1>; + module_id_support = <1>; + pinctrl-names = "pin_set_high", "pin_set_low"; + pinctrl-0 = <&tp_irq_active &tp_rst_active &tp_1v8_active>; + pinctrl-1 = <&tp_rst_suspend &tp_1v8_suspend>; + }; +}; + +&qupv3_se17_i2c { + status = "ok"; + synaptics-s3706@20 { + compatible = "synaptics-s3706"; + reg = <0x20>; + project-name = "18857"; + chip-name = "S3706"; + reset-gpio = <&tlmm 54 0x00>; + irq-gpio = <&tlmm 122 0x2008>; + vdd_2v8-supply = <&pm8150_l17>; //set 3.3 by ldo + vdd_2v8_volt = <3008000>; + //enable1v8_gpio = <&tlmm 59 0x00>; //set 1.8v by gpio + touchpanel,display-coords = <1080 2340>; + touchpanel,panel-coords = <1080 2340>; + touchpanel,tx-rx-num = <16 33>; + black_gesture_support = <1>; + face_detect_support = <1>; + touch_hold_support = <1>; + charge_detect_support = <1>; + module_id = <7>; + pinctrl-names = "pin_set_high", "pin_set_low"; + pinctrl-0 = <&tp_irq_active &tp_rst_active &tp_1v8_active>; + pinctrl-1 = <&tp_rst_suspend &tp_1v8_suspend>; + }; +}; + +&qupv3_se17_i2c { + status = "ok"; + st_fts@49 { + compatible = "st,fts"; + reg = <0x49>; + project-name = "18821"; + chip-name = "ST_ALIX"; + module_id = <7>; + reset-gpio = <&tlmm 54 0x00>; + irq-gpio = <&tlmm 122 0x2008>; + vdd_2v8-supply = <&pm8150_l17>; //set 3.3 by ldo + vdd_2v8_volt = <3008000>; + //enable1v8_gpio = <&tlmm 59 0x00>; //set 1.8v by gpio + touchpanel,display-coords = <1439 3119>; + touchpanel,panel-coords = <1439 3119>; + touchpanel,tx-rx-num = <17 37>; + black_gesture_support = <1>; + face_detect_support = <1>; + lcd_refresh_rate_switch = <1>; + touch_hold_support = <1>; + //lcd_trigger_fp_check = <1>; + pinctrl-names = "pin_set_high", "pin_set_low"; + pinctrl-0 = <&tp_irq_active &tp_rst_active &tp_1v8_active>; + pinctrl-1 = <&tp_rst_suspend &tp_1v8_suspend>; + }; +}; + + +/* @bsp, 2018/07/20 Battery & Charging porting STRAT */ +&qupv3_se8_i2c { + qcom,clk-freq-out = <100000>; + status = "ok"; + bq27541-battery@55 { + status = "ok"; + compatible = "ti,bq27541-battery"; + reg = <0x55>; + qcom,modify-soc-smooth; + }; + + oneplus_fastchg@26{ + status = "ok"; + compatible = "microchip,oneplus_fastchg"; + reg = <0x26>; + microchip,mcu-en-gpio = <&tlmm 82 0x00>; + microchip,usb-sw-1-gpio = <&tlmm 94 0x00>; + microchip,usb-sw-2-gpio = <&tlmm 119 0x00>; + microchip,ap-clk = <&tlmm 92 0x00>; + microchip,ap-data = <&tlmm 93 0x00>; + + pinctrl-names = "mux_fastchg_active", + "mux_fastchg_suspend", + "mcu_data_active", + "mcu_data_suspend"; + pinctrl-0 = <&fastchg_active + &usb_sw_active + &ap_clk_active>; + pinctrl-1 = <&usb_sw_suspend + &fastchg_suspend + &ap_clk_suspend>; + pinctrl-2 =<&ap_data_active>; + pinctrl-3 =<&ap_data_suspend>; + op,fw-erase-count = <384>; + op,fw-addr-low = <0x88>; + op,fw-addr-high = <0>; + }; +}; + +&pm8150b_gpios { + gpio1_adc { + gpio1_adc_default: gpio1_adc_default { + pins = "gpio1"; /* GPIO 1 */ + function = "normal"; /* normal */ + bias-pull-up; + bias-high-impedance; /* DISABLE GPIO1 for ADC*/ + }; + }; + + gpio12_adc { + gpio12_adc_default: gpio12_adc_default { + pins = "gpio12"; /* GPIO 12 */ + function = "normal"; /* normal */ + bias-pull-up; + bias-high-impedance; /* DISABLE GPIO12 for ADC*/ + }; + }; + ab_id2 { + ab_id2_default: ab_id2_default { + pins = "gpio2"; + function = "normal"; + input-enable; + bias-disable; + power-source = <0>; + }; + }; +}; + +&pm8150b_vadc { + gpio12_v { + reg = ; + label = "gpio12_v"; + qcom,pre-scaling = <1 1>; + }; + gpio1_v { + reg = ;/* 0x30*/ + label = "gpio1_v"; + qcom,ratiometric; + qcom,hw-settle-time = <800>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm8150b_charger { + qcom,dc-icl-ua = <1200000>; + qcom,fcc-max-ua = <500000>; + qcom,usb-icl-ua = <1800000>; + qcom,fv-max-uv = <4365000>; + /* ibatmax setting for different temp regions */ + ibatmax-little-cold-ma = <350>; + ibatmax-cool-ma = <2000>; + ibatmax-little-cool-ma = <2100>; + ibatmax-pre-normal-ma = <2100>; + ibatmax-normal-ma = <3000>; + ibatmax-warm-ma = <1100>; + ibatmax-little-cool-thr-ma = <1900>; + ibatmax-cool-thr-ma = <1100>; + /* vbatmax setting for different temp regions */ + vbatmax-little-cold-mv = <3975>; + vbatmax-cool-mv = <4390>; + vbatmax-little-cool-mv = <4390>; + vbatmax-pre-normal-mv = <4390>; + vbatmax-normal-mv = <4390>; + vbatmax-warm-mv = <4130>; + little-cool-vbat-thr-mv = <4180>; + cool-vbat-thr-mv = <4180>; + /* vbatdet setting for different temp regions */ + vbatdet-little-cold-mv = <3700>; + vbatdet-cool-mv = <4150>; + vbatdet-little-cool-mv = <4270>; + vbatdet-pre-normal-mv = <4270>; + vbatdet-normal-mv = <4270>; + vbatdet-warm-mv = <3980>; + /* temp region settings */ + cold-bat-decidegc = <20>; + little-cold-bat-decidegc = <0>; + cool-bat-decidegc = <50>; + little-cool-bat-decidegc = <120>; + pre-normal-bat-decidegc = <160>; + warm-bat-decidegc = <450>; + hot-bat-decidegc = <500>; + qcom,otg-cl-ua = <1500000>; + op,sw-iterm-ma = <310>; + op,sw-check-full-enable; + + /*otg low battery current limit*/ + op,otg-icl-ctrl-enable; + otg-low-battery-thr = <15>; + otg-low-bat-icl-thr = <1000000>; + otg-normal-bat-icl-thr = <1500000>; + disable-pd; + /*usb connector hw auto detection*/ + op,usb-check = <&tlmm 91 0x00>; + /* other settings */ + qcom,cutoff-voltage-with-charger = <3250>; + qcom,msm-bus,name = "dash_clk_vote"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <1 731 0 300000000>, + <1 731 0 0>; + /*ffc temp region*/ + ffc-pre-normal-decidegc = <160>; + ffc-normal-decidegc = <350>; + ffc-warm-decidegc = <400>; + ffc-normal-fcc-ma = <650>; + ffc-warm-fcc-ma = <750>; + ffc-normal-cutoff-ma = <550>; + ffc-warm-cutoff-ma = <650>; + ffc-full-vbat-mv = <4430>; + + /* for external ship mode suppot */ + pinctrl-names = "op_ship_mode_default","op_usb_temp_adc_default"; + pinctrl-0 = <&ship_mode_default>; + pinctrl-1= <&gpio1_adc_default>; + + op,stm-ctrl-gpio = <&tlmm 49 0x00>; + /* for usb connector temp protect */ + op,low-voltage-charger; + io-channels = <&pm8150b_vadc ADC_MID_CHG_DIV6>, + <&pm8150b_vadc ADC_USB_IN_V_16>, + <&pm8150b_vadc ADC_USB_IN_I>, + <&pm8150b_vadc ADC_CHG_TEMP>, + <&pm8150b_vadc ADC_AMUX_THM4_PU1>, + <&pm8150b_vadc ADC_VPH_PWR>, + <&pm8150b_vadc ADC_SBUx>; + io-channel-names = "mid_voltage", + "usb_in_voltage", + "usb_in_current", + "chg_temp", + "gpio1_voltage", + "vph_voltage", + "sbux_res"; + op,vbus-ctrl-gpio = <&pm8150l_gpios 8 GPIO_ACTIVE_LOW>; +}; + +&pm8150b_fg { + qcom,fg-force-load-profile; + oem,use_external_fg; + qcom,fg-rsense-sel = <0>; + qcom,fg-sys-term-current = <180>; + qcom,fg-chg-term-current = <165>; +}; + +&tlmm { + pm8150b_charger { + ship_mode_default: ship_mode_default { + mux { + pins = "gpio49"; + function = "gpio"; + }; + + config { + pins = "gpio49"; + drive-strength = <8>; + bias-pull-down; + }; + }; + }; + + oneplus_fastchg { + usb_sw_active: usb_sw_active { + mux { + pins = "gpio94", "gpio119"; + function = "gpio"; + }; + + config { + pins = "gpio94", "gpio119"; + drive-strength = <16>; + bias-pull-down; + }; + }; + + usb_sw_suspend: usb_sw_suspend { + mux { + pins = "gpio94", "gpio119"; + function = "gpio"; + }; + + config { + pins = "gpio94", "gpio119"; + drive-strength = <2>; + bias-disable; + }; + }; + + fastchg_active: fastchg_active { + mux { + pins = "gpio82"; + function = "gpio"; + }; + + config { + pins = "gpio82"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + fastchg_suspend: fastchg_suspend { + mux { + pins = "gpio82"; + function = "gpio"; + }; + + config { + pins = "gpio82"; + drive-strength = <2>; + bias-disable; + }; + }; + + ap_clk_active: ap_clk_active { + mux { + pins = "gpio92"; + function = "gpio"; + }; + + config { + pins = "gpio92"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + ap_clk_suspend: ap_clk_suspend { + mux { + pins = "gpio92"; + function = "gpio"; + }; + + config { + pins = "gpio92"; + drive-strength = <2>; + bias-disable; + }; + }; + + ap_data_active: ap_data_active { + mux { + pins = "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio93"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + ap_data_suspend: ap_data_suspend { + mux { + pins = "gpio93"; + function = "gpio"; + }; + + config { + pins = "gpio93"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + tp_irq_active: tp_irq_active { + mux { + pins = "gpio122"; + function = "gpio"; + }; + config { + pins = "gpio122"; + drive-strength = <8>; + bias-disable; + input-enable; + }; + }; + tp_rst_active: tp_rst_active { + mux { + pins = "gpio54"; + function = "gpio"; + }; + config { + pins = "gpio54"; + drive-strength = <8>; + bias-pull-up; + }; + }; + tp_1v8_active: tp_1v8_active { + mux { + pins = "gpio59"; + function = "gpio"; + }; + config { + pins = "gpio59"; + drive-strength = <8>; + bias-pull-up; + }; + }; + tp_rst_suspend: tp_rst_suspend { + mux { + pins = "gpio54"; + function = "gpio"; + }; + config { + pins = "gpio54"; + drive-strength = <8>; + bias-pull-down; + }; + }; + tp_1v8_suspend: tp_1v8_suspend { + mux { + pins = "gpio59"; + function = "gpio"; + }; + config { + pins = "gpio59"; + drive-strength = <8>; + bias-pull-down; + }; + }; + fp_irq_init: fp_irq_init { + mux { + pins = "gpio118"; + function = "gpio"; + }; + + config { + pins = "gpio118"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + }; + + fp_reset_init: fp_reset_init { + mux { + pins = "gpio131"; + function = "gpio"; + }; + + config { + pins = "gpio131"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + fp_vdd_init: fp_vdd_init { + mux { + pins = "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio101"; + drive-strength = <8>; + bias-pull-up; + output-high; + }; + }; + + fp_vdd_dis_init: fp_vdd_dis_init { + mux { + pins = "gpio101"; + function = "gpio"; + }; + + config { + pins = "gpio101"; + drive-strength = <8>; + bias-pull-down; + output-low; + }; + }; +}; +/* @bsp, 2018/07/20 Battery & Charging porting END */ + +&spmi_bus { + qcom,pm8009@10 { + compatible = "qcom,spmi-pmic"; + reg = <0xa SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm8009_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0x400>; + interrupts = <0xa 0xc0 0 IRQ_TYPE_NONE>, + <0xa 0xc1 0 IRQ_TYPE_NONE>, + <0xa 0xc2 0 IRQ_TYPE_NONE>, + <0xa 0xc3 0 IRQ_TYPE_NONE>; + interrupt-names = "pm8009_gpio1", "pm8009_gpio2", + "pm8009_gpio3", "pm8009_gpio4"; + gpio-controller; + #gpio-cells = <2>; + }; + + pm8009_pon: qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + }; + }; + qcom,pm8009@b { + compatible = "qcom,spmi-pmic"; + reg = <0xb SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + }; + /*power key + vol down long press hard reset*/ + qcom,pm8150@0 { + qcom,power-on@800 { + interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>, + <0x0 0x8 0x1 IRQ_TYPE_NONE>, + <0x0 0x8 0x5 IRQ_TYPE_NONE>; + interrupt-names = "kpdpwr", "resin", "kpdpwr-resin-bark"; + qcom,s3-src = "kpdpwr-and-resin"; + qcom,pon_1 { + qcom,support-reset = <0>; + qcom,s1-timer = <6720>; + qcom,s2-timer = <2000>; + qcom,s2-type = ; + qcom,pull-up; + }; + + qcom,pon_2 { + qcom,support-reset = <0>; + qcom,s1-timer = <6720>; + qcom,s2-timer = <2000>; + qcom,s2-type = ; + qcom,pull-up; + }; + + qcom,pon_3 { + qcom,pon-type = ; + qcom,support-reset = <0>; + qcom,s1-timer = <6720>; + qcom,s2-timer = <2000>; + qcom,s2-type = ; + qcom,pull-up; + }; + }; + }; +}; +&pm8150_gpios { + key_vol_down { + key_vol_down_default: key_vol_down_default { + pins = "gpio7"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <1>; + }; + }; + ab_id1 { + ab_id1_default: ab_id1_default { + pins = "gpio1"; + function = "normal"; + input-enable; + bias-disable; + power-source = <0>; + }; + }; +}; + +&soc { + gpio_keys { + pinctrl-0 = <&key_vol_up_default &key_vol_down_default>; + vol_down { + label = "volume_down"; + gpios = <&pm8150_gpios 7 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; + + bootloader_log { + compatible = "bootloader_log"; + linux,contiguous-region = <&bootloader_log_mem>; + }; +}; + +&reserved_memory { + + bootloader_log_mem: bootloader_log_mem@0x9FFF7000 { + reg = <0 0x9FFF7000 0 0x00009000>; + label = "bootloader_log_mem"; + }; + + param_mem: param_mem@ac200000 { + reg = <0 0xAC200000 0 0x00100000>; + label = "param_mem"; + }; + + //after cdsp_sec_mem + ramoops: ramoops@0xA9800000 { + compatible = "ramoops"; + reg = <0 0xA9800000 0 0x00400000>; + record-size = <0x40000>; //256x1024 + console-size = <0x40000>; + ftrace-size = <0x40000>; + pmsg-size= <0x200000>; + devinfo-size= <0x01000>; + ecc-size= <0x0>; + }; + + mtp_mem: mtp_mem@ac300000 { + reg = <0 0xAC300000 0 0x00B00000>; + label = "mtp_mem"; + }; +}; +&pm8009_gpios { + pm8009_gpios_pinctl: pm8009_gpios_pinctl { + + rf_cable_ant1: rf_cable_ant1{ + pins = "gpio3"; + function = "normal"; + power-source = <1>; + bias-pull-up; + qcom,pull-up-strength = <0>; /* 30uA pull up */ + input-enable; /* digital input */ + }; + rf_cable_ant3: rf_cable_ant3 { + pins = "gpio4"; + function = "normal"; + power-source = <1>; + bias-pull-up; + qcom,pull-up-strength = <0>; /* 30uA pull up */ + input-enable; /* digital input */ + }; + }; +}; + +&soc { + oem_aboard_check:oem_aboard_check { + compatible = "oem,aboard"; + interrupt-parent = <&tlmm>; + oem,aboard-gpio-0 = <&pm8150_gpios 1 0>; + oem,aboard-gpio-1 = <&pm8150b_gpios 2 0>; + pinctrl-names = "oem_aboard_active"; + pinctrl-0 = <&ab_id1_default &ab_id2_default>; + }; + + oem_serial_pinctrl { + compatible = "oem,oem_serial_pinctrl"; + pinctrl-names = "uart_pinctrl_active","uart_pinctrl_deactive"; + pinctrl-0 = <&qupv3_se12_2uart_active>; + pinctrl-1 = <&qupv3_se12_2uart_oem_sleep>; + }; + + oem_rf_cable:oem_rf_cable { + compatible = "oem,rf_cable"; + interrupt-parent = <&tlmm>; + rf,cable-gpio-0 = <&tlmm 36 0>; + rf,cable-gpio-1 = <&pm8009_gpios 4 0>; + rf,cable-support-timer = <0>; + pinctrl-names = "oem_rf_cable_active"; + pinctrl-0 = <&rf_cable_ant0_active &rf_cable_ant1 &rf_cable_ant3 >; + }; +}; +&tlmm { + rf_cable_ant0_active: rf_cable_ant0_active { + mux { + pins = "36"; + function = "gpio"; + }; + config { + pins = "36"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se12_2uart_oem_sleep: qupv3_se12_2uart_oem_sleep { + mux { + pins = "gpio85", "gpio86"; + function = "gpio"; + }; + config { + pins = "gpio85", "gpio86"; + drive-strength = <2>; + bias-pull-down; + }; + }; +}; + +&qupv3_se12_2uart { + compatible = "qcom,msm-geni-console-oem"; +}; + +/* Add for NXP NFCC */ +&qupv3_se9_i2c { + nq@28 { + status = "disabled"; + }; + + pn5xx@28 { + compatible = "nxp,pn544"; + reg = <0x28>; + nxp,pn544-irq = <&tlmm 47 0x00>; + nxp,pn544-ven = <&tlmm 41 0x00>; + nxp,pn544-fw-dwnld = <&tlmm 48 0x00>; + nxp,pn544-clk-gpio = <&tlmm 113 0x00>; + nxp,pn544-ese-pwr = <&tlmm 49 0x00>; + nfc_voltage_s4-supply = <&pm8150_s4>; + interrupt-parent = <&tlmm>; + qcom,clk-src = "BBCLK3"; + interrupts = <47 0>; + interrupt-names = "nfc_irq"; + pinctrl-names = "nfc_active", "nfc_suspend"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; + }; +}; + +/* Add for NXP eSE */ +&qupv3_se0_spi { + status = "ok"; + + ese@0 { + compatible = "nxp,p61"; + reg = <0>; + spi-max-frequency = <8000000>; + }; +}; + +/* add for disabling wil6210 config */ +&wil6210 { + status = "disabled"; +}; + +/*disable smb3190 config */ +&smb1390 { + status = "disabled"; +}; +&smb1390_charger { + status = "disabled"; +}; +&smb1355 { + status = "disabled"; +}; +&smb1355_charger { + status = "disabled"; +}; + +&ipa_smmu_wlan { + qcom,smmu-s1-bypass; +}; + +&icnss { + qcom,smmu-s1-bypass; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi b/arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi index 6af0687eed0cfa3b49655296a79f5d7f7878bee0..7f17daf5375a3f27698b5f76bff7d8b6f5f81718 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi @@ -69,14 +69,14 @@ storage_cd: storage_cd { mux { - pins = "gpio96"; - function = "gpio"; + /*pins = "gpio96"; + function = "gpio";*/ }; config { - pins = "gpio96"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ + /*pins = "gpio96";*/ + /*bias-pull-up;*/ /* pull up */ + /*drive-strength = <2>;*/ /* 2 MA */ }; }; @@ -448,14 +448,14 @@ wil6210_refclk3_en_pin: wil6210_refclk3_en_pin { mux { - pins = "gpio87"; - function = "gpio"; + /*pins = "gpio87"; + function = "gpio";*/ }; config { - pins = "gpio87"; - bias-pull-down; /* PULL DOWN */ - drive-strength = <2>; /* 2 MA */ + /*pins = "gpio87";*/ + /*bias-pull-down;*/ /* PULL DOWN */ + /*drive-strength = <2>;*/ /* 2 MA */ }; }; @@ -985,6 +985,18 @@ bias-pull-up; }; }; + qupv3_se8_i2c_reset: qupv3_se8_i2c_reset { + mux { + pins = "gpio88", "gpio89"; + function = "gpio"; + }; + + config { + pins = "gpio88", "gpio89"; + drive-strength = <2>; + bias-pull-down; + }; + }; }; qupv3_se8_spi_pins: qupv3_se8_spi_pins { @@ -1624,7 +1636,8 @@ config { pins = "gpio55", "gpio56"; drive-strength = <2>; - bias-pull-up; + bias-disable; + input-enable; }; }; }; @@ -4211,14 +4224,14 @@ }; }; - usb2_id_det_default: usb2_id_det_default { + /*usb2_id_det_default: usb2_id_det_default { config { pins = "gpio101"; function = "gpio"; input-enable; bias-pull-up; }; - }; + };GPIO 101 for fingerprint VDD enable */ emac { emac_mdc: emac_mdc { diff --git a/arch/arm64/boot/dts/qcom/sm8150-pmic-overlay.dtsi b/arch/arm64/boot/dts/qcom/sm8150-pmic-overlay.dtsi index 43cebaaba21952cb42591c5f6326cb700b2058e3..db5573be3eb0b5e605153270013132a24ca1f851 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-pmic-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-pmic-overlay.dtsi @@ -99,12 +99,37 @@ power-source = <0>; }; }; + + haptics_boost { + haptics_boost_default: haptics_boost_default { + pins = "gpio5"; + function = "normal"; + output-enable; + input-disable; + bias-disable; + qcom,drive-strength = <3>; /* high */ + power-source = <0>; /* VPH_PWR */ + }; + }; }; &usb0 { extcon = <&pm8150b_pdphy>, <&eud>; }; +&vendor { + haptics_boost_vreg: haptics_boost_vreg { + compatible = "regulator-fixed"; + regulator-name = "haptics_boost"; + gpio = <&pm8150b_gpios 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-enable-ramp-delay = <300>; + pinctrl-names = "default"; + pinctrl-0 = <&haptics_boost_default>; + status = "disabled"; + }; +}; + &usb_qmp_dp_phy { extcon = <&pm8150b_pdphy>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150-qrd.dtsi b/arch/arm64/boot/dts/qcom/sm8150-qrd.dtsi index 31900f80fd19509812b4632616d377c414576ff3..927dd6863154598d159c9053f91b2b975f6b4786 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-qrd.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-qrd.dtsi @@ -225,6 +225,7 @@ compatible = "qcom,ufs-phy-qmp-v4"; vdda-phy-supply = <&pm8150_l5>; + vdda-phy-always-on; vdda-pll-supply = <&pm8150l_l3>; vdda-phy-max-microamp = <90200>; vdda-pll-max-microamp = <19000>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-qupv3.dtsi b/arch/arm64/boot/dts/qcom/sm8150-qupv3.dtsi index 4ef1873e2aefc7c34c1858ede4f863241eebff97..245be7cd541b43094faab7766e8570894a8eb499 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-qupv3.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-qupv3.dtsi @@ -446,9 +446,10 @@ dmas = <&gpi_dma1 0 0 3 64 0>, <&gpi_dma1 1 0 3 64 0>; dma-names = "tx", "rx"; - pinctrl-names = "default", "sleep"; + pinctrl-names = "default", "sleep","reset"; pinctrl-0 = <&qupv3_se8_i2c_active>; pinctrl-1 = <&qupv3_se8_i2c_sleep>; + pinctrl-2 = <&qupv3_se8_i2c_reset>; qcom,wrapper-core = <&qupv3_1>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150-regulator.dtsi b/arch/arm64/boot/dts/qcom/sm8150-regulator.dtsi index 40a4ab37f02a850e4d4fb08cf1d7d1eff3147da5..e12333e4bc0979d1f71336fbf000f3eaea19cf17 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-regulator.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-regulator.dtsi @@ -909,13 +909,13 @@ }; rpmh-regulator-ldof2 { - compatible = "qcom,rpmh-xob-regulator"; + compatible = "qcom,rpmh-vrm-regulator"; mboxes = <&apps_rsc 0>; qcom,resource-name = "ldof2"; L2F: pm8009_l2: regulator-pm8009-l2 { regulator-name = "pm8009_l2"; qcom,set = ; - regulator-min-microvolt = <1200000>; + regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1200000>; }; }; @@ -944,6 +944,54 @@ }; }; + rpmh-regulator-ldof1 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldof1"; + L1F: pm8009_l1: regulator-pm8009-l1 { + regulator-name = "pm8009_l1"; + qcom,set = ; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + }; + + rpmh-regulator-ldof3 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldof3"; + L3F: pm8009_l3: regulator-pm8009-l3 { + regulator-name = "pm8009_l3"; + qcom,set = ; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + }; + + rpmh-regulator-ldof4 { + compatible = "qcom,rpmh-vrm-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldof4"; + L4F: pm8009_l4: regulator-pm8009-l4 { + regulator-name = "pm8009_l4"; + qcom,set = ; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + }; + + rpmh-regulator-ldof7 { + compatible = "qcom,rpmh-xob-regulator"; + mboxes = <&apps_rsc 0>; + qcom,resource-name = "ldof7"; + L7F: pm8009_l7: regulator-pm8009-l7 { + regulator-name = "pm8009_l7"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + refgen: refgen-regulator@88e7000 { compatible = "qcom,refgen-regulator"; reg = <0x88e7000 0x60>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi old mode 100644 new mode 100755 index fb477aa76987436e68a4556e212ebcb6970283ec..df86e39498e6cfaa06720ce068f480cae475419d --- a/arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sde-display.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -33,7 +33,12 @@ #include "dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi" #include "dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi" #include - +#include "dsi-panel-samsung_sofef00_m_cmd.dtsi" +#include "dsi-panel-samsung_s6e3fc2x01.dtsi" +#include "dsi-panel-samsung-sofef00_m-fhd-video.dtsi" +#include "dsi-panel-samsung_oneplus_dsc.dtsi" +#include "dsi-panel-samsung_s6e3fc2x01_ed173.dtsi" +#include "dsi_samsung_oneplus_fhd_dsc.dtsi" &tlmm { display_panel_avdd_eldo_default: display_panel_avdd_eldo_default { mux { @@ -57,13 +62,13 @@ qcom,panel-supply-entry@0 { reg = <0>; qcom,supply-name = "vddio"; - qcom,supply-min-voltage = <1800000>; - qcom,supply-max-voltage = <1800000>; + qcom,supply-min-voltage = <1850000>; + qcom,supply-max-voltage = <1850000>; qcom,supply-enable-load = <62000>; qcom,supply-disable-load = <80>; - qcom,supply-post-on-sleep = <20>; + qcom,supply-post-on-sleep = <6>; }; - + /* qcom,panel-supply-entry@1 { reg = <1>; qcom,supply-name = "lab"; @@ -82,6 +87,7 @@ qcom,supply-disable-load = <100>; qcom,supply-post-on-sleep = <20>; }; + */ }; dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { @@ -143,7 +149,7 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sharp_4k_dsc_video>; }; @@ -154,7 +160,7 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sharp_4k_dsc_cmd>; }; @@ -165,7 +171,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sharp_1080_cmd>; }; @@ -176,7 +182,7 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_dual_sharp_1080_120hz_cmd>; }; @@ -187,7 +193,7 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_dual_nt35597_truly_video>; }; @@ -198,7 +204,7 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_dual_nt35597_truly_cmd>; }; @@ -209,7 +215,7 @@ qcom,dsi-ctrl-num = <1>; qcom,dsi-phy-num = <1>; - qcom,dsi-select-clocks = "src_byte_clk1", "src_pixel_clk1"; + qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,dsi-panel = <&dsi_nt35597_truly_dsc_cmd>; }; @@ -220,7 +226,7 @@ qcom,dsi-ctrl-num = <1>; qcom,dsi-phy-num = <1>; - qcom,dsi-select-clocks = "src_byte_clk1", "src_pixel_clk1"; + qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,dsi-panel = <&dsi_nt35597_truly_dsc_video>; }; @@ -231,7 +237,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sim_vid>; }; @@ -242,7 +248,7 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_dual_sim_vid>; }; @@ -253,7 +259,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sim_cmd>; }; @@ -264,7 +270,7 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_dual_sim_cmd>; }; @@ -275,7 +281,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sim_dsc_375_cmd>; }; @@ -286,7 +292,7 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_dual_sim_dsc_375_cmd>; }; @@ -297,7 +303,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sw43404_amoled_cmd>; }; @@ -308,7 +314,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_cmd>; @@ -320,7 +326,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_video>; }; @@ -331,7 +337,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sw43404_amoled_video>; }; @@ -342,7 +348,7 @@ qcom,dsi-ctrl-num = <0>; qcom,dsi-phy-num = <0>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_sw43404_amoled_fhd_plus_cmd>; }; @@ -353,7 +359,7 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; - qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0"; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,dsi-panel = <&dsi_dual_nt36850_truly_cmd>; }; @@ -364,7 +370,7 @@ qcom,dsi-ctrl-num = <1>; qcom,dsi-phy-num = <1>; - qcom,dsi-select-clocks = "src_byte_clk1", "src_pixel_clk1"; + qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_cmd>; @@ -376,7 +382,7 @@ qcom,dsi-ctrl-num = <1>; qcom,dsi-phy-num = <1>; - qcom,dsi-select-clocks = "src_byte_clk1", "src_pixel_clk1"; + qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_video>; }; @@ -388,7 +394,7 @@ qcom,dsi-ctrl-num = <1>; qcom,dsi-phy-num = <1>; - qcom,dsi-select-clocks = "src_byte_clk1", "src_pixel_clk1"; + qcom,dsi-select-clocks = "mux_byte_clk1", "mux_pixel_clk1"; qcom,dsi-panel = <&dsi_sim_sec_hd_cmd>; }; @@ -404,8 +410,8 @@ <&mdss_dsi0_pll PCLK_MUX_0_CLK>, <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, <&mdss_dsi1_pll PCLK_MUX_1_CLK>; - clock-names = "src_byte_clk0", "src_pixel_clk0", - "src_byte_clk1", "src_pixel_clk1"; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi_active &sde_te_active>; @@ -413,6 +419,7 @@ qcom,platform-te-gpio = <&tlmm 8 0>; qcom,panel-te-source = <0>; + enable1v8_gpio = <&tlmm 119 0x00>; vddio-supply = <&pm8150_l14>; lab-supply = <&lcdb_ldo_vreg>; @@ -453,8 +460,8 @@ <&mdss_dsi0_pll PCLK_MUX_0_CLK>, <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, <&mdss_dsi1_pll PCLK_MUX_1_CLK>; - clock-names = "src_byte_clk0", "src_pixel_clk0", - "src_byte_clk1", "src_pixel_clk1"; + clock-names = "mux_byte_clk0", "mux_pixel_clk0", + "mux_byte_clk1", "mux_pixel_clk1"; pinctrl-names = "panel_active", "panel_suspend"; pinctrl-0 = <&sde_dsi1_active &sde_te1_active>; @@ -507,8 +514,7 @@ /* PHY TIMINGS REVISION T */ &dsi_dual_nt35597_truly_video { - qcom,mdss-dsi-min-refresh-rate = <53>; - qcom,mdss-dsi-max-refresh-rate = <60>; + qcom,dsi-supported-dfps-list = <60 55 53>; qcom,mdss-dsi-pan-enable-dynamic-fps; qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,esd-check-enabled; diff --git a/arch/arm64/boot/dts/qcom/sm8150-sde.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sde.dtsi index eff9ec22d83bc3d0068313addf89564c4d276c05..5d9633b3a66a1653d92667303e48ac49e826d065 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sde.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sde.dtsi @@ -641,7 +641,7 @@ qcom,max-pclk-frequency-khz = <675000>; - qcom,mst-enable; + //qcom,mst-enable; qcom,dsc-feature-enable; qcom,fec-feature-enable; qcom,max-dp-dsc-blks = <2>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-sdx50m-mtp-overlay.dts b/arch/arm64/boot/dts/qcom/sm8150-sdx50m-mtp-overlay.dts index fb74f162754f93c1e76e1f3e6e4a7e28932f2b07..b2f06e81cdd192e1f76541e806285247673d920d 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sdx50m-mtp-overlay.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-sdx50m-mtp-overlay.dts @@ -24,8 +24,15 @@ #include "sm8150-sdx50m.dtsi" #include "sm8150-mtp-audio-overlay.dtsi" +#include "sm8150-oem.dtsi" +#include "sm8150-oem-camera-v2.dtsi" +#include "guacamole.dtsi" +#include "guacamole_t0.dtsi" + + / { - model = "SDX50M MTP"; + model = "SDX50M MTP ref"; compatible = "qcom,sm8150-mtp", "qcom,sm8150", "qcom,mtp"; qcom,board-id = <0x01010008 0x1>; + }; diff --git a/arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi index 86fcb7b67c6782c935f76928b960938d6c7097c8..a6621fb8b8e754e5e7c4d8e6918d40fd26959862 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sdx50m.dtsi @@ -254,6 +254,7 @@ qcom,instance-id = <100>; qcom,qmi-sensor-names = "pa", "pa_1", + "pa_2", "qfe_pa0", "qfe_wtr0", "modem_tsens", @@ -325,7 +326,7 @@ }; }; - modem1-qfe-pa-usr { + modem1-pa2-usr { polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; @@ -343,7 +344,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor 103>; + thermal-sensors = <&qmi_sensor 104>; trips { active-config0 { temperature = <125000>; @@ -357,7 +358,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor 104>; + thermal-sensors = <&qmi_sensor 105>; trips { active-config0 { temperature = <125000>; @@ -371,7 +372,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor 105>; + thermal-sensors = <&qmi_sensor 106>; trips { active-config0 { temperature = <125000>; @@ -385,7 +386,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor 106>; + thermal-sensors = <&qmi_sensor 107>; trips { active-config0 { temperature = <125000>; @@ -399,7 +400,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor 107>; + thermal-sensors = <&qmi_sensor 108>; trips { active-config0 { temperature = <125000>; @@ -413,7 +414,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor 108>; + thermal-sensors = <&qmi_sensor 109>; trips { active-config0 { temperature = <125000>; @@ -427,7 +428,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor 109>; + thermal-sensors = <&qmi_sensor 110>; trips { active-config0 { temperature = <125000>; @@ -441,7 +442,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor 110>; + thermal-sensors = <&qmi_sensor 111>; trips { active-config0 { temperature = <125000>; @@ -455,7 +456,7 @@ polling-delay-passive = <0>; polling-delay = <0>; thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor 111>; + thermal-sensors = <&qmi_sensor 112>; trips { active-config0 { temperature = <125000>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-thermal-overlay.dtsi b/arch/arm64/boot/dts/qcom/sm8150-thermal-overlay.dtsi index 9c8b8ea200f73f3311674729b77dbee6b244012c..87e75cf559e7e8a66071513f59a39210e615d65e 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-thermal-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-thermal-overlay.dtsi @@ -127,29 +127,22 @@ soc { cooling-maps { - soc_cpu4 { - trip = <&soc_trip>; + soctrip_cpu4 { + trip = <&soc_trip2>; cooling-device = - <&CPU4 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + <&CPU4 6 6>; }; - soc_cpu5 { - trip = <&soc_trip>; + soctrip_cpu7 { + trip = <&soc_trip2>; cooling-device = - <&CPU5 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + <&CPU7 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; }; - soc_cpu6 { + soctrip_cpu6 { trip = <&soc_trip>; cooling-device = <&CPU6 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; - }; - soc_cpu7 { - trip = <&soc_trip>; - cooling-device = - <&CPU7 THERMAL_MAX_LIMIT - THERMAL_MAX_LIMIT>; + THERMAL_MAX_LIMIT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150-thermal.dtsi b/arch/arm64/boot/dts/qcom/sm8150-thermal.dtsi index 99a9d461a02f3a9058d0c393ac0f07b137f16a4a..3f40e46a188f8eaaf968b09bba5c54c94eb910af 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-thermal.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-thermal.dtsi @@ -742,8 +742,8 @@ }; gpuss-max-step { - polling-delay-passive = <10>; - polling-delay = <100>; + polling-delay-passive = <0>; + polling-delay = <0>; thermal-governor = "step_wise"; trips { gpu_trip0: gpu-trip0 { diff --git a/arch/arm64/boot/dts/qcom/sm8150-usb.dtsi b/arch/arm64/boot/dts/qcom/sm8150-usb.dtsi index ec42091e8d01f7d2e41f86c4bc0a1c49229161e6..38fba614ff22cc97c144715e6b541c0b8583ade3 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-usb.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-usb.dtsi @@ -61,6 +61,7 @@ 0x144 /* GSI_RING_BASE_ADDR_H */ 0x1a4>; /* GSI_IF_STS */ qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + qcom,pm-qos-latency = <44>; qcom,msm-bus,name = "usb0"; qcom,msm-bus,num-cases = <4>; @@ -98,10 +99,11 @@ snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,ssp-u3-u0-quirk; - snps,usb3-u1u2-disable; + //snps,usb3-u1u2-disable; usb-core-id = <0>; tx-fifo-resize; - maximum-speed = "super-speed-plus"; + maximum-speed = "super-speed"; + //maximum-speed = "super-speed-plus"; dr_mode = "otg"; }; @@ -386,6 +388,7 @@ 0x1a4>; /* GSI_IF_STS */ qcom,dwc-usb3-msm-tx-fifo-size = <27696>; qcom,charging-disabled; + qcom,pm-qos-latency = <44>; qcom,msm-bus,name = "usb1"; qcom,msm-bus,num-cases = <3>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-v2-camera.dtsi b/arch/arm64/boot/dts/qcom/sm8150-v2-camera.dtsi index e92fd1b7c180e826a9c75c491f98e4599d962c45..6cdfb798bbfcc13a7db94a87a7eb4d72fc6567c7 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-v2-camera.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-v2-camera.dtsi @@ -235,10 +235,10 @@ }; iova-mem-region-shared { - /* Shared region is 100MB long */ + /* Shared region is 150MB long */ iova-region-name = "shared"; iova-region-start = <0x7400000>; - iova-region-len = <0x6400000>; + iova-region-len = <0x9600000>; iova-region-id = <0x1>; status = "ok"; }; @@ -246,7 +246,7 @@ iova-mem-region-secondary-heap { /* Secondary heap region is 1MB long */ iova-region-name = "secheap"; - iova-region-start = <0xd800000>; + iova-region-start = <0x10A00000>; iova-region-len = <0x100000>; iova-region-id = <0x4>; status = "ok"; @@ -255,8 +255,8 @@ iova-mem-region-io { /* IO region is approximately 3.3 GB */ iova-region-name = "io"; - iova-region-start = <0xda00000>; - iova-region-len = <0xd2500000>; + iova-region-start = <0x10C00000>; + iova-region-len = <0xCF300000>; iova-region-id = <0x3>; status = "ok"; }; @@ -264,7 +264,7 @@ iova-mem-qdss-region { /* QDSS region is appropriate 1MB */ iova-region-name = "qdss"; - iova-region-start = <0xd900000>; + iova-region-start = <0x10B00000>; iova-region-len = <0x100000>; iova-region-id = <0x5>; qdss-phy-addr = <0x16790000>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-v2.dtsi b/arch/arm64/boot/dts/qcom/sm8150-v2.dtsi index 5a779486d300f9f226487f54b19f3bc012e35752..c4e65ca39f1e80ef89b76ec3475524c94a358035 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-v2.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-v2.dtsi @@ -1040,6 +1040,12 @@ USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0 USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00 0 USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00 0 + /*op do optimize A/B side 0x1214/0x1614:0x06 0x1308/0x1708:0x0c + *0x120C/0x160C:0x06 + */ + USB3_DP_QSERDES_TXA_TX_DRV_LVL 0x06 0 + USB3_DP_QSERDES_TXA_PRE_EMPH 0x0c 0 + USB3_DP_QSERDES_TXA_TX_EMP_POST1_LVL 0x06 0 USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x16 0 USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x05 0 USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x20 0 @@ -1083,6 +1089,12 @@ USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0 USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00 0 USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00 0 + /*op do optimize A/B side 0x1214/0x1614:0x06 0x1308/0x1708:0x0c + *0x120C/0x160C:0x06 + */ + USB3_DP_QSERDES_TXB_TX_DRV_LVL 0x06 0 + USB3_DP_QSERDES_TXB_PRE_EMPH 0x0c 0 + USB3_DP_QSERDES_TXB_TX_EMP_POST1_LVL 0x06 0 USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x16 0 USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x05 0 USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x01 0 diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 742c82c483d80e77a936def74cce734455b5d5f1..8c087a766bb4e4b248abbf0b068fdaf6a72e6356 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -576,25 +576,25 @@ compatible = "android,firmware"; vbmeta { compatible = "android,vbmeta"; - parts = "vbmeta,boot,system,vendor,dtbo,vm-linux"; + parts = "vbmeta,boot,system,vendor,dtbo"; }; fstab { compatible = "android,fstab"; vendor { compatible = "android,vendor"; - dev = "/dev/block/platform/soc/8804000.sdhci/by-name/vendor"; + dev = "/dev/block/platform/soc/1d84000.sdhci/by-name/vendor"; type = "ext4"; mnt_flags = "ro,barrier=1,discard"; fsmgr_flags = "wait,slotselect,avb"; status = "ok"; }; - vm-linux { - compatible = "android,vm-linux"; - dev = "/dev/block/platform/soc/8804000.sdhci/by-name/vm-linux"; - type = "emmc"; + odm { + compatible = "android,odm"; + dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/odm"; + type = "ext4"; mnt_flags = "ro"; fsmgr_flags = "wait,slotselect"; - status = ""; + status = "ok"; }; }; }; @@ -2990,7 +2990,7 @@ qcom_seecom: qseecom@87900000 { compatible = "qcom,qseecom"; - reg = <0x87900000 0x2200000>; + reg = <0x87900000 0x3E00000>; /* enlarge TA memory size from 34M to 62M on 2018/11/22 */ reg-names = "secapp-region"; memory-region = <&qseecom_mem>; qcom,hlos-num-ce-hw-instances = <1>; @@ -3007,7 +3007,7 @@ qcom_smcinvoke: smcinvoke@87900000 { compatible = "qcom,smcinvoke"; - reg = <0x87900000 0x2200000>; + reg = <0x87900000 0x3E00000>; /* enlarge TA memory size from 34M to 62M on 2018/11/22 */ reg-names = "secapp-region"; }; diff --git a/arch/arm64/configs/vendor/sm8150-perf_defconfig b/arch/arm64/configs/vendor/sm8150-perf_defconfig index 485894d2cafb744c7e88cfa86fde8b01e27fd28a..0922e4bf461d000a2640ab71839f6497ab9754ce 100644 --- a/arch/arm64/configs/vendor/sm8150-perf_defconfig +++ b/arch/arm64/configs/vendor/sm8150-perf_defconfig @@ -1,4 +1,4 @@ -CONFIG_HOTPLUG_SIZE_BITS=29 +# CONFIG_HOTPLUG_SIZE_BITS is not set CONFIG_LOCALVERSION="-perf" # CONFIG_LOCALVERSION_AUTO is not set # CONFIG_FHANDLE is not set @@ -65,10 +65,10 @@ CONFIG_SCHED_MC=y CONFIG_NR_CPUS=8 CONFIG_PREEMPT=y CONFIG_HZ_100=y -CONFIG_MEMORY_HOTPLUG=y -CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE=y -CONFIG_MEMORY_HOTPLUG_MOVABLE_NODE=y -CONFIG_MEMORY_HOTREMOVE=y +# CONFIG_MEMORY_HOTPLUG is not set +# CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE is not set +# CONFIG_MEMORY_HOTPLUG_MOVABLE_NODE is not set +# CONFIG_MEMORY_HOTREMOVE is not set CONFIG_CMA=y CONFIG_ZSMALLOC=y CONFIG_BALANCE_ANON_FILE_RECLAIM=y @@ -94,6 +94,7 @@ CONFIG_PM_WAKELOCKS_LIMIT=0 CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_GOV_ONDEMAND=y @@ -253,7 +254,9 @@ CONFIG_CFG80211_CERTIFICATION_ONUS=y CONFIG_CFG80211_REG_CELLULAR_HINTS=y CONFIG_CFG80211_INTERNAL_REGDB=y CONFIG_RFKILL=y -CONFIG_NFC_NQ=y +# CONFIG_NFC_NQ=y +CONFIG_NFC_PN5XX=y +CONFIG_NFC_PN80T=y CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y @@ -261,7 +264,7 @@ CONFIG_MHI_BUS=y CONFIG_MHI_QCOM=y CONFIG_MHI_NETDEV=y CONFIG_MHI_UCI=y -CONFIG_ZRAM=y +# CONFIG_ZRAM is not set CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 @@ -293,6 +296,7 @@ CONFIG_TUN=y CONFIG_SKY2=y CONFIG_RMNET=y CONFIG_SMSC911X=y +CONFIG_SENSOR_HALL_MXM1120=y CONFIG_PPP=y CONFIG_PPP_BSDCOMP=y CONFIG_PPP_DEFLATE=y @@ -312,11 +316,32 @@ CONFIG_CLD_LL_CORE=y CONFIG_CNSS_GENL=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y +CONFIG_TRI_STATE_KEY=y +CONFIG_HALL_TRI_STATE_KEY=y # CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_JOYSTICK=y CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ST=y +CONFIG_INPUT_FINGERPRINT=y +CONFIG_FINGERPRINT_DETECT=y +#CONFIG_FINGERPRINT_FPC=y +CONFIG_FINGERPRINT_GOODIX=y +CONFIG_FINGERPRINT_SILEAD=y +CONFIG_TOUCHPANEL_ONEPLUS=y +CONFIG_TOUCHPANEL_SAMSUNG=y +CONFIG_TOUCHPANEL_SAMSUNG_S6SY761=y +CONFIG_TOUCHPANEL_SYNAPTICS=y +CONFIG_TOUCHPANEL_SYNAPTICS_S3706=y +CONFIG_TOUCHPANEL_ST=y +CONFIG_TOUCHPANEL_ST_FST1BA90A=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_S3320_I2C_RMI=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_EXTRA_SYSFS=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_TEST_REPORTING=y +#CONFIG_TOUCHSCREEN_ST=y CONFIG_INPUT_MISC=y -CONFIG_INPUT_HBTP_INPUT=y +# CONFIG_INPUT_HBTP_INPUT is not set CONFIG_INPUT_QPNP_POWER_ON=y CONFIG_INPUT_QTI_HAPTICS=y CONFIG_INPUT_UINPUT=y @@ -325,6 +350,7 @@ CONFIG_INPUT_UINPUT=y # CONFIG_LEGACY_PTYS is not set # CONFIG_DEVMEM is not set CONFIG_SERIAL_MSM_GENI=y +CONFIG_SERIAL_MSM_GENI_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_MSM_LEGACY=y # CONFIG_DEVPORT is not set @@ -355,6 +381,11 @@ CONFIG_QPNP_FG_GEN4=y CONFIG_SMB1355_SLAVE_CHARGER=y CONFIG_QPNP_SMB5=y CONFIG_QPNP_QNOVO5=y +CONFIG_FG_BQ27541=y +CONFIG_ONEPLUS_FASTCHG=y +CONFIG_JOYSTICK_XPAD=y +CONFIG_HID_SONY=y +CONFIG_SONY_FF=y CONFIG_SMB1390_CHARGE_PUMP=y CONFIG_THERMAL=y CONFIG_THERMAL_WRITABLE_TRIPS=y @@ -535,8 +566,8 @@ CONFIG_RPMSG_CHAR=y CONFIG_RPMSG_QCOM_GLINK_SMEM=y CONFIG_RPMSG_QCOM_GLINK_SPSS=y CONFIG_RPMSG_QCOM_GLINK_SPI=y -CONFIG_QCOM_MEM_OFFLINE=y -CONFIG_OVERRIDE_MEMORY_LIMIT=y +# CONFIG_QCOM_MEM_OFFLINE is not set +# CONFIG_OVERRIDE_MEMORY_LIMIT is not set CONFIG_QCOM_CPUSS_DUMP=y CONFIG_QCOM_RUN_QUEUE_STATS=y CONFIG_QCOM_LLCC=y @@ -629,12 +660,17 @@ CONFIG_EXT4_FS_SECURITY=y CONFIG_EXT4_ENCRYPTION=y CONFIG_EXT4_FS_ENCRYPTION=y CONFIG_EXT4_FS_ICE_ENCRYPTION=y +CONFIG_F2FS_FS=y +CONFIG_F2FS_FS_SECURITY=y +CONFIG_F2FS_FS_ENCRYPTION=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y CONFIG_QFMT_V2=y CONFIG_FUSE_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y +CONFIG_EXFAT_FS=y +CONFIG_NTFS_FS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_ECRYPT_FS=y CONFIG_ECRYPT_FS_MESSAGING=y @@ -688,3 +724,33 @@ CONFIG_CRYPTO_AES_ARM64_CE_CCM=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y CONFIG_STACK_HASH_ORDER_SHIFT=12 +CONFIG_PSTORE=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_RAM=y +CONFIG_PSTORE_DEVICE_INFO=y +CONFIG_PSTORE_PMSG=y +CONFIG_BOOTLOADER_LOG=y +CONFIG_PROJECT_INFO=y +CONFIG_OEM_BOOT_MODE=y +CONFIG_AW8697_HAPTIC=y +CONFIG_INPUT_KEYCHORD=y +CONFIG_DIGITAL_HALL_M1120=y +CONFIG_STEP_MOTOR=y +CONFIG_RF_CABLE_DETECT=y +CONFIG_NET_CLS_CGROUP=y +CONFIG_ADJ_CHAIN=y +CONFIG_DEFRAG_HELPER=y +CONFIG_FSC=y +# zhongbin, 2019/1/4, add for memory plus project +CONFIG_MEMPLUS=y +CONFIG_SWAP=y +CONFIG_ZRAM=y +CONFIG_ZRAM_LZ4_COMPRESS=y +CONFIG_LZ4_DECOMPRESS=y +CONFIG_LZ4_COMPRESS=y +CONFIG_CRYPTO_LZ4=y +# end +CONFIG_OPCHAIN=y +CONFIG_SMART_BOOST=y +# dylanchang,2019/4/1, add for kernel log reserve +CONFIG_WB_KERNEL_LOG=y diff --git a/arch/arm64/configs/vendor/sm8150_defconfig b/arch/arm64/configs/vendor/sm8150_defconfig index fe0ff6c35645ccf8965fe6dd49455e39c8a543ea..33aa07d5c9e561dbbc4df830e3ff5151f7ed16a1 100644 --- a/arch/arm64/configs/vendor/sm8150_defconfig +++ b/arch/arm64/configs/vendor/sm8150_defconfig @@ -1,4 +1,4 @@ -CONFIG_HOTPLUG_SIZE_BITS=29 +# CONFIG_HOTPLUG_SIZE_BITS is not set # CONFIG_LOCALVERSION_AUTO is not set # CONFIG_FHANDLE is not set CONFIG_AUDIT=y @@ -69,10 +69,10 @@ CONFIG_SCHED_MC=y CONFIG_NR_CPUS=8 CONFIG_PREEMPT=y CONFIG_HZ_100=y -CONFIG_MEMORY_HOTPLUG=y -CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE=y -CONFIG_MEMORY_HOTPLUG_MOVABLE_NODE=y -CONFIG_MEMORY_HOTREMOVE=y +# CONFIG_MEMORY_HOTPLUG is not set +# CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE is not set +# CONFIG_MEMORY_HOTPLUG_MOVABLE_NODE is not set +# CONFIG_MEMORY_HOTREMOVE is not set CONFIG_CLEANCACHE=y CONFIG_CMA=y CONFIG_CMA_DEBUGFS=y @@ -101,6 +101,7 @@ CONFIG_PM_DEBUG=y CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_GOV_ONDEMAND=y @@ -263,7 +264,9 @@ CONFIG_CFG80211_REG_CELLULAR_HINTS=y CONFIG_CFG80211_INTERNAL_REGDB=y # CONFIG_CFG80211_CRDA_SUPPORT is not set CONFIG_RFKILL=y -CONFIG_NFC_NQ=y +# CONFIG_NFC_NQ=y +CONFIG_NFC_PN5XX=y +CONFIG_NFC_PN80T=y CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y @@ -272,7 +275,7 @@ CONFIG_MHI_DEBUG=y CONFIG_MHI_QCOM=y CONFIG_MHI_NETDEV=y CONFIG_MHI_UCI=y -CONFIG_ZRAM=y +# CONFIG_ZRAM is not set CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 @@ -304,6 +307,7 @@ CONFIG_BONDING=y CONFIG_DUMMY=y CONFIG_TUN=y CONFIG_RMNET=y +CONFIG_SENSOR_HALL_MXM1120=y CONFIG_PPP=y CONFIG_PPP_BSDCOMP=y CONFIG_PPP_DEFLATE=y @@ -323,12 +327,32 @@ CONFIG_CLD_LL_CORE=y CONFIG_CNSS_GENL=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y +CONFIG_TRI_STATE_KEY=y +CONFIG_HALL_TRI_STATE_KEY=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_JOYSTICK=y CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ST=y +CONFIG_INPUT_FINGERPRINT=y +CONFIG_FINGERPRINT_DETECT=y +#CONFIG_FINGERPRINT_FPC=y +CONFIG_FINGERPRINT_GOODIX=y +CONFIG_FINGERPRINT_SILEAD=y +CONFIG_TOUCHPANEL_ONEPLUS=y +CONFIG_TOUCHPANEL_SAMSUNG=y +CONFIG_TOUCHPANEL_SAMSUNG_S6SY761=y +CONFIG_TOUCHPANEL_SYNAPTICS=y +CONFIG_TOUCHPANEL_SYNAPTICS_S3706=y +CONFIG_TOUCHPANEL_ST=y +CONFIG_TOUCHPANEL_ST_FST1BA90A=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_S3320_I2C_RMI=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_DEV=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FW_UPDATE_EXTRA_SYSFS=y +#CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_TEST_REPORTING=y +#CONFIG_TOUCHSCREEN_ST=y CONFIG_INPUT_MISC=y -CONFIG_INPUT_HBTP_INPUT=y +# CONFIG_INPUT_HBTP_INPUT is not set CONFIG_INPUT_QPNP_POWER_ON=y CONFIG_INPUT_QTI_HAPTICS=y CONFIG_INPUT_UINPUT=y @@ -370,6 +394,11 @@ CONFIG_QPNP_FG_GEN4=y CONFIG_SMB1355_SLAVE_CHARGER=y CONFIG_QPNP_SMB5=y CONFIG_QPNP_QNOVO5=y +CONFIG_FG_BQ27541=y +CONFIG_ONEPLUS_FASTCHG=y +CONFIG_JOYSTICK_XPAD=y +CONFIG_HID_SONY=y +CONFIG_SONY_FF=y CONFIG_SMB1390_CHARGE_PUMP=y CONFIG_THERMAL=y CONFIG_THERMAL_WRITABLE_TRIPS=y @@ -558,8 +587,8 @@ CONFIG_RPMSG_CHAR=y CONFIG_RPMSG_QCOM_GLINK_SMEM=y CONFIG_RPMSG_QCOM_GLINK_SPSS=y CONFIG_RPMSG_QCOM_GLINK_SPI=y -CONFIG_QCOM_MEM_OFFLINE=y -CONFIG_OVERRIDE_MEMORY_LIMIT=y +# CONFIG_QCOM_MEM_OFFLINE is not set +# CONFIG_OVERRIDE_MEMORY_LIMIT is not set CONFIG_QCOM_CPUSS_DUMP=y CONFIG_QCOM_RUN_QUEUE_STATS=y CONFIG_QCOM_LLCC=y @@ -658,12 +687,17 @@ CONFIG_EXT4_FS_SECURITY=y CONFIG_EXT4_ENCRYPTION=y CONFIG_EXT4_FS_ENCRYPTION=y CONFIG_EXT4_FS_ICE_ENCRYPTION=y +CONFIG_F2FS_FS=y +CONFIG_F2FS_FS_SECURITY=y +CONFIG_F2FS_FS_ENCRYPTION=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y CONFIG_QFMT_V2=y CONFIG_FUSE_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y +CONFIG_EXFAT_FS=y +CONFIG_NTFS_FS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_EFIVAR_FS=y CONFIG_ECRYPT_FS=y @@ -682,7 +716,7 @@ CONFIG_DEBUG_SECTION_MISMATCH=y # CONFIG_SECTION_MISMATCH_WARN_ONLY is not set CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_PAGEALLOC=y -CONFIG_SLUB_DEBUG_PANIC_ON=y +# CONFIG_SLUB_DEBUG_PANIC_ON is not set CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT=y CONFIG_PAGE_POISONING=y CONFIG_PAGE_POISONING_ENABLE_DEFAULT=y @@ -691,9 +725,10 @@ CONFIG_DEBUG_OBJECTS_FREE=y CONFIG_DEBUG_OBJECTS_TIMERS=y CONFIG_DEBUG_OBJECTS_WORK=y CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y -CONFIG_SLUB_DEBUG_ON=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_SLUB_DEBUG_ON is not set CONFIG_DEBUG_KMEMLEAK=y -CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=4000 +CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=8192 CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y CONFIG_DEBUG_STACK_USAGE=y CONFIG_DEBUG_MEMORY_INIT=y @@ -773,3 +808,35 @@ CONFIG_CRYPTO_AES_ARM64_CE_CCM=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y CONFIG_XZ_DEC=y +# yangfb,2018/1/26, add for aging test get log and limmit current +CONFIG_OP_DEBUG_CHG=y +CONFIG_PSTORE=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_RAM=y +CONFIG_PSTORE_DEVICE_INFO=y +CONFIG_PSTORE_PMSG=y +CONFIG_BOOTLOADER_LOG=y +CONFIG_PROJECT_INFO=y +CONFIG_OEM_BOOT_MODE=y +CONFIG_AW8697_HAPTIC=y +CONFIG_INPUT_KEYCHORD=y +CONFIG_DIGITAL_HALL_M1120=y +CONFIG_STEP_MOTOR=y +CONFIG_RF_CABLE_DETECT=y +CONFIG_NET_CLS_CGROUP=y +CONFIG_ADJ_CHAIN=y +CONFIG_DEFRAG_HELPER=y +CONFIG_FSC=y +# zhongbin, 2019/1/4, add for memory plus project +CONFIG_MEMPLUS=y +CONFIG_SWAP=y +CONFIG_ZRAM=y +CONFIG_ZRAM_LZ4_COMPRESS=y +CONFIG_LZ4_DECOMPRESS=y +CONFIG_LZ4_COMPRESS=y +CONFIG_CRYPTO_LZ4=y +# end +CONFIG_OPCHAIN=y +CONFIG_SMART_BOOST=y +# dylanchang,2019/4/1, add for kernel log reserve +CONFIG_WB_KERNEL_LOG=y diff --git a/arch/arm64/include/uapi/asm/setup.h b/arch/arm64/include/uapi/asm/setup.h index 5d703888f35110d2a7a15ec1836bffcffae3c8bb..9f583cb9e76ecf4ce937fc93f41d0d4dcff8927a 100644 --- a/arch/arm64/include/uapi/asm/setup.h +++ b/arch/arm64/include/uapi/asm/setup.h @@ -22,6 +22,6 @@ #include -#define COMMAND_LINE_SIZE 2048 +#define COMMAND_LINE_SIZE 3072 #endif diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 92800fe7c5a052c97c09365ba8cf0c5256387e72..1f658e433ccf9ead8218231057700d92c358b890 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -524,12 +524,6 @@ const struct arm64_cpu_capabilities arm64_errata[] = { MIDR_CPU_VAR_REV(0, 0), MIDR_CPU_VAR_REV(3, 0)), }, - { - .capability = ARM64_WORKAROUND_REPEAT_TLBI, - MIDR_RANGE(MIDR_KRYO4G, - MIDR_CPU_VAR_REV(12, 14), - MIDR_CPU_VAR_REV(13, 14)), - }, #endif #ifdef CONFIG_ARM64_ERRATUM_858921 { diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 3e7958f8293b960fd339cce00ddcd7d505c5ec71..51e072e30d602b35a470268a8e167a975d0a9e5f 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -1001,7 +1001,7 @@ static void armv8pmu_idle_update(struct arm_pmu *cpu_pmu) struct perf_event *event; int idx; - if (!cpu_pmu) + if (!cpu_pmu || !(cpu_pmu->hw_events)) return; if (__this_cpu_read(is_hotplugging)) diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 7d8c7ab56bfd2621d1b5e0c4317708bb3e9583c9..d5410b91d07af9c75aa5edf509bea672ebe80198 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -897,7 +897,7 @@ asmlinkage int __exception do_debug_exception(unsigned long addr, if (!inf->fn(addr, esr, regs)) { rv = 1; } else { - pr_alert("Unhandled debug exception: %s (0x%08x) at 0x%016lx\n", + pr_info_ratelimited("Unhandled debug exception: %s (0x%08x) at 0x%016lx\n", inf->name, esr, addr); info.si_signo = inf->sig; diff --git a/drivers/Kconfig b/drivers/Kconfig index 29096a4caa440f04eb17c53a671eeaefb9156760..3bb5ee07b1aa0bb6221d41956e0e8d72d86ce92e 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -219,4 +219,8 @@ source "drivers/sensors/Kconfig" source "drivers/esoc/Kconfig" +source "drivers/oneplus/Kconfig" + +source "drivers/param_read_write/Kconfig" +source "drivers/oem_debug/Kconfig" endmenu diff --git a/drivers/Makefile b/drivers/Makefile index f409e6ddf143b813a2de6326dd3bd05c9c0bb40b..7d62aba241270231eb9fb8e82fb546bd83eaf258 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -188,3 +188,6 @@ obj-$(CONFIG_TEE) += tee/ obj-$(CONFIG_MULTIPLEXER) += mux/ obj-$(CONFIG_SENSORS_SSC) += sensors/ obj-$(CONFIG_ESOC) += esoc/ +obj-y += oneplus/ +obj-y += param_read_write/ +obj-y += oem_debug/ diff --git a/drivers/android/binder.c b/drivers/android/binder.c index 9c06e7f46d7f0f1037b6c36bccfa4a939f926946..df367aa95eff980714c6128e45d88efe554aeba5 100644 --- a/drivers/android/binder.c +++ b/drivers/android/binder.c @@ -72,10 +72,14 @@ #include #include +#include #include #include #include "binder_alloc.h" #include "binder_trace.h" +#ifdef CONFIG_OPCHAIN +#include <../drivers/oneplus/coretech/opchain/opchain_binder.h> +#endif static HLIST_HEAD(binder_deferred_list); static DEFINE_MUTEX(binder_deferred_lock); @@ -3136,7 +3140,6 @@ static void binder_transaction(struct binder_proc *proc, t->buffer = NULL; goto err_binder_alloc_buf_failed; } - t->buffer->allow_user_free = 0; t->buffer->debug_id = t->debug_id; t->buffer->transaction = t; t->buffer->target_node = target_node; @@ -3184,6 +3187,11 @@ static void binder_transaction(struct binder_proc *proc, sg_bufp = (u8 *)(PTR_ALIGN(off_end, sizeof(void *))); sg_buf_end = sg_bufp + extra_buffers_size; off_min = 0; +#ifdef CONFIG_OPCHAIN + opc_binder_pass( + t->buffer->data_size, + (uint32_t *)t->buffer->data, 1); +#endif for (; offp < off_end; offp++) { struct binder_object_header *hdr; size_t object_size = binder_validate_object(t->buffer, *offp); @@ -3632,14 +3640,18 @@ static int binder_thread_write(struct binder_proc *proc, buffer = binder_alloc_prepare_to_free(&proc->alloc, data_ptr); - if (buffer == NULL) { - binder_user_error("%d:%d BC_FREE_BUFFER u%016llx no match\n", - proc->pid, thread->pid, (u64)data_ptr); - break; - } - if (!buffer->allow_user_free) { - binder_user_error("%d:%d BC_FREE_BUFFER u%016llx matched unreturned buffer\n", - proc->pid, thread->pid, (u64)data_ptr); + if (IS_ERR_OR_NULL(buffer)) { + if (PTR_ERR(buffer) == -EPERM) { + binder_user_error( + "%d:%d BC_FREE_BUFFER u%016llx matched unreturned or currently freeing buffer\n", + proc->pid, thread->pid, + (u64)data_ptr); + } else { + binder_user_error( + "%d:%d BC_FREE_BUFFER u%016llx no match\n", + proc->pid, thread->pid, + (u64)data_ptr); + } break; } binder_debug(BINDER_DEBUG_FREE_BUFFER, @@ -5793,6 +5805,55 @@ static int __init init_binder_device(const char *name) return ret; } +static int proc_state_open(struct inode *inode, struct file *file) +{ + return single_open(file, binder_state_show, NULL); +} + +static int proc_transactions_open(struct inode *inode, struct file *file) +{ + return single_open(file, binder_transactions_show, NULL); +} + +static int proc_transaction_log_open(struct inode *inode, struct file *file) +{ + return single_open(file, binder_transaction_log_show, + &binder_transaction_log); +} + + +static const struct file_operations proc_state_operations = { + .open = proc_state_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static const struct file_operations proc_transactions_operations = { + .open = proc_transactions_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static const struct file_operations proc_transaction_log_operations = { + .open = proc_transaction_log_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int binder_proc_init(void) +{ + proc_create("proc_state", 0444, NULL, + &proc_state_operations); + proc_create("proc_transactions", 0444, NULL, + &proc_transactions_operations); + proc_create("proc_transaction_log", 0444, NULL, + &proc_transaction_log_operations); + return 0; +} + static int __init binder_init(void) { int ret; @@ -5857,6 +5918,7 @@ static int __init binder_init(void) if (ret) goto err_init_binder_device_failed; } + binder_proc_init(); return ret; diff --git a/drivers/android/binder_alloc.c b/drivers/android/binder_alloc.c index 54debce30ee079a4a6925d3aa625769b911697c8..e00d4d13810a004d61821fe9ccec31651645be8b 100644 --- a/drivers/android/binder_alloc.c +++ b/drivers/android/binder_alloc.c @@ -149,14 +149,12 @@ static struct binder_buffer *binder_alloc_prepare_to_free_locked( else { /* * Guard against user threads attempting to - * free the buffer twice + * free the buffer when in use by kernel or + * after it's already been freed. */ - if (buffer->free_in_progress) { - pr_err("%d:%d FREE_BUFFER u%016llx user freed buffer twice\n", - alloc->pid, current->pid, (u64)user_ptr); - return NULL; - } - buffer->free_in_progress = 1; + if (!buffer->allow_user_free) + return ERR_PTR(-EPERM); + buffer->allow_user_free = 0; return buffer; } } @@ -490,7 +488,7 @@ static struct binder_buffer *binder_alloc_new_buf_locked( rb_erase(best_fit, &alloc->free_buffers); buffer->free = 0; - buffer->free_in_progress = 0; + buffer->allow_user_free = 0; binder_insert_allocated_buffer_locked(alloc, buffer); binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC, "%d: binder_alloc_buf size %zd got %pK\n", diff --git a/drivers/android/binder_alloc.h b/drivers/android/binder_alloc.h index 9ef64e56385667a53abeab2f41f67b198a8ce86e..fb3238c74c8a8671282cf9a428febaf182880821 100644 --- a/drivers/android/binder_alloc.h +++ b/drivers/android/binder_alloc.h @@ -50,8 +50,7 @@ struct binder_buffer { unsigned free:1; unsigned allow_user_free:1; unsigned async_transaction:1; - unsigned free_in_progress:1; - unsigned debug_id:28; + unsigned debug_id:29; struct binder_transaction *transaction; diff --git a/drivers/base/power/wakeup.c b/drivers/base/power/wakeup.c index 50cb3da3a13c7063022778d7eb0fab5fea91ef0a..2c2a1ce90d4b55f7c6f1006b9f041841adbc81db 100644 --- a/drivers/base/power/wakeup.c +++ b/drivers/base/power/wakeup.c @@ -22,6 +22,8 @@ #include #include "power.h" +#include +#include /* * If set, the suspend/hibernate code will abort transitions to a sleep state @@ -71,6 +73,10 @@ static struct wakeup_source deleted_ws = { .lock = __SPIN_LOCK_UNLOCKED(deleted_ws.lock), }; +#define WORK_TIMEOUT (60*1000) +static void ws_printk(struct work_struct *work); +static DECLARE_DELAYED_WORK(ws_printk_work, ws_printk); + /** * wakeup_source_prepare - Prepare a new wakeup source for initialization. * @ws: Wakeup source to prepare. @@ -850,7 +856,7 @@ void pm_print_active_wakeup_sources(void) srcuidx = srcu_read_lock(&wakeup_srcu); list_for_each_entry_rcu(ws, &wakeup_sources, entry) { if (ws->active) { - pr_debug("active wakeup source: %s\n", ws->name); + pr_info("active wakeup source: %s\n", ws->name); active = 1; } else if (!active && (!last_activity_ws || @@ -861,12 +867,30 @@ void pm_print_active_wakeup_sources(void) } if (!active && last_activity_ws) - pr_debug("last active wakeup source: %s\n", + pr_info("last active wakeup source: %s\n", last_activity_ws->name); srcu_read_unlock(&wakeup_srcu, srcuidx); } EXPORT_SYMBOL_GPL(pm_print_active_wakeup_sources); +static void ws_printk(struct work_struct *work) +{ + pm_print_active_wakeup_sources(); + queue_delayed_work(system_freezable_wq, + &ws_printk_work, msecs_to_jiffies(WORK_TIMEOUT)); +} + +void pm_print_active_wakeup_sources_queue(bool on) +{ + if (on) { + queue_delayed_work(system_freezable_wq, &ws_printk_work, + msecs_to_jiffies(WORK_TIMEOUT)); + } else { + cancel_delayed_work(&ws_printk_work); + } +} +EXPORT_SYMBOL_GPL(pm_print_active_wakeup_sources_queue); + /** * pm_wakeup_pending - Check if power transition in progress should be aborted. * @@ -930,6 +954,7 @@ void pm_system_irq_wakeup(unsigned int irq_number) else if (desc->action && desc->action->name) name = desc->action->name; + log_wakeup_reason(irq_number); pr_warn("%s: %d triggered %s\n", __func__, irq_number, name); diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c index 8fd08023c0f5fae351800ab27d30a8a244eabaaa..cc60ddfd971fa90766cba4bc6e88391d4312a620 100644 --- a/drivers/base/regmap/regmap.c +++ b/drivers/base/regmap/regmap.c @@ -1651,6 +1651,9 @@ int _regmap_write(struct regmap *map, unsigned int reg, dev_info(map->dev, "%x <= %x\n", reg, val); #endif + if ( reg == 0x88E || reg == 0x88d) + dev_info(map->dev, "w:%x <= %x[%s],\n", reg, val,dev_name(map->dev)); + trace_regmap_reg_write(map, reg, val); return map->reg_write(context, reg, val); @@ -2379,6 +2382,8 @@ static int _regmap_read(struct regmap *map, unsigned int reg, if (map->dev && strcmp(dev_name(map->dev), LOG_DEVICE) == 0) dev_info(map->dev, "%x => %x\n", reg, *val); #endif + if ( reg == 0x88E || reg == 0x88d) + dev_info(map->dev, "r:%x <= %x[%s],\n", reg, val,dev_name(map->dev)); trace_regmap_reg_read(map, reg, *val); diff --git a/drivers/char/diag/diagfwd_cntl.c b/drivers/char/diag/diagfwd_cntl.c index caf833ce42b3207a4c28f6a4d186d9334f2714cd..7d88965da5598e9bdb4d6581e6e9eb8d649af6de 100644 --- a/drivers/char/diag/diagfwd_cntl.c +++ b/drivers/char/diag/diagfwd_cntl.c @@ -64,6 +64,10 @@ void diag_cntl_channel_close(struct diagfwd_info *p_info) if (peripheral >= NUM_PERIPHERALS) return; + pr_debug("diag: ETS: %s: peripheral=%d (+)\n", + __func__, peripheral); + + driver->feature[peripheral].sent_feature_mask = 0; driver->feature[peripheral].rcvd_feature_mask = 0; reg_dirty[peripheral] = 1; @@ -75,6 +79,10 @@ void diag_cntl_channel_close(struct diagfwd_info *p_info) driver->stm_state_requested[peripheral] = DISABLE_STM; reg_dirty[peripheral] = 0; diag_notify_md_client(peripheral, DIAG_STATUS_CLOSED); + + pr_debug("diag: ETS: %s: peripheral=%d (-)\n", + __func__, peripheral); + } static void diag_stm_update_work_fn(struct work_struct *work) @@ -1136,8 +1144,13 @@ void diag_real_time_work_fn(struct work_struct *work) if (peripheral == APPS_DATA) continue; - if (peripheral > NUM_PERIPHERALS) + if (peripheral > NUM_PERIPHERALS) { peripheral = diag_search_peripheral_by_pd(i); + if (peripheral > NUM_PERIPHERALS) { + pr_warn("invalid peripheral for pd %d\n", i); + continue; + } + } if (!driver->feature[peripheral].peripheral_buffering) continue; diff --git a/drivers/char/misc.c b/drivers/char/misc.c index 1bb9e7cc82e306a34c970540e58301d0ca2a60ac..b4c4312ab6d2eb072f410853df6fdaa44b2aa697 100644 --- a/drivers/char/misc.c +++ b/drivers/char/misc.c @@ -60,7 +60,7 @@ static DEFINE_MUTEX(misc_mtx); /* * Assigned numbers, used for dynamic minors */ -#define DYNAMIC_MINORS 64 /* like dynamic majors */ +#define DYNAMIC_MINORS 128 /* like dynamic majors */ static DECLARE_BITMAP(misc_minors, DYNAMIC_MINORS); #ifdef CONFIG_PROC_FS diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index e562c92b63c9a5836075044e95364f4444387d7c..854013b5884ea2d941a8d4b8de07c21104b99994 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -1,7 +1,7 @@ /* * Copyright (C) 2010-2011 Canonical Ltd * Copyright (C) 2011-2012 Linaro Ltd - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -49,6 +49,17 @@ struct clk_handoff_vdd { }; static LIST_HEAD(clk_handoff_vdd_list); +static bool vdd_class_handoff_completed; +static DEFINE_MUTEX(vdd_class_list_lock); +/* + * clk_rate_change_list is used during clk_core_set_rate_nolock() calls to + * handle vdd_class vote tracking. core->rate_change_node is added to + * clk_rate_change_list when core->new_rate requires a different voltage level + * (core->new_vdd_class_vote) than core->vdd_class_vote. Elements are removed + * from the list after unvoting core->vdd_class_vote immediately before + * returning from clk_core_set_rate_nolock(). + */ +static LIST_HEAD(clk_rate_change_list); /*** private data structures ***/ @@ -88,6 +99,9 @@ struct clk_core { #endif struct kref ref; struct clk_vdd_class *vdd_class; + int vdd_class_vote; + int new_vdd_class_vote; + struct list_head rate_change_node; unsigned long *rate_max; int num_rate_max; }; @@ -632,9 +646,11 @@ static int clk_unvote_vdd_level(struct clk_vdd_class *vdd_class, int level) mutex_lock(&vdd_class->lock); if (WARN(!vdd_class->level_votes[level], - "Reference counts are incorrect for %s level %d\n", - vdd_class->class_name, level)) + "Reference counts are incorrect for %s level %d\n", + vdd_class->class_name, level)) { + rc = -EINVAL; goto out; + } vdd_class->level_votes[level]--; @@ -698,29 +714,43 @@ static bool clk_is_rate_level_valid(struct clk_core *core, unsigned long rate) static int clk_vdd_class_init(struct clk_vdd_class *vdd) { struct clk_handoff_vdd *v; + int ret = 0; if (vdd->skip_handoff) return 0; + mutex_lock(&vdd_class_list_lock); + list_for_each_entry(v, &clk_handoff_vdd_list, list) { if (v->vdd_class == vdd) - return 0; + goto done; } - pr_debug("voting for vdd_class %s\n", vdd->class_name); + if (!vdd_class_handoff_completed) { + pr_debug("voting for vdd_class %s\n", vdd->class_name); - if (clk_vote_vdd_level(vdd, vdd->num_levels - 1)) - pr_err("failed to vote for %s\n", vdd->class_name); + ret = clk_vote_vdd_level(vdd, vdd->num_levels - 1); + if (ret) { + pr_err("failed to vote for %s, ret=%d\n", + vdd->class_name, ret); + goto done; + } + } v = kmalloc(sizeof(*v), GFP_KERNEL); - if (!v) - return -ENOMEM; + if (!v) { + ret = -ENOMEM; + goto done; + } v->vdd_class = vdd; list_add_tail(&v->list, &clk_handoff_vdd_list); - return 0; +done: + mutex_unlock(&vdd_class_list_lock); + + return ret; } /*** clk api ***/ @@ -750,7 +780,11 @@ static void clk_core_unprepare(struct clk_core *core) trace_clk_unprepare_complete(core); - clk_unvote_rate_vdd(core, core->rate); + if (core->vdd_class) { + clk_unvote_vdd_level(core->vdd_class, core->vdd_class_vote); + core->vdd_class_vote = 0; + core->new_vdd_class_vote = 0; + } clk_core_unprepare(core->parent); } @@ -803,6 +837,11 @@ static int clk_core_prepare(struct clk_core *core) clk_core_unprepare(core->parent); return ret; } + if (core->vdd_class) { + core->vdd_class_vote + = clk_find_vdd_level(core, core->rate); + core->new_vdd_class_vote = core->vdd_class_vote; + } if (core->ops->prepare) ret = core->ops->prepare(core->hw); @@ -811,6 +850,8 @@ static int clk_core_prepare(struct clk_core *core) if (ret) { clk_unvote_rate_vdd(core, core->rate); + core->vdd_class_vote = 0; + core->new_vdd_class_vote = 0; clk_core_unprepare(core->parent); return ret; } @@ -1125,12 +1166,15 @@ static int clk_disable_unused(void) hlist_for_each_entry(core, &clk_orphan_list, child_node) clk_unprepare_unused_subtree(core); + mutex_lock(&vdd_class_list_lock); list_for_each_entry_safe(v, v_temp, &clk_handoff_vdd_list, list) { clk_unvote_vdd_level(v->vdd_class, v->vdd_class->num_levels - 1); list_del(&v->list); kfree(v); }; + vdd_class_handoff_completed = true; + mutex_unlock(&vdd_class_list_lock); clk_prepare_unlock(); @@ -1614,12 +1658,59 @@ static int __clk_speculate_rates(struct clk_core *core, return ret; } -static void clk_calc_subtree(struct clk_core *core, unsigned long new_rate, +/* + * Vote for the voltage level required for core->new_rate. Keep track of all + * clocks with a changed voltage level in clk_rate_change_list. + */ +static int clk_vote_new_rate_vdd(struct clk_core *core) +{ + int cur_level, next_level; + int ret; + + if (IS_ERR_OR_NULL(core) || !core->vdd_class) + return 0; + + if (!clk_core_is_prepared(core)) + return 0; + + cur_level = core->new_vdd_class_vote; + next_level = clk_find_vdd_level(core, core->new_rate); + if (cur_level == next_level) + return 0; + + ret = clk_vote_vdd_level(core->vdd_class, next_level); + if (ret) + return ret; + + core->new_vdd_class_vote = next_level; + + if (list_empty(&core->rate_change_node)) { + list_add(&core->rate_change_node, &clk_rate_change_list); + } else { + /* + * A different new_rate has been determined for a clock that + * was already encountered in the clock tree traversal so the + * level that was previously voted for it should be removed. + */ + ret = clk_unvote_vdd_level(core->vdd_class, cur_level); + if (ret) + return ret; + } + + return 0; +} + +static int clk_calc_subtree(struct clk_core *core, unsigned long new_rate, struct clk_core *new_parent, u8 p_index) { struct clk_core *child; + int ret; core->new_rate = new_rate; + ret = clk_vote_new_rate_vdd(core); + if (ret) + return ret; + core->new_parent = new_parent; core->new_parent_index = p_index; /* include clk in new parent's PRE_RATE_CHANGE notifications */ @@ -1629,8 +1720,12 @@ static void clk_calc_subtree(struct clk_core *core, unsigned long new_rate, hlist_for_each_entry(child, &core->children, child_node) { child->new_rate = clk_recalc(child, new_rate); - clk_calc_subtree(child, child->new_rate, NULL, 0); + ret = clk_calc_subtree(child, child->new_rate, NULL, 0); + if (ret) + return ret; } + + return 0; } /* @@ -1734,7 +1829,9 @@ static struct clk_core *clk_calc_new_rates(struct clk_core *core, if (!clk_is_rate_level_valid(core, rate)) return NULL; - clk_calc_subtree(core, new_rate, parent, p_index); + ret = clk_calc_subtree(core, new_rate, parent, p_index); + if (ret) + return NULL; return top; } @@ -1814,13 +1911,6 @@ static int clk_change_rate(struct clk_core *core) trace_clk_set_rate(core, core->new_rate); - /* Enforce vdd requirements for new frequency. */ - if (core->prepare_count) { - rc = clk_vote_rate_vdd(core, core->new_rate); - if (rc) - goto out; - } - if (core->new_parent && core->new_parent != core->parent) { old_parent = __clk_set_parent_before(core, core->new_parent); trace_clk_set_parent(core, core->new_parent); @@ -1850,10 +1940,6 @@ static int clk_change_rate(struct clk_core *core) trace_clk_set_rate_complete(core, core->new_rate); - /* Release vdd requirements for old frequency. */ - if (core->prepare_count) - clk_unvote_rate_vdd(core, old_rate); - core->rate = clk_recalc(core, best_parent_rate); if (core->flags & CLK_SET_RATE_UNGATE) { @@ -1894,20 +1980,89 @@ static int clk_change_rate(struct clk_core *core) return rc; err_set_rate: - if (core->prepare_count) - clk_unvote_rate_vdd(core, core->new_rate); -out: trace_clk_set_rate_complete(core, core->new_rate); return rc; } +/* + * Unvote for the voltage level required for each core->new_vdd_class_vote in + * clk_rate_change_list. This is used when undoing voltage requests after an + * error is encountered before any physical rate changing. + */ +static void clk_unvote_new_rate_vdd(void) +{ + struct clk_core *core; + + list_for_each_entry(core, &clk_rate_change_list, rate_change_node) { + clk_unvote_vdd_level(core->vdd_class, core->new_vdd_class_vote); + core->new_vdd_class_vote = core->vdd_class_vote; + } +} + +/* + * Unvote for the voltage level required for each core->vdd_class_vote in + * clk_rate_change_list. + */ +static int clk_unvote_old_rate_vdd(void) +{ + struct clk_core *core; + int ret; + + list_for_each_entry(core, &clk_rate_change_list, rate_change_node) { + ret = clk_unvote_vdd_level(core->vdd_class, + core->vdd_class_vote); + if (ret) + return ret; + } + + return 0; +} + +/* + * In the case that rate setting fails, apply the max voltage level needed + * by either the old or new rate for each changed clock. + */ +static void clk_vote_safe_vdd(void) +{ + struct clk_core *core; + + list_for_each_entry(core, &clk_rate_change_list, rate_change_node) { + if (core->vdd_class_vote > core->new_vdd_class_vote) { + clk_vote_vdd_level(core->vdd_class, + core->vdd_class_vote); + clk_unvote_vdd_level(core->vdd_class, + core->new_vdd_class_vote); + core->new_vdd_class_vote = core->vdd_class_vote; + } + } +} + +static void clk_cleanup_vdd_votes(void) +{ + struct clk_core *core, *temp; + + list_for_each_entry_safe(core, temp, &clk_rate_change_list, + rate_change_node) { + core->vdd_class_vote = core->new_vdd_class_vote; + list_del_init(&core->rate_change_node); + } +} static int clk_core_set_rate_nolock(struct clk_core *core, unsigned long req_rate) { struct clk_core *top, *fail_clk; unsigned long rate = req_rate; int ret = 0; + /* + * The prepare lock ensures mutual exclusion with other tasks. + * set_rate_nesting_count is a static so that it can be incremented in + * the case of reentrancy caused by a set_rate() ops callback itself + * calling clk_set_rate(). That way, the voltage level votes for the + * old rates are safely removed when the original invocation of this + * function completes. + */ + static unsigned int set_rate_nesting_count; if (!core) return 0; @@ -1921,8 +2076,10 @@ static int clk_core_set_rate_nolock(struct clk_core *core, /* calculate new rates and get the topmost changed clock */ top = clk_calc_new_rates(core, rate); - if (!top) - return -EINVAL; + if (!top) { + ret = -EINVAL; + goto pre_rate_change_err; + } /* notify that we are about to change rates */ fail_clk = clk_propagate_rate_change(top, PRE_RATE_CHANGE); @@ -1930,20 +2087,43 @@ static int clk_core_set_rate_nolock(struct clk_core *core, pr_debug("%s: failed to set %s clock to run at %lu\n", __func__, fail_clk->name, req_rate); clk_propagate_rate_change(top, ABORT_RATE_CHANGE); - return -EBUSY; + ret = -EBUSY; + goto pre_rate_change_err; } + /* change the rates */ + set_rate_nesting_count++; ret = clk_change_rate(top); + set_rate_nesting_count--; if (ret) { pr_err("%s: failed to set %s clock to run at %lu\n", __func__, top->name, req_rate); clk_propagate_rate_change(top, ABORT_RATE_CHANGE); - return ret; + clk_vote_safe_vdd(); + goto post_rate_change_err; } core->req_rate = req_rate; +post_rate_change_err: + /* + * Only remove vdd_class level votes for old clock rates after all + * nested clk_set_rate() calls have completed. + */ + if (set_rate_nesting_count == 0) { + ret |= clk_unvote_old_rate_vdd(); + clk_cleanup_vdd_votes(); + } + + return ret; + +pre_rate_change_err: + if (set_rate_nesting_count == 0) { + clk_unvote_new_rate_vdd(); + clk_cleanup_vdd_votes(); + } + return ret; } @@ -3688,6 +3868,7 @@ struct clk *clk_register(struct device *dev, struct clk_hw *hw) }; INIT_HLIST_HEAD(&core->clks); + INIT_LIST_HEAD(&core->rate_change_node); hw->clk = __clk_create_clk(hw, NULL, NULL); if (IS_ERR(hw->clk)) { diff --git a/drivers/clk/qcom/clk-cpu-osm.c b/drivers/clk/qcom/clk-cpu-osm.c index 874a6f07b96e95c519278d1d43895301025534d6..7fe046cd25752ce282c7408d04a336da5650c85b 100644 --- a/drivers/clk/qcom/clk-cpu-osm.c +++ b/drivers/clk/qcom/clk-cpu-osm.c @@ -79,6 +79,7 @@ struct clk_osm { u64 total_cycle_counter; u32 prev_cycle_counter; unsigned long rate; + cpumask_t related_cpus; }; static bool is_sdmshrike; @@ -560,7 +561,8 @@ static struct clk_osm *osm_configure_policy(struct cpufreq_policy *policy) if (parent != c_parent) continue; - cpumask_set_cpu(cpu, policy->cpus); + /* cpumask_set_cpu(cpu, policy->cpus); */ + cpumask_set_cpu(cpu, &c->related_cpus); if (n->core_num == 0) first = n; } @@ -688,6 +690,9 @@ static int osm_cpufreq_cpu_init(struct cpufreq_policy *policy) policy->dvfs_possible_from_any_cpu = true; policy->fast_switch_possible = true; policy->driver_data = c; + + cpumask_copy(policy->cpus, &c->related_cpus); + return 0; err: diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 01e82010f7e4b50dc863ae1155ccb04c9653b6b6..83b90a7305abbb4ebae896e73582b29af905573b 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013, 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2013, 2016-2018, The Linux Foundation. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -391,6 +391,39 @@ static int clk_rcg2_determine_floor_rate(struct clk_hw *hw, return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR); } +static bool clk_rcg2_current_config(struct clk_rcg2 *rcg, + const struct freq_tbl *f) +{ + struct clk_hw *hw = &rcg->clkr.hw; + u32 cfg, mask, new_cfg; + int index; + + if (rcg->mnd_width) { + mask = BIT(rcg->mnd_width) - 1; + regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG, &cfg); + if ((cfg & mask) != (f->m & mask)) + return false; + + regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG, &cfg); + if ((cfg & mask) != (~(f->n - f->m) & mask)) + return false; + } + + mask = (BIT(rcg->hid_width) - 1) | CFG_SRC_SEL_MASK; + + index = qcom_find_src_index(hw, rcg->parent_map, f->src); + + new_cfg = ((f->pre_div << CFG_SRC_DIV_SHIFT) | + (rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT)) & mask; + + regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); + + if (new_cfg != (cfg & mask)) + return false; + + return true; +} + static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) { u32 cfg, mask, old_cfg; @@ -1034,6 +1067,8 @@ static int clk_byte2_set_rate(struct clk_hw *hw, unsigned long rate, for (i = 0; i < num_parents; i++) { if (cfg == rcg->parent_map[i].cfg) { f.src = rcg->parent_map[i].src; + if (clk_rcg2_current_config(rcg, &f)) + return 0; return clk_rcg2_configure(rcg, &f); } } @@ -1130,6 +1165,9 @@ static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate, f.m = frac->num; f.n = frac->den; + if (clk_rcg2_current_config(rcg, &f)) + return 0; + return clk_rcg2_configure(rcg, &f); } return -EINVAL; diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index 93893c3aae16c0c468177742771dda67fa78069b..93cb5c93bc76a24cb7994d380d6cf9b8614b2ffd 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -32,7 +32,10 @@ #include #include +#include #include +#define GOLD_CPU_NUMBER 4 +#define GOLD_PLUS_CPU_NUMBER 7 static LIST_HEAD(cpufreq_policy_list); @@ -59,6 +62,29 @@ static LIST_HEAD(cpufreq_governor_list); #define for_each_governor(__governor) \ list_for_each_entry(__governor, &cpufreq_governor_list, governor_list) +struct qos_request_value { + bool flag; + unsigned int max_cpufreq; + unsigned int min_cpufreq; +}; +static struct qos_request_value c0_qos_request_value = { + .flag = false, + .max_cpufreq = INT_MAX, + .min_cpufreq = MIN_CPUFREQ, +}; +static struct qos_request_value c1_qos_request_value = { + .flag = false, + .max_cpufreq = INT_MAX, + .min_cpufreq = MIN_CPUFREQ, +}; +static struct qos_request_value c2_qos_request_value = { + .flag = false, + .max_cpufreq = INT_MAX, + .min_cpufreq = MIN_CPUFREQ, +}; +unsigned int cluster1_first_cpu = GOLD_CPU_NUMBER; +unsigned int cluster2_first_cpu = GOLD_PLUS_CPU_NUMBER; + /** * The "cpufreq driver" - the arch- or hardware-dependent low * level driver of CPUFreq support, and its spinlock. This lock @@ -341,7 +367,8 @@ static void __cpufreq_notify_transition(struct cpufreq_policy *policy, pr_debug("FREQ: %lu - CPU: %lu\n", (unsigned long)freqs->new, (unsigned long)freqs->cpu); trace_cpu_frequency(freqs->new, freqs->cpu); - cpufreq_stats_record_transition(policy, freqs->new); + if (freqs->new != policy->cur) + cpufreq_stats_record_transition(policy, freqs->new); cpufreq_times_record_transition(freqs); srcu_notifier_call_chain(&cpufreq_transition_notifier_list, CPUFREQ_POSTCHANGE, freqs); @@ -1862,7 +1889,17 @@ EXPORT_SYMBOL(cpufreq_unregister_notifier); unsigned int cpufreq_driver_fast_switch(struct cpufreq_policy *policy, unsigned int target_freq) { + struct qos_request_value *qos; + target_freq = clamp_val(target_freq, policy->min, policy->max); + if (policy->cpu >= cluster2_first_cpu) + qos = &c2_qos_request_value; + else { + qos = policy->cpu >= cluster1_first_cpu ? + &c1_qos_request_value : &c0_qos_request_value; + } + target_freq = clamp_val(target_freq, qos->min_cpufreq, + qos->max_cpufreq); return cpufreq_driver->fast_switch(policy, target_freq); } @@ -2619,3 +2656,285 @@ static int __init cpufreq_core_init(void) } module_param(off, int, 0444); core_initcall(cpufreq_core_init); + +static int get_c0_available_cpufreq(struct cpufreq_policy *policy) +{ + int max_cpufreq_index = -1, min_cpufreq_index = -1; + int max_index = -1; + int index_max = 0, index_min = 0; + struct cpufreq_frequency_table *table, *pos; + + table = policy->freq_table; + if (!table) { + pr_err("cpufreq:Failed to get frequency table for CPU%u\n", 0); + return -EINVAL; + } + + max_cpufreq_index = (unsigned int)pm_qos_request(PM_QOS_C0_CPUFREQ_MAX); + min_cpufreq_index = (unsigned int)pm_qos_request(PM_QOS_C0_CPUFREQ_MIN); + + /* you can limit the min cpufreq*/ + if (min_cpufreq_index > max_cpufreq_index) + max_cpufreq_index = min_cpufreq_index; + + /* get the available cpufreq + * lock for the max available cpufreq + */ + cpufreq_for_each_valid_entry(pos, table) { + max_index = pos - table; + } + if (max_cpufreq_index & MASK_CPUFREQ) { + index_max = MAX_CPUFREQ - max_cpufreq_index; + if (index_max > max_index) + index_max = 0; + index_max = max_index - index_max; + } else { + if (max_cpufreq_index > max_index) + index_max = max_index; + } + if (min_cpufreq_index & MASK_CPUFREQ) { + index_min = MAX_CPUFREQ - min_cpufreq_index; + if (index_min > max_index) + index_min = 0; + index_min = max_index - index_min; + } else { + if (min_cpufreq_index > max_index) + index_min = max_index; + } + c0_qos_request_value.max_cpufreq = table[index_max].frequency; + c0_qos_request_value.min_cpufreq = table[index_min].frequency; + pr_debug("c0::: m:%d, ii:%d-, mm:%d-", max_index, index_min, index_max); + + return 0; +} + +static int get_c1_available_cpufreq(struct cpufreq_policy *policy) +{ + int max_cpufreq_index = -1, min_cpufreq_index = -1; + int max_index = -1; + int index_max = 0, index_min = 0; + struct cpufreq_frequency_table *table, *pos; + + table = policy->freq_table; + if (!table) { + pr_err("cpufreq: Failed to get frequency table for CPU\n"); + return -EINVAL; + } + + max_cpufreq_index = (unsigned int)pm_qos_request(PM_QOS_C1_CPUFREQ_MAX); + min_cpufreq_index = (unsigned int)pm_qos_request(PM_QOS_C1_CPUFREQ_MIN); + + /* you can limit the min cpufreq*/ + if (min_cpufreq_index > max_cpufreq_index) + max_cpufreq_index = min_cpufreq_index; + + /* get the available cpufreq + * lock for the max available cpufreq + */ + cpufreq_for_each_valid_entry(pos, table) { + max_index = pos - table; + } + + /* add limits */ + if (max_cpufreq_index & MASK_CPUFREQ) { + index_max = MAX_CPUFREQ - max_cpufreq_index; + if (index_max > max_index) + index_max = 0; + index_max = max_index - index_max; + } else { + if (max_cpufreq_index > max_index) + index_max = max_index; + } + if (min_cpufreq_index & MASK_CPUFREQ) { + index_min = MAX_CPUFREQ - min_cpufreq_index; + if (index_min > max_index) + index_min = 0; + index_min = max_index - index_min; + } else { + if (min_cpufreq_index > max_index) + index_min = max_index; + } + c1_qos_request_value.max_cpufreq = table[index_max].frequency; + c1_qos_request_value.min_cpufreq = table[index_min].frequency; + pr_debug("c1::: m:%d, ii:%d-, mm:%d-", max_index, index_min, index_max); + + return 0; +} + +static int get_c2_available_cpufreq(struct cpufreq_policy *policy) +{ + int max_cpufreq_index = -1, min_cpufreq_index = -1; + int max_index = -1; + int index_max = 0, index_min = 0; + struct cpufreq_frequency_table *table, *pos; + + table = policy->freq_table; + if (!table) { + pr_err("cpufreq: Failed to get frequency table for CPU\n"); + return -EINVAL; + } + + max_cpufreq_index = (unsigned int)pm_qos_request(PM_QOS_C2_CPUFREQ_MAX); + min_cpufreq_index = (unsigned int)pm_qos_request(PM_QOS_C2_CPUFREQ_MIN); + + /* you can limit the min cpufreq*/ + if (min_cpufreq_index > max_cpufreq_index) + max_cpufreq_index = min_cpufreq_index; + + /* get the available cpufreq + * lock for the max available cpufreq + */ + cpufreq_for_each_valid_entry(pos, table) { + max_index = pos - table; + } + + /* add limits */ + if (max_cpufreq_index & MASK_CPUFREQ) { + index_max = MAX_CPUFREQ - max_cpufreq_index; + if (index_max > max_index) + index_max = 0; + index_max = max_index - index_max; + } else { + if (max_cpufreq_index > max_index) + index_max = max_index; + } + if (min_cpufreq_index & MASK_CPUFREQ) { + index_min = MAX_CPUFREQ - min_cpufreq_index; + if (index_min > max_index) + index_min = 0; + index_min = max_index - index_min; + } else { + if (min_cpufreq_index > max_index) + index_min = max_index; + } + c2_qos_request_value.max_cpufreq = table[index_max].frequency; + c2_qos_request_value.min_cpufreq = table[index_min].frequency; + pr_debug("c2::: m:%d, ii:%d-, mm:%d-", max_index, index_min, index_max); + + return 0; +} + +static int c0_cpufreq_qos_handler(struct notifier_block *b, + unsigned long val, void *v) +{ + struct cpufreq_policy *policy; + int ret = -1; + + policy = cpufreq_cpu_get(0); + + if (!policy) + return NOTIFY_BAD; + + if (!policy->governor) { + cpufreq_cpu_put(policy); + return NOTIFY_BAD; + } + + if (strcmp(policy->governor->name, "schedutil")) { + cpufreq_cpu_put(policy); + return NOTIFY_OK; + } + + ret = get_c0_available_cpufreq(policy); + if (ret) { + cpufreq_cpu_put(policy); + return NOTIFY_BAD; + } + cpufreq_driver_fast_switch(policy, c0_qos_request_value.min_cpufreq); + + cpufreq_cpu_put(policy); + return NOTIFY_OK; +} + +static struct notifier_block c0_cpufreq_qos_notifier = { + .notifier_call = c0_cpufreq_qos_handler, +}; + +static int c1_cpufreq_qos_handler(struct notifier_block *b, + unsigned long val, void *v) +{ + struct cpufreq_policy *policy; + int ret = -1; + + policy = cpufreq_cpu_get(cluster1_first_cpu); + + if (!policy) + return NOTIFY_BAD; + + if (!policy->governor) { + cpufreq_cpu_put(policy); + return NOTIFY_BAD; + } + + if (strcmp(policy->governor->name, "schedutil")) { + cpufreq_cpu_put(policy); + return NOTIFY_OK; + } + + ret = get_c1_available_cpufreq(policy); + if (ret) { + cpufreq_cpu_put(policy); + return NOTIFY_BAD; + } + + cpufreq_driver_fast_switch(policy, c1_qos_request_value.min_cpufreq); + + cpufreq_cpu_put(policy); + + return NOTIFY_OK; +} + +static struct notifier_block c1_cpufreq_qos_notifier = { + .notifier_call = c1_cpufreq_qos_handler, +}; + +static int c2_cpufreq_qos_handler(struct notifier_block *b, + unsigned long val, void *v) +{ + struct cpufreq_policy *policy; + int ret = -1; + + policy = cpufreq_cpu_get(cluster2_first_cpu); + + if (!policy) + return NOTIFY_BAD; + + if (!policy->governor) { + cpufreq_cpu_put(policy); + return NOTIFY_BAD; + } + + if (strcmp(policy->governor->name, "schedutil")) { + cpufreq_cpu_put(policy); + return NOTIFY_OK; + } + + ret = get_c2_available_cpufreq(policy); + if (ret) { + cpufreq_cpu_put(policy); + return NOTIFY_BAD; + } + + cpufreq_driver_fast_switch(policy, c2_qos_request_value.min_cpufreq); + + cpufreq_cpu_put(policy); + + return NOTIFY_OK; +} + +static struct notifier_block c2_cpufreq_qos_notifier = { + .notifier_call = c2_cpufreq_qos_handler, +}; + +static int __init pm_qos_notifier_init(void) +{ + /* add cpufreq qos notify */ + pm_qos_add_notifier(PM_QOS_C0_CPUFREQ_MAX, &c0_cpufreq_qos_notifier); + pm_qos_add_notifier(PM_QOS_C0_CPUFREQ_MIN, &c0_cpufreq_qos_notifier); + pm_qos_add_notifier(PM_QOS_C1_CPUFREQ_MAX, &c1_cpufreq_qos_notifier); + pm_qos_add_notifier(PM_QOS_C1_CPUFREQ_MIN, &c1_cpufreq_qos_notifier); + pm_qos_add_notifier(PM_QOS_C2_CPUFREQ_MAX, &c2_cpufreq_qos_notifier); + pm_qos_add_notifier(PM_QOS_C2_CPUFREQ_MIN, &c2_cpufreq_qos_notifier); + return 0; +} +subsys_initcall(pm_qos_notifier_init); diff --git a/drivers/cpufreq/cpufreq_performance.c b/drivers/cpufreq/cpufreq_performance.c index dafb679adc589ed533ef6dd02c186fb5ed03f4cc..3674faffe8d18ee53c3e72829d28a3a4b336b8cf 100644 --- a/drivers/cpufreq/cpufreq_performance.c +++ b/drivers/cpufreq/cpufreq_performance.c @@ -15,11 +15,45 @@ #include #include #include +#include + +#define CPUFREQ_INDEX 5 static void cpufreq_gov_performance_limits(struct cpufreq_policy *policy) { + unsigned int index = 0; + unsigned int valid_freq; + struct cpufreq_frequency_table *table, *pos; + static unsigned int first_cpu = 1010; + pr_debug("setting to %u kHz\n", policy->max); - __cpufreq_driver_target(policy, policy->max, CPUFREQ_RELATION_H); + if (get_boot_mode() == MSM_BOOT_MODE__WLAN + || (get_boot_mode() == MSM_BOOT_MODE__RF) + || (get_boot_mode() == MSM_BOOT_MODE__FACTORY)) { + if (first_cpu != cpumask_first(policy->related_cpus)) + first_cpu = cpumask_first(policy->related_cpus); + table = policy->freq_table; + if (!table) { + pr_err("Failed to get freqtable\n"); + } else { + for (pos = table; pos->frequency + != CPUFREQ_TABLE_END; pos++) + index++; + if (index > CPUFREQ_INDEX) + index = index - CPUFREQ_INDEX; + valid_freq = table[index].frequency; + if (valid_freq) + __cpufreq_driver_target(policy, + valid_freq, + CPUFREQ_RELATION_H); + else + __cpufreq_driver_target(policy, + policy->max, + CPUFREQ_RELATION_H); + } + } else + __cpufreq_driver_target(policy, policy->max, + CPUFREQ_RELATION_H); } static struct cpufreq_governor cpufreq_gov_performance = { diff --git a/drivers/cpufreq/cpufreq_stats.c b/drivers/cpufreq/cpufreq_stats.c index e75880eb037d3b358b8afcfa80fa5d8b41353610..994e630ed91085033e4e737b927c8fcae24b34a2 100644 --- a/drivers/cpufreq/cpufreq_stats.c +++ b/drivers/cpufreq/cpufreq_stats.c @@ -29,12 +29,13 @@ struct cpufreq_stats { static int cpufreq_stats_update(struct cpufreq_stats *stats) { + unsigned long flags; unsigned long long cur_time = get_jiffies_64(); - spin_lock(&cpufreq_stats_lock); + spin_lock_irqsave(&cpufreq_stats_lock, flags); stats->time_in_state[stats->last_index] += cur_time - stats->last_time; stats->last_time = cur_time; - spin_unlock(&cpufreq_stats_lock); + spin_unlock_irqrestore(&cpufreq_stats_lock, flags); return 0; } @@ -59,8 +60,6 @@ static ssize_t show_time_in_state(struct cpufreq_policy *policy, char *buf) ssize_t len = 0; int i; - if (policy->fast_switch_enabled) - return 0; cpufreq_stats_update(stats); for (i = 0; i < stats->state_num; i++) { @@ -85,8 +84,6 @@ static ssize_t show_trans_table(struct cpufreq_policy *policy, char *buf) ssize_t len = 0; int i, j; - if (policy->fast_switch_enabled) - return 0; len += snprintf(buf + len, PAGE_SIZE - len, " From : To\n"); len += snprintf(buf + len, PAGE_SIZE - len, " : "); @@ -235,7 +232,7 @@ void cpufreq_stats_record_transition(struct cpufreq_policy *policy, new_index = freq_table_get_index(stats, new_freq); /* We can't do stats->time_in_state[-1]= .. */ - if (old_index == -1 || new_index == -1 || old_index == new_index) + if (new_index == -1) return; cpufreq_stats_update(stats); diff --git a/drivers/cpuidle/lpm-levels.c b/drivers/cpuidle/lpm-levels.c index 7553ee21b6f97a376c26bdaefe7e2e25d535ec7e..953d99f8f2d5aa556d55a6a00bd889cee719881b 100644 --- a/drivers/cpuidle/lpm-levels.c +++ b/drivers/cpuidle/lpm-levels.c @@ -126,6 +126,12 @@ module_param_named(print_parsed_dt, print_parsed_dt, bool, 0664); static bool sleep_disabled; module_param_named(sleep_disabled, sleep_disabled, bool, 0664); +void msm_cpuidle_set_sleep_disable(bool disable) +{ + sleep_disabled = disable; + pr_info("%s:sleep_disabled=%d\n", __func__, disable); +} + /** * msm_cpuidle_get_deep_idle_latency - Get deep idle latency value * diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c index 586691521ec2377a20a90871b74b637fd45cde2b..9e79d52e0b01af7c978c1f8adff93cb77e002843 100644 --- a/drivers/devfreq/devfreq.c +++ b/drivers/devfreq/devfreq.c @@ -464,7 +464,9 @@ void devfreq_interval_update(struct devfreq *devfreq, unsigned int *delay) mutex_unlock(&devfreq->lock); cancel_delayed_work_sync(&devfreq->work); mutex_lock(&devfreq->lock); - if (!devfreq->stop_polling) + + if (!devfreq->stop_polling + && !delayed_work_pending(&devfreq->work)) queue_delayed_work(devfreq_wq, &devfreq->work, msecs_to_jiffies(devfreq->profile->polling_ms)); } diff --git a/drivers/devfreq/devfreq_devbw.c b/drivers/devfreq/devfreq_devbw.c index e7fcc11a2c08cf291cd95bbe420a0806b788a6a6..ed46634cb244e695fb90e6cbd9afef1030e83720 100644 --- a/drivers/devfreq/devfreq_devbw.c +++ b/drivers/devfreq/devfreq_devbw.c @@ -35,6 +35,19 @@ #define MAX_PATHS 2 #define DBL_BUF 2 +#include +struct qos_request_v { + int max_state; + int max_devfreq; + int min_devfreq; +}; + +static bool cpubw_flag; +static struct qos_request_v qos_request_value = { + .max_state = 0, + .max_devfreq = INT_MAX, + .min_devfreq = 0, +}; struct dev_data { struct msm_bus_vectors vectors[MAX_PATHS * DBL_BUF]; struct msm_bus_paths bw_levels[DBL_BUF]; @@ -78,6 +91,50 @@ static int set_bw(struct device *dev, int new_ib, int new_ab) return ret; } +static void find_freq_cpubw(struct devfreq_dev_profile *p, unsigned long *freq, + u32 flags) +{ + int i; + unsigned long atmost, atleast, f; + int min_index, max_index; + + min_index = qos_request_value.min_devfreq; + if (p->max_state > qos_request_value.max_devfreq) + max_index = qos_request_value.max_devfreq; + else + max_index = p->max_state; + + atmost = p->freq_table[min_index]; + atleast = p->freq_table[max_index-1]; + + for (i = min_index; i < max_index; i++) { + f = p->freq_table[i]; + if (f <= *freq) + atmost = max(f, atmost); + if (f >= *freq) + atleast = min(f, atleast); + } + + if (flags & DEVFREQ_FLAG_LEAST_UPPER_BOUND) + *freq = atmost; + else + *freq = atleast; +} + +static int devbw_target_cpubw(struct device *dev, unsigned long *freq, + u32 flags) +{ + struct dev_data *d = dev_get_drvdata(dev); + struct dev_pm_opp *opp; + + opp = devfreq_recommended_opp(dev, freq, flags); + if (!IS_ERR(opp)) + dev_pm_opp_put(opp); + find_freq_cpubw(&d->dp, freq, flags); + + return set_bw(dev, *freq, d->gov_ab); +} + static int devbw_target(struct device *dev, unsigned long *freq, u32 flags) { struct dev_data *d = dev_get_drvdata(dev); @@ -99,6 +156,44 @@ static int devbw_get_dev_status(struct device *dev, return 0; } +static int devfreq_qos_handler(struct notifier_block *b, unsigned long val, + void *v) +{ + unsigned int max_devfreq_index, min_devfreq_index; + unsigned int index_max = 0, index_min = 0; + + max_devfreq_index = (unsigned int)pm_qos_request(PM_QOS_DEVFREQ_MAX); + min_devfreq_index = (unsigned int)pm_qos_request(PM_QOS_DEVFREQ_MIN); + + /* add limit */ + if (max_devfreq_index & MASK_CPUFREQ) { + index_max = MAX_CPUFREQ - max_devfreq_index; + if (index_max > qos_request_value.max_state) + index_max = 0; + index_max = qos_request_value.max_state - index_max; + } else { + if (max_devfreq_index > qos_request_value.max_state) + index_max = qos_request_value.max_state; + } + if (min_devfreq_index & MASK_CPUFREQ) { + index_min = MAX_CPUFREQ - min_devfreq_index; + if (index_min > (qos_request_value.max_state-1)) + index_min = 0; + index_min = qos_request_value.max_state - 1 - index_min; + } else { + if (min_devfreq_index > qos_request_value.max_state) + index_min = qos_request_value.max_state - 1; + } + + qos_request_value.min_devfreq = index_min; + qos_request_value.max_devfreq = index_max; + + return NOTIFY_OK; +} +static struct notifier_block devfreq_qos_notifier = { + .notifier_call = devfreq_qos_handler, +}; + #define PROP_PORTS "qcom,src-dst-ports" #define PROP_ACTIVE "qcom,active-only" @@ -152,7 +247,13 @@ int devfreq_add_devbw(struct device *dev) p = &d->dp; p->polling_ms = 50; - p->target = devbw_target; + + if (strnstr(d->bw_data.name, "soc:qcom,cpu-cpu-llcc-bw", + strlen(d->bw_data.name)) != NULL) { + p->target = devbw_target_cpubw; + cpubw_flag = true; + } else + p->target = devbw_target; p->get_dev_status = devbw_get_dev_status; ret = dev_pm_opp_of_add_table(dev); @@ -174,6 +275,12 @@ int devfreq_add_devbw(struct device *dev) return PTR_ERR(d->df); } + if (cpubw_flag) { + cpubw_flag = false; + qos_request_value.max_state = p->max_state; + qos_request_value.min_devfreq = 0; + qos_request_value.max_devfreq = p->max_state; + } return 0; } @@ -221,10 +328,20 @@ static struct platform_driver devbw_driver = { .driver = { .name = "devbw", .of_match_table = devbw_match_table, + .owner = THIS_MODULE, .suppress_bind_attrs = true, }, }; -module_platform_driver(devbw_driver); +static int __init devbw_init(void) +{ + /* add cpufreq qos notify */ + cpubw_flag = false; + pm_qos_add_notifier(PM_QOS_DEVFREQ_MAX, &devfreq_qos_notifier); + pm_qos_add_notifier(PM_QOS_DEVFREQ_MIN, &devfreq_qos_notifier); + platform_driver_register(&devbw_driver); + return 0; +} +device_initcall(devbw_init); MODULE_DESCRIPTION("Device DDR bandwidth voting driver MSM SoCs"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/esoc/esoc-mdm-drv.c b/drivers/esoc/esoc-mdm-drv.c index 6b343fa57846a6832707a7cc2e1f094be29cfc68..3c64a2fb452e113cb0109fc692e30ea174cd376c 100644 --- a/drivers/esoc/esoc-mdm-drv.c +++ b/drivers/esoc/esoc-mdm-drv.c @@ -18,6 +18,7 @@ #include "esoc.h" #include "esoc-mdm.h" #include "mdm-dbg.h" +#include /* Default number of powerup trial requests per session */ #define ESOC_DEF_PON_REQ 2 @@ -39,6 +40,8 @@ module_param(boot_fail_action, uint, 0644); MODULE_PARM_DESC(boot_fail_action, "Actions: 0:Retry PON; 1:Cold reset; 2:Power-down; 3:APQ Panic; 4:No action"); +bool modem_5G_panic; + enum esoc_pon_state { PON_INIT, PON_SUCCESS, @@ -343,7 +346,10 @@ static int mdm_handle_boot_fail(struct esoc_clink *esoc_clink, u8 *pon_trial) break; case BOOT_FAIL_ACTION_PANIC: esoc_mdm_log("Calling panic!!\n"); - panic("Panic requested on external modem boot failure\n"); + if (get_second_board_absent() == 0) + panic("Panic requested on external modem boot failure\n"); + else + pr_err("Panic requested on external modem boot failure\n"); break; case BOOT_FAIL_ACTION_NOP: esoc_mdm_log("Leaving the modem in its curent state\n"); @@ -367,8 +373,10 @@ static int mdm_subsys_powerup(const struct subsys_desc *crashed_subsys) subsys); struct mdm_drv *mdm_drv = esoc_get_drv_data(esoc_clink); const struct esoc_clink_ops * const clink_ops = esoc_clink->clink_ops; + struct mdm_ctrl *mdm = get_esoc_clink_data(mdm_drv->esoc_clink); int timeout = INT_MAX; u8 pon_trial = 1; + modem_5G_panic = false; esoc_mdm_log("Powerup request from SSR\n"); @@ -438,11 +446,29 @@ static int mdm_subsys_powerup(const struct subsys_desc *crashed_subsys) "Boot failed. Doing cleanup and attempting to retry\n"); pon_trial++; mdm_subsys_retry_powerup_cleanup(esoc_clink); + if (!oem_get_download_mode()) { + pr_err("[MDM] DumpMode is disabled. Skip trigger 5G dump\n"); + } else { + pr_err("[MDM] Crash Trigger\n"); + modem_5G_panic = true; + } } else if (mdm_drv->pon_state == PON_SUCCESS) { break; } } while (pon_trial <= n_pon_tries); + //because two times powerup flow, make sure SDX50 is ready + pr_err("[MDM] Roland: check 5G dump gpio\n"); + if (gpio_get_value(MDM_GPIO(mdm, MDM2AP_STATUS)) == 1) { + pr_err("[MDM] gpio check pass, 5g flag [%d]\n", modem_5G_panic); + if (modem_5G_panic == true) { + pr_err("[MDM] Power done SDX50 and wait 5s\n"); + msleep(5000); + mdm_power_down(mdm); + panic("get the SDX50 dump"); // warm reset device + } + } + return 0; } diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig index a7bca4207f447a72caf33edd96327d0ecd811c0f..c844dd6637ef951d2fadfcea3fedc16a6b380a57 100644 --- a/drivers/extcon/Kconfig +++ b/drivers/extcon/Kconfig @@ -157,4 +157,17 @@ config EXTCON_USBC_CROS_EC Say Y here to enable USB Type C cable detection extcon support when using Chrome OS EC based USB Type-C ports. +config TRI_STATE_KEY + default n + tristate "switch Profiles by this triple key" + help + Say Y here if you want to enable the feature. + +config HALL_TRI_STATE_KEY + default n + tristate "switch Profiles by this triple key" + help + Say Y here if you want to enable the feature. endif + +source "drivers/extcon/hall_ic/Kconfig" diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile index 0888fdeded7230de9ca368e4af3efa3529451211..ad346e6a1a2e35e465cae299ecefda4f35d84c67 100644 --- a/drivers/extcon/Makefile +++ b/drivers/extcon/Makefile @@ -22,3 +22,6 @@ obj-$(CONFIG_EXTCON_RT8973A) += extcon-rt8973a.o obj-$(CONFIG_EXTCON_SM5502) += extcon-sm5502.o obj-$(CONFIG_EXTCON_USB_GPIO) += extcon-usb-gpio.o obj-$(CONFIG_EXTCON_USBC_CROS_EC) += extcon-usbc-cros-ec.o +obj-$(CONFIG_SENSOR_HALL_MXM1120) +=hall_ic/ +obj-$(CONFIG_TRI_STATE_KEY) += tri_state_key.o +obj-$(CONFIG_HALL_TRI_STATE_KEY) += oneplus_tri_key.o \ No newline at end of file diff --git a/drivers/extcon/hall_ic/Kconfig b/drivers/extcon/hall_ic/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..b6ce56cad6cebaef688e11875913bede08c8f271 --- /dev/null +++ b/drivers/extcon/hall_ic/Kconfig @@ -0,0 +1,5 @@ +config SENSOR_HALL_MXM1120 + tristate "digital hall m1120 Controler" + default n + help + Say Y here to enable m1120. \ No newline at end of file diff --git a/drivers/extcon/hall_ic/Makefile b/drivers/extcon/hall_ic/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..9f6752810ab3ab6841c541ffca56779fac71ff1d --- /dev/null +++ b/drivers/extcon/hall_ic/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for the touchscreen drivers. +# + +# Each configuration option enables a list of files. + +obj-$(CONFIG_SENSOR_HALL_MXM1120) += hall_mxm1120_up.o hall_mxm1120_down.o + +#obj-y += mxm1120_up.o mxm1120_down.o +#mxm1120_down.o + + + diff --git a/drivers/extcon/hall_ic/hall_mxm1120.h b/drivers/extcon/hall_ic/hall_mxm1120.h new file mode 100644 index 0000000000000000000000000000000000000000..8cf4509e69eb9a6cbf9276e094b3a4f4cf089441 --- /dev/null +++ b/drivers/extcon/hall_ic/hall_mxm1120.h @@ -0,0 +1,307 @@ +#ifndef __MXM1120_H__ +#define __MXM1120_H__ + +#include +#include + +/* ********************************************************* */ +/* feature of ic revision */ +/* ********************************************************* */ +#define M1120_REV_0_2 (0x02) +#define M1120_REV_1_0 (0x10) +#define M1120_REV M1120_REV_1_0 +#define M1120_DRIVER_VERSION "Ver1.04-140226" +/* ********************************************************* */ + +/* ********************************************************* */ +/* property of driver */ +/* ********************************************************* */ +#define M1120_DRIVER_NAME_UP "hall_m1120_up" +#define M1120_DRIVER_NAME_MIDDLE "m1120_middle" +#define M1120_DRIVER_NAME_DOWN "hall_m1120_down" +#define M1120_IRQ_NAME "m1120-irq" +#define M1120_PATH "/dev/m1120" + +/* +SAD1 SAD0 == 00 0001100 R/W (7bits)0x0C (8bits)0x18 +SAD1 SAD0 == 01 0001101 R/W (7bits)0x0D (8bits)0x1A +SAD1 SAD0 == 10 0001110 R/W (7bits)0x0E (8bits)0x1C +SAD1 SAD0 == 11 0001111 R/W (7bits)0x0F (8bits)0x1E +*/ +#define M1120_SLAVE_ADDR (0x18) +/* ********************************************************* */ + +/* ********************************************************* */ +/* register map */ +/* ********************************************************* */ +#define M1120_REG_PERSINT (0x00) +#define M1120_VAL_PERSINT_COUNT(n) (n<<4) +#define M1120_VAL_PERSINT_INTCLR (0x01) + /* + [7:4] PERS : interrupt persistence count + [0] INTCLR = 1 : interrupt clear + */ +/* --------------------------------------------------------- */ +#define M1120_REG_INTSRS (0x01) +#define M1120_VAL_INTSRS_INT_ON (0x80) +#define M1120_DETECTION_MODE_INTERRUPT M1120_VAL_INTSRS_INT_ON +#define M1120_VAL_INTSRS_INT_OFF (0x00) +#define M1120_DETECTION_MODE_POLLING M1120_VAL_INTSRS_INT_OFF +#define M1120_VAL_INTSRS_INTTYPE_BESIDE (0x00) +#define M1120_VAL_INTSRS_INTTYPE_WITHIN (0x10) +#define M1120_VAL_INTSRS_SRS_10BIT_0_068mT (0x00) +#define M1120_VAL_INTSRS_SRS_10BIT_0_034mT (0x01) +#define M1120_VAL_INTSRS_SRS_10BIT_0_017mT (0x02) +#define M1120_VAL_INTSRS_SRS_10BIT_0_009mT (0x03) +#define M1120_VAL_INTSRS_SRS_10BIT_0_004mT (0x04) +#define M1120_VAL_INTSRS_SRS_8BIT_0_272mT (0x00) +#define M1120_VAL_INTSRS_SRS_8BIT_0_136mT (0x01) +#define M1120_VAL_INTSRS_SRS_8BIT_0_068mT (0x02) +#define M1120_VAL_INTSRS_SRS_8BIT_0_036mT (0x03) +#define M1120_VAL_INTSRS_SRS_8BIT_0_016mT (0x04) + /* + [7] INTON = 0 : disable interrupt + [7] INTON = 1 : enable interrupt + [4] INT_TYP = 0 : generate interrupt when raw data is beside range of threshold + [4] INT_TYP = 1 : generate interrupt when raw data is within range of threshold + [2:0] SRS : select sensitivity type when M1120_VAL_OPF_BIT_10 + 000 : 0.068 (mT/LSB) + 001 : 0.034 (mT/LSB) + 010 : 0.017 (mT/LSB) + 011 : 0.009 (mT/LSB) + 100 : 0.004 (mT/LSB) + 101 : 0.017 (mT/LSB) + 110 : 0.017 (mT/LSB) + 111 : 0.017 (mT/LSB) + [2:0] SRS : select sensitivity type when M1120_VAL_OPF_BIT_8 + 000 : 0.272 (mT/LSB) + 001 : 0.136 (mT/LSB) + 010 : 0.068 (mT/LSB) + 011 : 0.036 (mT/LSB) + 100 : 0.016 (mT/LSB) + 101 : 0.068 (mT/LSB) + 110 : 0.068 (mT/LSB) + 111 : 0.068 (mT/LSB) + */ +/* --------------------------------------------------------- */ +#define M1120_REG_LTHL (0x02) + /* + [7:0] LTHL : low byte of low threshold value + */ +/* --------------------------------------------------------- */ +#define M1120_REG_LTHH (0x03) + /* + [7:6] LTHH : high 2bits of low threshold value with sign + */ +/* --------------------------------------------------------- */ +#define M1120_REG_HTHL (0x04) + /* + [7:0] HTHL : low byte of high threshold value + */ +/* --------------------------------------------------------- */ +#define M1120_REG_HTHH (0x05) + /* + [7:6] HTHH : high 2bits of high threshold value with sign + */ +/* --------------------------------------------------------- */ +#define M1120_REG_I2CDIS (0x06) +#define M1120_VAL_I2CDISABLE (0x37) + /* + [7:0] I2CDIS : disable i2c + */ +/* --------------------------------------------------------- */ +#define M1120_REG_SRST (0x07) +#define M1120_VAL_SRST_RESET (0x01) + /* + [0] SRST = 1 : soft reset + */ +/* --------------------------------------------------------- */ +#define M1120_REG_OPF (0x08) +#define M1120_VAL_OPF_FREQ_20HZ (0x00) +#define M1120_VAL_OPF_FREQ_10HZ (0x10) +#define M1120_VAL_OPF_FREQ_6_7HZ (0x20) +#define M1120_VAL_OPF_FREQ_5HZ (0x30) +#define M1120_VAL_OPF_FREQ_80HZ (0x40) +#define M1120_VAL_OPF_FREQ_40HZ (0x50) +#define M1120_VAL_OPF_FREQ_26_7HZ (0x60) +#define M1120_VAL_OPF_EFRD_ON (0x08) +#define M1120_VAL_OPF_BIT_8 (0x02) +#define M1120_VAL_OPF_BIT_10 (0x00) +#define M1120_VAL_OPF_HSSON_ON (0x01) +#define M1120_VAL_OPF_HSSON_OFF (0x00) + /* + [6:4] OPF : operation frequency + 000 : 20 (Hz) + 001 : 10 (Hz) + 010 : 6.7 (Hz) + 011 : 5 (Hz) + 100 : 80 (Hz) + 101 : 40 (Hz) + 110 : 26.7 (Hz) + 111 : 20 (Hz) + [3] EFRD = 0 : keep data without accessing eFuse + [3] EFRD = 1 : update data after accessing eFuse + [1] BIT = 0 : 10 bit resolution + [1] BIT = 1 : 8 bit resolution + [0] HSSON = 0 : Off power down mode + [0] HSSON = 1 : On power down mode + + */ +/* --------------------------------------------------------- */ +#define M1120_REG_DID (0x09) +#define M1120_VAL_DID (0x9C) + /* + [7:0] DID : Device ID + */ +/* --------------------------------------------------------- */ +#define M1120_REG_INFO (0x0A) + /* + [7:0] INFO : Information about IC + */ +/* --------------------------------------------------------- */ +#define M1120_REG_ASA (0x0B) + /* + [7:0] ASA : Hall Sensor sensitivity adjustment + */ +/* --------------------------------------------------------- */ +#define M1120_REG_ST1 (0x10) +#define M1120_VAL_ST1_DRDY (0x01) + /* + [4] INTM : status of interrupt mode + [1] BITM : status of resolution + [0] DRDY : status of data ready + */ +/* --------------------------------------------------------- */ +#define M1120_REG_HSL (0x11) + /* + [7:0] HSL : low byte of hall sensor measurement data + */ +/* --------------------------------------------------------- */ +#define M1120_REG_HSH (0x12) + /* + [7:6] HSL : high 2bits of hall sensor measurement data with sign + */ +/* ********************************************************* */ + + +/* ********************************************************* */ + + +/* ********************************************************* */ +/* ioctl command */ +/* ********************************************************* */ +#define M1120_IOCTL_BASE (0x80) +#define M1120_IOCTL_SET_ENABLE _IOW(M1120_IOCTL_BASE, 0x00, int) +#define M1120_IOCTL_GET_ENABLE _IOR(M1120_IOCTL_BASE, 0x01, int) +#define M1120_IOCTL_SET_DELAY _IOW(M1120_IOCTL_BASE, 0x02, int) +#define M1120_IOCTL_GET_DELAY _IOR(M1120_IOCTL_BASE, 0x03, int) +#define M1120_IOCTL_SET_CALIBRATION _IOW(M1120_IOCTL_BASE, 0x04, int*) +#define M1120_IOCTL_GET_CALIBRATED_DATA _IOR(M1120_IOCTL_BASE, 0x05, int*) +#define M1120_IOCTL_SET_INTERRUPT _IOW(M1120_IOCTL_BASE, 0x06, unsigned int) +#define M1120_IOCTL_GET_INTERRUPT _IOR(M1120_IOCTL_BASE, 0x07, unsigned int*) +#define M1120_IOCTL_SET_THRESHOLD_HIGH _IOW(M1120_IOCTL_BASE, 0x08, unsigned int) +#define M1120_IOCTL_GET_THRESHOLD_HIGH _IOR(M1120_IOCTL_BASE, 0x09, unsigned int*) +#define M1120_IOCTL_SET_THRESHOLD_LOW _IOW(M1120_IOCTL_BASE, 0x0A, unsigned int) +#define M1120_IOCTL_GET_THRESHOLD_LOW _IOR(M1120_IOCTL_BASE, 0x0B, unsigned int*) +#define M1120_IOCTL_SET_REG _IOW(M1120_IOCTL_BASE, 0x0C, int) +#define M1120_IOCTL_GET_REG _IOR(M1120_IOCTL_BASE, 0x0D, int) +/* ********************************************************* */ + + +/* ********************************************************* */ +/* event property */ +/* ********************************************************* */ +#define DEFAULT_EVENT_TYPE EV_ABS +#define DEFAULT_EVENT_CODE ABS_X +#define DEFAULT_EVENT_DATA_CAPABILITY_MIN (-32768) +#define DEFAULT_EVENT_DATA_CAPABILITY_MAX (32767) +/* ********************************************************* */ +/* delay property */ +/* ********************************************************* */ +#define M1120_DELAY_MAX (200) // ms +#define M1120_DELAY_MIN (20) // ms +#define M1120_DELAY_FOR_READY (10) // ms +/* ********************************************************* */ + + +/* ********************************************************* */ +/* data type for driver */ +/* ********************************************************* */ + +enum { + OPERATION_MODE_POWERDOWN, + OPERATION_MODE_MEASUREMENT, + OPERATION_MODE_FUSEROMACCESS +}; + +#define M1120_REG_NUM (15) +typedef union { + struct { + unsigned char persint; + unsigned char intsrs; + unsigned char lthl; + unsigned char lthh; + unsigned char hthl; + unsigned char hthh; + unsigned char i2cdis; + unsigned char srst; + unsigned char opf; + unsigned char did; + unsigned char info; + unsigned char asa; + unsigned char st1; + unsigned char hsl; + unsigned char hsh; + } map; + unsigned char array[M1120_REG_NUM]; +} m1120_reg_t; + +typedef struct { + struct mutex enable; + struct mutex data; +} m1120_mutex_t; + +typedef struct { + atomic_t enable; + atomic_t delay; + atomic_t debug; +} m1120_atomic_t; + +typedef struct { + int power_vi2c; + int power_vdd; + int interrupt_gpio; + int interrupt_irq; +} m1120_platform_data_t; + +typedef struct { + struct i2c_client *client; + struct input_dev *input_dev; + m1120_mutex_t mtx; + m1120_atomic_t atm; + m1120_reg_t reg; + bool irq_enabled; + int calibrated_data; + int last_data; + short thrhigh; + short thrlow; + bool irq_first; + + struct delayed_work work; + + int power_vi2c; + int power_vdd; + int igpio; + int int_en; + int irq; + int irq_gpio; + int use_hrtimer; + struct regulator *vdd; + struct regulator *vio; + int power_enabled; + +} m1120_data_t; +/* ********************************************************* */ + +#endif // __MXM1120_H__ + diff --git a/drivers/extcon/hall_ic/hall_mxm1120_down.c b/drivers/extcon/hall_ic/hall_mxm1120_down.c new file mode 100644 index 0000000000000000000000000000000000000000..42c24b656fd1d86bb5740ae3a9098af7970115be --- /dev/null +++ b/drivers/extcon/hall_ic/hall_mxm1120_down.c @@ -0,0 +1,1473 @@ +/* + * m1120.c - Linux kernel modules for hall switch + * + * Copyright (C) 2013 Seunghwan Park + * Copyright (C) 2014 MagnaChip Semiconductor. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "hall_mxm1120.h" +#include "../oneplus_tri_key.h" + +//i2c address : 0X0D + +/***********************************************************/ +/*customer config*/ +/***********************************************************/ +#define M1120_DBG_ENABLE // for debugging +#define M1120_DETECTION_MODE M1120_DETECTION_MODE_INTERRUPT/*M1120_DETECTION_MODE_POLLING /James*/ +#define M1120_INTERRUPT_TYPE M1120_VAL_INTSRS_INTTYPE_BESIDE +//#define M1120_INTERRUPT_TYPE M1120_VAL_INTSRS_INTTYPE_WITHIN +#define M1120_SENSITIVITY_TYPE M1120_VAL_INTSRS_SRS_10BIT_0_068mT +#define M1120_PERSISTENCE_COUNT M1120_VAL_PERSINT_COUNT(15) +#define M1120_OPERATION_FREQUENCY M1120_VAL_OPF_FREQ_80HZ +#define M1120_OPERATION_RESOLUTION M1120_VAL_OPF_BIT_10 +#define M1120_DETECT_RANGE_HIGH (60)/*Need change via test.*/ +#define M1120_DETECT_RANGE_LOW (50)/*Need change via test.*/ +#define M1120_RESULT_STATUS_A (0x01) // result status A ----> ==180Degree. +#define M1120_RESULT_STATUS_B (0x02) // result status B ----> != 180Degree. +#define M1120_EVENT_TYPE EV_ABS // EV_KEY +#define M1120_EVENT_CODE ABS_X // KEY_F1 +#define M1120_EVENT_DATA_CAPABILITY_MIN (-32768) +#define M1120_EVENT_DATA_CAPABILITY_MAX (32767) + +/*MagnaChip Hall Sensor power supply VDD 2.7V~3.6V, VIO 1.65~VDD*/ +#define M1120_VDD_MIN_UV 2700000 +#define M1120_VDD_MAX_UV 3600000 +#define M1120_VIO_MIN_UV 1650000 +#define M1120_VIO_MAX_UV 3600000 + +/***********************************************************/ +/*debug macro*/ +/***********************************************************/ +#ifdef M1120_DBG_ENABLE +#define dbg(fmt, args...) printk("[M1120-DBG] %s(L%04d) : " fmt "\n", __func__, __LINE__, ##args) +#define dbgn(fmt, args...) printk(fmt, ##args) +#else +#define dbg(fmt, args...) +#define dbgn(fmt, args...) +#endif // M1120_DBG_ENABLE +#define dbg_func_in() dbg("[M1120-DBG-F.IN] %s", __func__) +#define dbg_func_out() dbg("[M1120-DBG-F.OUT] %s", __func__) +#define dbg_line() dbg("[LINE] %d(%s)", __LINE__, __func__) +/***********************************************************/ + + +/***********************************************************/ +/*error display macro*/ +/***********************************************************/ +#define mxerr(pdev, fmt, args...) \ + dev_err(pdev, "[M1120-ERR] %s(L%04d) : " fmt "\n", __func__, __LINE__, ##args) +#define mxinfo(pdev, fmt, args...) \ + dev_info(pdev, "[M1120-INFO] %s(L%04d) : " fmt "\n", __func__, __LINE__, ##args) +/***********************************************************/ + +/***********************************************************/ +/*static variable*/ +/***********************************************************/ +static m1120_data_t *p_m1120_data; +/***********************************************************/ + + +/***********************************************************/ +/*function protyps*/ +/***********************************************************/ +/*i2c interface*/ +static int m1120_i2c_read_block(m1120_data_t* m1120_data, u8 addr, u8 *data, u8 len); +static int m1120_i2c_write_block(m1120_data_t* m1120_data, u8 addr, u8 *data, u8 len); +static void m1120_short_to_2byte(m1120_data_t* m1120_data, short x, u8 *hbyte, u8 *lbyte); +static short m1120_2byte_to_short(m1120_data_t* m1120_data, u8 hbyte, u8 lbyte); +/*vdd / vid power control*/ +static int m1120_set_power(struct device *dev, bool on); + + +static int m1120_get_enable(struct device *dev); +static void m1120_set_enable(struct device *dev, int enable); +static int m1120_get_delay(struct device *dev); +static void m1120_set_delay(struct device *dev, int delay); +static int m1120_get_debug(struct device *dev); +static void m1120_set_debug(struct device *dev, int debug); +static int m1120_clear_interrupt(struct device *dev); +static int m1120_set_operation_mode(struct device *dev, int mode); +static int m1120_init_device(struct device *dev); +static int m1120_reset_device(struct device *dev); +static int m1120_power_ctl(m1120_data_t *data, bool on); +static int m1120_get_data( short *data); +/***********************************************************/ + + +/***********************************************************/ +/*functions for i2c interface*/ +/***********************************************************/ +#define M1120_I2C_BUF_SIZE (17) + + +static int m1120_i2c_read_block(m1120_data_t* m1120_data, u8 addr, u8 *data, u8 len) +{ + u8 reg_addr = addr; + int err = 0; + struct i2c_client *client = NULL; + struct i2c_msg msgs[2]={{0},{0}}; + + if (!m1120_data) { + MOTOR_ERR("m1120_data == NULL\n"); + return -EINVAL; + } + client = m1120_data->client; + + if (!client) { + MOTOR_ERR("client null\n"); + return -EINVAL; + } else if (len >= M1120_I2C_BUF_SIZE) { + MOTOR_ERR(" length %d exceeds %d\n", len, M1120_I2C_BUF_SIZE); + return -EINVAL; + } + //mutex_lock(&m1120_i2c_mutex); Ëø¾ßÌåÔõôÀ´ÓÃ,µÈºóÃæÔÙ¿´,ÏÈ×¢Ê͵ô + + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len =1; + msgs[0].buf = ®_addr; + + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len =len; + msgs[1].buf = data; + + err = i2c_transfer(client->adapter, msgs, (sizeof(msgs) / sizeof(msgs[0]))); + + if (err < 0) { + MOTOR_ERR("i2c_transfer error: (%d %p %d) %d\n",addr, data, len, err); + err = -EIO; + } else { + err = 0; + } + //mutex_unlock(&m1120_i2c_mutex); + + return err; + +} + +static int m1120_i2c_write_block(m1120_data_t* m1120_data, u8 addr, u8 *data, u8 len) +{ + int err = 0; + int idx = 0; + int num = 0; + char buf[M1120_I2C_BUF_SIZE] ={0}; + struct i2c_client *client = NULL; + + if (!m1120_data) { + MOTOR_ERR("m1120_data == NULL\n"); + return -EINVAL; + } + client = m1120_data->client; + + if (!client) { + MOTOR_ERR("client null\n"); + return -EINVAL; + } else if (len >= M1120_I2C_BUF_SIZE) { + MOTOR_ERR(" length %d exceeds %d\n", len, M1120_I2C_BUF_SIZE); + return -EINVAL; + } + + //mutex_lock(&m1120_i2c_mutex); + + buf[num++] = addr; + for (idx = 0; idx < len; idx++) { + buf[num++] = data[idx]; + } + + err = i2c_master_send(client, buf, num); + if (err < 0) { + MOTOR_ERR("send command error!! %d\n",err); + } + + //store reg written + if (len == 1) { + switch(addr){ + case M1120_REG_PERSINT: + m1120_data->reg.map.persint = data[0]; + break; + case M1120_REG_INTSRS: + m1120_data->reg.map.intsrs = data[0]; + break; + case M1120_REG_LTHL: + m1120_data->reg.map.lthl = data[0]; + break; + case M1120_REG_LTHH: + m1120_data->reg.map.lthh = data[0]; + break; + case M1120_REG_HTHL: + m1120_data->reg.map.hthl = data[0]; + break; + case M1120_REG_HTHH: + m1120_data->reg.map.hthh = data[0]; + break; + case M1120_REG_I2CDIS: + m1120_data->reg.map.i2cdis = data[0]; + break; + case M1120_REG_SRST: + m1120_data->reg.map.srst = data[0]; + break; + case M1120_REG_OPF: + m1120_data->reg.map.opf = data[0]; + break; + } + } + + //mutex_unlock(&m1120_i2c_mutex); + return err; +} + +static void m1120_short_to_2byte(m1120_data_t* m1120_data, short x, u8 *hbyte, u8 *lbyte) +{ + if (!m1120_data) { + MOTOR_ERR("m1120_data == NULL\n"); + return ; + } + + if ((m1120_data->reg.map.opf & M1120_VAL_OPF_BIT_8) == M1120_VAL_OPF_BIT_8) { + /* 8 bit resolution */ + if (x < -128) { + x = -128; + } else if(x > 127) { + x = 127; + } + + if (x >= 0) { + *lbyte = x & 0x7F; + } else { + *lbyte = ( (0x80 - (x*(-1))) & 0x7F ) | 0x80; + } + *hbyte = 0x00; + } else { + /* 10 bit resolution */ + if (x < -512) { + x = -512; + } else if (x > 511) { + x = 511; + } + + if (x >=0 ) { + *lbyte = x & 0xFF; + *hbyte = (((x & 0x100) >> 8) & 0x01) << 6; + } else { + *lbyte = (0x0200 - (x*(-1))) & 0xFF; + *hbyte = ((((0x0200 - (x*(-1))) & 0x100) >> 8) << 6) | 0x80; + } + } +} + + +static short m1120_2byte_to_short(m1120_data_t* m1120_data, u8 hbyte, u8 lbyte) +{ + short x = 0; + + if (!m1120_data) { + MOTOR_ERR("m1120_data == NULL\n"); + return -EINVAL; + } + + if( (m1120_data->reg.map.opf & M1120_VAL_OPF_BIT_8) == M1120_VAL_OPF_BIT_8) { + /* 8 bit resolution */ + x = lbyte & 0x7F; + if (lbyte & 0x80) { + x -= 0x80; + } + } else { + /* 10 bit resolution */ + x = ( ( (hbyte & 0x40) >> 6) << 8 ) | lbyte; + if (hbyte & 0x80) { + x -= 0x200; + } + } + + return x; +} + +/***********************************************************/ + + + +/***********************************************************/ +/*vdd / vid power control*/ +/***********************************************************/ +static int m1120_set_power(struct device *dev, bool on) +{ + m1120_power_ctl(p_m1120_data, on); + + return 0; +} +/***********************************************************/ + + +static irqreturn_t m1120_down_irq_handler(int irq, void *dev_id) +{ + MOTOR_LOG("call \n"); + + if (!p_m1120_data) { + MOTOR_LOG("p_m1120_data NULL \n"); + return -EINVAL; + } + + disable_irq_nosync(p_m1120_data->irq); + oneplus_hall_irq_handler(1);//DHALL_1 DHALL_DOWN + + return IRQ_HANDLED; +} + + +static int m1120_get_enable(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + m1120_data_t *p_data = i2c_get_clientdata(client); + + return atomic_read(&p_data->atm.enable); +} + + +static void m1120_set_enable(struct device *dev, int enable) +{ + struct i2c_client *client = to_i2c_client(dev); + m1120_data_t *p_data = i2c_get_clientdata(client); +// int delay = m1120_get_delay(dev); + + mutex_lock(&p_data->mtx.enable); + MOTOR_LOG("enable : %d\n", enable); + if (enable) { /*enable if state will be changed*/ + if (!atomic_cmpxchg(&p_data->atm.enable, 0, 1)) { + //m1120_set_detection_mode(dev, p_data->reg.map.intsrs & M1120_DETECTION_MODE_INTERRUPT); + //m1120_set_detection_mode(dev, p_data->reg.map.intsrs & M1120_DETECTION_MODE_POLLING); + m1120_set_operation_mode(&p_m1120_data->client->dev, OPERATION_MODE_MEASUREMENT); + /*if(!(p_data->reg.map.intsrs & M1120_DETECTION_MODE_INTERRUPT))*/ + // if (0) { + // schedule_delayed_work(&p_data->work, msecs_to_jiffies(delay)); + // } + } + } else { /*disable if state will be changed*/ + if (atomic_cmpxchg(&p_data->atm.enable, 1, 0)) { + //cancel_delayed_work_sync(&p_data->work); + m1120_set_operation_mode(&p_m1120_data->client->dev, OPERATION_MODE_POWERDOWN); + } + } + atomic_set(&p_data->atm.enable, enable); + + mutex_unlock(&p_data->mtx.enable); +} + +static int m1120_get_delay(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + m1120_data_t *p_data = i2c_get_clientdata(client); + + int delay = 0; + + delay = atomic_read(&p_data->atm.delay); + + return delay; +} + +static void m1120_set_delay(struct device *dev, int delay) +{ + struct i2c_client *client = to_i2c_client(dev); + m1120_data_t *p_data = i2c_get_clientdata(client); + + if (delay < M1120_DELAY_MIN) + delay = M1120_DELAY_MIN; + atomic_set(&p_data->atm.delay, delay); + + mutex_lock(&p_data->mtx.enable); + + if (m1120_get_enable(dev)) { + if (!(p_data->reg.map.intsrs & M1120_DETECTION_MODE_INTERRUPT)) { + cancel_delayed_work_sync(&p_data->work); + schedule_delayed_work(&p_data->work, msecs_to_jiffies(delay)); + } + } + + mutex_unlock(&p_data->mtx.enable); +} + +static int m1120_get_debug(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + m1120_data_t *p_data = i2c_get_clientdata(client); + + return atomic_read(&p_data->atm.debug); +} + +static void m1120_set_debug(struct device *dev, int debug) +{ + struct i2c_client *client = to_i2c_client(dev); + m1120_data_t *p_data = i2c_get_clientdata(client); + + atomic_set(&p_data->atm.debug, debug); +} + +static int m1120_clear_interrupt(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + m1120_data_t *p_data = i2c_get_clientdata(client); + int ret = 0; + u8 data = 0x00; + + data = p_data->reg.map.persint | 0x01; + ret = m1120_i2c_write_block(p_data, M1120_REG_PERSINT, &data,1); + + return ret; +} + +static int m1120_set_operation_mode(struct device *dev, int mode) +{ + struct i2c_client *client = to_i2c_client(dev); + m1120_data_t *p_data = i2c_get_clientdata(client); + u8 opf = p_data->reg.map.opf; + int err = -1; + + switch (mode) { + case OPERATION_MODE_POWERDOWN: + opf &= (0xFF - M1120_VAL_OPF_HSSON_ON); + err = m1120_i2c_write_block(p_data, M1120_REG_OPF, &opf, 1); + mxinfo(&client->dev, "operation mode was chnaged to OPERATION_MODE_POWERDOWN"); + break; + case OPERATION_MODE_MEASUREMENT: + opf &= (0xFF - M1120_VAL_OPF_EFRD_ON); + opf |= M1120_VAL_OPF_HSSON_ON; + err = m1120_i2c_write_block(p_data, M1120_REG_OPF, &opf, 1); + + mxinfo(&client->dev, "operation mode was chnaged to OPERATION_MODE_MEASUREMENT"); + break; + case OPERATION_MODE_FUSEROMACCESS: + opf |= M1120_VAL_OPF_EFRD_ON; + opf |= M1120_VAL_OPF_HSSON_ON; + err = m1120_i2c_write_block(p_data, M1120_REG_OPF, &opf, 1); + mxinfo(&client->dev, "operation mode was chnaged to OPERATION_MODE_FUSEROMACCESS"); + break; + } + mxinfo(&client->dev, "opf = ox%x \n", opf); + return err; +} + +static int m1120_init_device(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + m1120_data_t *p_data = i2c_get_clientdata(client); + int err = -1; + + /*(1) vdd and vid power up*/ + err = m1120_set_power(dev, 1); + if (err) { + mxerr(&client->dev, "m1120 power-on was failed (%d)", err); + return err; + } + + /*(2) init variables*/ + atomic_set(&p_data->atm.enable, 0); + atomic_set(&p_data->atm.delay, M1120_DELAY_MIN); +#ifdef M1120_DBG_ENABLE + atomic_set(&p_data->atm.debug, 1); +#else + atomic_set(&p_data->atm.debug, 0); +#endif + p_data->calibrated_data = 0; + p_data->last_data = 0; + p_data->irq_enabled = 0; + p_data->irq_first = 1; + p_data->thrhigh = M1120_DETECT_RANGE_HIGH; + p_data->thrlow = M1120_DETECT_RANGE_LOW; + m1120_set_delay(&client->dev, M1120_DELAY_MAX); + m1120_set_debug(&client->dev, 0); + + /*(3) reset registers*/ + err = m1120_reset_device(dev); + if (err < 0) { + mxerr(&client->dev, "m1120_reset_device was failed (%d)", err); + return err; + } + + mxinfo(&client->dev, "initializing device was success"); + + return 0; +} + +static int m1120_reset_device(struct device *dev) +{ + int err = 0; + u8 id = 0xFF, data = 0x00; + + struct i2c_client *client = to_i2c_client(dev); + m1120_data_t *p_data = i2c_get_clientdata(client); + + if ((p_data == NULL) || (p_data->client == NULL)) + return -ENODEV; + + /*(1) sw reset*/ + data = M1120_VAL_SRST_RESET; + err = m1120_i2c_write_block(p_data, M1120_REG_SRST, &data,1); + if (err < 0) { + mxerr(&client->dev, "sw-reset was failed(%d)", err); + return err; + } + msleep(5); + dbg("wait 5ms after vdd power up"); + + /*(2) check id*/ + err = m1120_i2c_read_block(p_data, M1120_REG_DID, &id, 1); + if (err < 0) + return err; + if (id != M1120_VAL_DID) { + mxerr(&client->dev, "current device id(0x%02X) is not M1120 device id(0x%02X)", id, M1120_VAL_DID); + return -ENXIO; + } + + /*(3) init variables*/ + /*(3-1) persint*/ + data = M1120_PERSISTENCE_COUNT; + err = m1120_i2c_write_block(p_data, M1120_REG_PERSINT, &data,1); + if (err <0) { + mxerr(&client->dev, "cm1120_i2c_write_block error, data : %d", data); + return err; + } + /*(3-2) intsrs*/ + data = M1120_DETECTION_MODE | M1120_SENSITIVITY_TYPE; + if (data & M1120_DETECTION_MODE_INTERRUPT) { + data |= M1120_INTERRUPT_TYPE; + } + err = m1120_i2c_write_block(p_data, M1120_REG_INTSRS, &data, 1); + if (err < 0) { + mxerr(&client->dev, "cm1120_i2c_write_block error, data : %d", data); + return err; + } + /*(3-3) opf*/ + data = M1120_OPERATION_FREQUENCY | M1120_OPERATION_RESOLUTION; + err = m1120_i2c_write_block(p_data, M1120_REG_OPF, &data, 1); + if (err < 0) { + mxerr(&client->dev, "cm1120_i2c_write_block error, data : %d", data); + return err; + } + + /*(4) write variable to register*/ + // err = m1120_set_detection_mode(dev, M1120_DETECTION_MODE); + // if (err) { + // mxerr(&client->dev, "m1120_set_detection_mode was failed(%d)", err); + // return err; + // } + + + /*(5) set power-on mode*/ + err = m1120_set_operation_mode(dev, OPERATION_MODE_MEASUREMENT); + if (err < 0) { + mxerr(&client->dev, "m1120_set_detection_mode was failed(%d)", err); + return err; + } + + return err; +} + +/************************************************** + input device interface + **************************************************/ +static int m1120_input_dev_init(m1120_data_t *p_data) +{ + struct input_dev *dev; + int err; + + dev = input_allocate_device(); + if (!dev) { + return -ENOMEM; + } + dev->name = M1120_DRIVER_NAME_DOWN; + dev->id.bustype = BUS_I2C; + +#if (M1120_EVENT_TYPE == EV_ABS) + input_set_drvdata(dev, p_data); + input_set_capability(dev, M1120_EVENT_TYPE, ABS_MISC); + input_set_abs_params(dev, M1120_EVENT_CODE, M1120_EVENT_DATA_CAPABILITY_MIN, M1120_EVENT_DATA_CAPABILITY_MAX, 0, 0); +#elif (M1120_EVENT_TYPE == EV_KEY) + input_set_drvdata(dev, p_data); + input_set_capability(dev, M1120_EVENT_TYPE, M1120_EVENT_CODE); +#else +#error ("[ERR] M1120_EVENT_TYPE is not defined.") +#endif + + err = input_register_device(dev); + if (err < 0) { + input_free_device(dev); + return err; + } + + p_data->input_dev = dev; + + return 0; +} + +static void m1120_input_dev_terminate(m1120_data_t *p_data) +{ + struct input_dev *dev = p_data->input_dev; + + input_unregister_device(dev); + input_free_device(dev); +} + +/************************************************** + sysfs attributes + **************************************************/ +static ssize_t m1120_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return snprintf(buf, 20, "%d\n", m1120_get_enable(dev)); +} + +static ssize_t m1120_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + unsigned long enable = simple_strtoul(buf, NULL, 10); + + if ((enable == 0) || (enable == 1)) { + m1120_set_enable(dev, enable); + } + + return count; +} + +static ssize_t m1120_delay_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return snprintf(buf, 20, "%d\n", m1120_get_delay(dev)); +} + +static ssize_t m1120_delay_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + unsigned long delay = simple_strtoul(buf, NULL, 10); + + if (delay > M1120_DELAY_MAX) { + delay = M1120_DELAY_MAX; + } + + m1120_set_delay(dev, delay); + + return count; +} + +static ssize_t m1120_debug_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return snprintf(buf, 20, "%d\n", m1120_get_debug(dev)); +} + +static ssize_t m1120_debug_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + unsigned long debug = simple_strtoul(buf, NULL, 10); + + m1120_set_debug(dev, debug); + + return count; +} + +static ssize_t m1120_wake_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + return 0; +} + +static ssize_t m1120_data_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + //struct i2c_client *client = to_i2c_client(dev); + //m1120_data_t *p_data = i2c_get_clientdata(client); + short raw = 0; + m1120_get_data(&raw); + return snprintf(buf, 10, "%d\n", raw); +} + + static int m1120_i2c_read(struct i2c_client *client, u8 reg, u8 *rdata, u8 len) +{ +#if 0////add by James. + int rc; + struct i2c_msg msg[] = { + { + .addr = client->addr, + .flags = 0, + .len = 1, + .buf = ®, + }, + { + .addr = client->addr, + .flags = I2C_M_RD, + .len = len, + .buf = rdata, + }, + }; + if (client == NULL) { + mxerr(&client->dev, "client is NULL"); + return -ENODEV; + } + rc = i2c_transfer(client->adapter, msg, 2); + if (rc < 0) { + mxerr(&client->dev, "i2c_transfer was failed(%d)", rc); + return rc; + } +#else +/*Add By James for i2c_smbus_read_i2c_block_data */ + i2c_smbus_read_i2c_block_data(client, reg, len, rdata); +#endif + return 0; +} + +static int m1120_i2c_get_reg(struct i2c_client *client, u8 reg, u8 *rdata) +{ + return m1120_i2c_read(client, reg, rdata, 1); +} + +static void m1120_get_reg(struct device *dev, int *regdata) +{ + struct i2c_client *client = to_i2c_client(dev); + int err; + u8 rega = (((*regdata) >> 8) & 0xFF); + u8 regd = 0; + err = m1120_i2c_get_reg(client, rega, ®d); + *regdata = 0; + *regdata |= (err == 0) ? 0x0000 : 0xFF00; + *regdata |= regd; +} + +static ssize_t m1120_dump_show(struct device *dev,struct device_attribute *attr, char *buf) +{ + int reg = 0; + int reg_l = M1120_REG_HSL; + int reg_h = M1120_REG_HSH; + int i = 0; + for (i = 0; i < 11; i++) { + reg = i<<8; + m1120_get_reg(&p_m1120_data->client->dev, ®); + printk(KERN_ERR"dkk: the reg 0x%02X value: 0x%02X\n", i, reg); + } + m1120_get_reg(&p_m1120_data->client->dev, ®_l); + printk(KERN_ERR"dkk: the reg_l is 0x%02X\n", (u8)(reg_l&0xFF)); + m1120_get_reg(&p_m1120_data->client->dev, ®_h); + printk(KERN_ERR"dkk: the reg_h is 0x%02X", (u8)(reg_h&0xFF)); + reg = ((reg_h&0xC0) << 2)|reg_l; + printk(KERN_ERR"dkk: the down hall reg measure is 0x%02X\n", reg); + return snprintf(buf, 10, "%d\n", reg); + //return 0; +} + + +static DEVICE_ATTR(enable, S_IRUGO|S_IWUSR|S_IWGRP, m1120_enable_show, m1120_enable_store); +static DEVICE_ATTR(delay, S_IRUGO|S_IWUSR|S_IWGRP, m1120_delay_show, m1120_delay_store); +static DEVICE_ATTR(debug, S_IRUGO|S_IWUSR|S_IWGRP, m1120_debug_show, m1120_debug_store); +static DEVICE_ATTR(wake, S_IWUSR|S_IWGRP, NULL, m1120_wake_store); +static DEVICE_ATTR(rawdata, S_IRUGO|S_IWUSR|S_IWGRP, m1120_data_show, NULL); +static DEVICE_ATTR(dump, S_IRUGO|S_IWUSR|S_IWGRP, m1120_dump_show, NULL); + +static struct attribute *m1120_attributes[] = { + &dev_attr_enable.attr, + &dev_attr_delay.attr, + &dev_attr_debug.attr, + &dev_attr_wake.attr, + &dev_attr_rawdata.attr, + &dev_attr_dump.attr, + NULL +}; + +static struct attribute_group m1120_attribute_group = { + .attrs = m1120_attributes +}; + +static int m1120_power_ctl(m1120_data_t *data, bool on) +{ + int ret = 0; + int err = 0; + if (!on && data->power_enabled) { + ret = regulator_disable(data->vdd); + if (ret) { + dev_err(&data->client->dev, + "Regulator vdd disable failed ret=%d\n", ret); + return ret; + } + + ret = regulator_disable(data->vio); + if (ret) { + dev_err(&data->client->dev, + "Regulator vio disable failed ret=%d\n", ret); + err = regulator_enable(data->vdd); + return ret; + } + data->power_enabled = on; + } else if (on && !data->power_enabled) { + ret = regulator_enable(data->vdd); + if (ret) { + dev_err(&data->client->dev, + "Regulator vdd enable failed ret=%d\n", ret); + return ret; + } + msleep(8);////>=5ms OK. + ret = regulator_enable(data->vio); + if (ret) { + dev_err(&data->client->dev, + "Regulator vio enable failed ret=%d\n", ret); + err = regulator_disable(data->vdd); + return ret; + } + msleep(10); // wait 10ms + data->power_enabled = on; + } else { + dev_info(&data->client->dev, + "Power on=%d. enabled=%d\n", + on, data->power_enabled); + } + + return ret; +} + +static int m1120_power_init(m1120_data_t *data) +{ + int ret; + + data->vdd = regulator_get(&data->client->dev, "vdd"); + if (IS_ERR(data->vdd)) { + ret = PTR_ERR(data->vdd); + dev_err(&data->client->dev, + "Regulator get failed vdd ret=%d\n", ret); + return ret; + } + + if (regulator_count_voltages(data->vdd) > 0) { + ret = regulator_set_voltage(data->vdd, + M1120_VDD_MIN_UV, + M1120_VDD_MAX_UV); + if (ret) { + dev_err(&data->client->dev, + "Regulator set failed vdd ret=%d\n", + ret); + goto reg_vdd_put; + } + } + + data->vio = regulator_get(&data->client->dev, "vio"); + if (IS_ERR(data->vio)) { + ret = PTR_ERR(data->vio); + dev_err(&data->client->dev, + "Regulator get failed vio ret=%d\n", ret); + goto reg_vdd_set; + } + + if (regulator_count_voltages(data->vio) > 0) { + ret = regulator_set_voltage(data->vio, + M1120_VIO_MIN_UV, + M1120_VIO_MAX_UV); + if (ret) { + dev_err(&data->client->dev, + "Regulator set failed vio ret=%d\n", ret); + goto reg_vio_put; + } + } + + return 0; + +reg_vio_put: + regulator_put(data->vio); +reg_vdd_set: + if (regulator_count_voltages(data->vdd) > 0) + regulator_set_voltage(data->vdd, 0, M1120_VDD_MAX_UV); +reg_vdd_put: + regulator_put(data->vdd); + return ret; +} + + +static int tri_key_m1120_parse_dt(struct device *dev, + m1120_data_t *pdata) +{ + struct device_node *np = dev->of_node; + struct pinctrl *key_pinctrl; + struct pinctrl_state *set_state; + u32 temp_val; + int rc; + struct i2c_client *client = to_i2c_client(dev); + m1120_data_t *p_data = i2c_get_clientdata(client); + + dev_err(dev, " %s", __func__); + rc = of_property_read_u32(np, "magnachip,init-interval", &temp_val); + if (rc && (rc != -EINVAL)) { + dev_err(dev, "Unable to read init-interval\n"); + return rc; + } else { + if (temp_val < M1120_DELAY_MIN) + temp_val = M1120_DELAY_MIN; + atomic_set(&p_data->atm.delay, temp_val); + } + + p_data->int_en = of_property_read_bool(np, "magnachip,use-interrupt"); + + p_data->igpio = of_get_named_gpio_flags(dev->of_node, + "magnachip,gpio-int", 0, NULL); + + p_data->irq_gpio = of_get_named_gpio(np, "dhall,irq-gpio", 0); + dev_err(dev, "irq_gpio : %d", p_data->irq_gpio); + + p_data->use_hrtimer = of_property_read_bool(np, "magnachip,use-hrtimer"); + key_pinctrl = devm_pinctrl_get(dev); + + if (IS_ERR_OR_NULL(key_pinctrl)) { + dev_err(dev, "Failed to get pinctrl\n"); + } + set_state = pinctrl_lookup_state(key_pinctrl, + "downhall_tri_state_key_active"); + if (IS_ERR_OR_NULL(set_state)) { + dev_err(dev, "Failed to lookup_state\n"); + } + + pinctrl_select_state(key_pinctrl,set_state); + + return 0; +} + +//interface implement for op_motor.c + +static int m1120_get_data( short *data) +{ + int err = 0; + u8 buf[3] = {0}; + short value = 0; + + printk(KERN_INFO " %s", __func__); + if(!p_m1120_data) { + MOTOR_ERR("p_m1120_data == NULL"); + return -1; + } + // (1) read data + err = m1120_i2c_read_block(p_m1120_data, M1120_REG_ST1, buf, sizeof(buf)); + if (err < 0) { + MOTOR_LOG(" fail %d \n",err); + return err; + } + + // (2) collect data + if (buf[0] & 0x01) { + value = m1120_2byte_to_short(p_m1120_data, buf[2], buf[1]); + } else { + MOTOR_LOG("m1120: st1(0x%02X) is not DRDY.\n", buf[0]); + return err; + } + MOTOR_LOG("down, value : %d\n", value); + *data = value; + + return 0; +} + +static int m1120_enable_irq(bool enable) +{ + printk(KERN_INFO " %s", __func__); + + if(p_m1120_data == NULL) { + MOTOR_ERR("p_m1120_data == NULL"); + return -EINVAL; + } + + if (enable) { + enable_irq(p_m1120_data->irq); + } else { + disable_irq_nosync(p_m1120_data->irq); + } + + return 0; +} + +static int m1120_clear_irq() +{ + printk(KERN_INFO " %s", __func__); + if(p_m1120_data == NULL) { + MOTOR_ERR("p_m1120_data == NULL"); + return -EINVAL; + } + + m1120_clear_interrupt(&p_m1120_data->client->dev); + return 0; +} + +static int m1120_get_irq_state() +{ + printk(KERN_INFO " %s", __func__); + if(p_m1120_data == NULL) { + MOTOR_ERR("p_m1120_data == NULL"); + return -EINVAL; + } + + return ((p_m1120_data->reg.map.intsrs & M1120_DETECTION_MODE_INTERRUPT) ? 1 : 0); +} + +static bool m1120_update_threshold(int position, short lowthd, short highthd) +{ + + u8 lthh, lthl, hthh, hthl; + int err = 0; + + printk(KERN_INFO " %s", __func__); + if (p_m1120_data == NULL) { + MOTOR_LOG("p_m1120_data == NULL \n"); + return -EINVAL; + } + + MOTOR_LOG("m1120_down ,low:%d, high:%d \n",lowthd, highthd); + + err = m1120_clear_interrupt(&p_m1120_data->client->dev); + + //if (p_m1120_data->reg.map.intsrs & M1120_VAL_INTSRS_INTTYPE_BESIDE) { + if (p_m1120_data->reg.map.intsrs & M1120_DETECTION_MODE_INTERRUPT) { + printk("dn hall m1120_update_threshold, lowthd=%d, highthd=%d.\n", lowthd, highthd); + m1120_short_to_2byte(p_m1120_data, highthd, &hthh, &hthl); + m1120_short_to_2byte(p_m1120_data, lowthd, <hh, <hl); + + err |= m1120_i2c_write_block(p_m1120_data, M1120_REG_HTHH,&hthh, 1); + err |= m1120_i2c_write_block(p_m1120_data, M1120_REG_HTHL,&hthl, 1); + err |= m1120_i2c_write_block(p_m1120_data, M1120_REG_LTHH,<hh, 1); + err |= m1120_i2c_write_block(p_m1120_data, M1120_REG_LTHL,<hl, 1); + } + + if (err < 0) { + MOTOR_ERR("tri_key:fail %d\n",err); + return false; + } else { + return true; + } + + return true; +} + +static void m1120_dump_reg(u8* buf) +{ + int i, err; + u8 val; + u8 buffer[512] = {0}; + u8 _buf[20] = {0}; + + printk(KERN_INFO " %s", __func__); + if (p_m1120_data == NULL) { + MOTOR_LOG("p_m1120_data == NULL \n"); + return ; + } + + for (i = 0; i <= 0x12; i++) { + memset(_buf, 0, sizeof(_buf)); + + err = m1120_i2c_read_block(p_m1120_data, i, &val, 1); + if (err < 0) { + snprintf(buf, PAGE_SIZE, "read reg error!\n"); + return; + } + + snprintf(_buf, sizeof(_buf), "reg 0x%x:0x%x\n", i, val); + strcat(buffer, _buf); + } + snprintf(buf, PAGE_SIZE, "%s\n", buffer); + MOTOR_LOG("%s \n",buf); + return; +} + +static bool m1120_is_power_on() +{ + printk(KERN_INFO " %s", __func__); + if (p_m1120_data == NULL) { + MOTOR_LOG("p_m1120_data == NULL \n"); + return false; + } + + return p_m1120_data->power_enabled > 0 ? true : false; +} + +static int m1120_set_detection_mode_1(u8 mode) +{ + u8 data = 0; + int err = 0; + + printk(KERN_INFO " %s", __func__); + if(p_m1120_data == NULL) { + MOTOR_ERR("p_m1120_data == NULL"); + return -EINVAL; + } + + MOTOR_LOG("m1120 down detection mode : %s\n", (mode == 0)? "POLLING":"INTERRUPT"); + + if(mode & DETECTION_MODE_INTERRUPT) { //interrupt mode + if (!p_m1120_data->irq_enabled) { + data = p_m1120_data->reg.map.intsrs | M1120_DETECTION_MODE_INTERRUPT; + + err = m1120_i2c_write_block(p_m1120_data, M1120_REG_INTSRS, &data, 1);// + if (err < 0) { + MOTOR_ERR("config interupt fail %d \n",err); + return err; + } + + err = m1120_clear_interrupt(&p_m1120_data->client->dev); + if (err < 0) { + MOTOR_ERR("clear interupt fail %d \n",err); + return err; + } + + /* requst irq */ + MOTOR_LOG("m1120 down enter irq handler \n"); + if (request_irq(p_m1120_data->irq, &m1120_down_irq_handler, IRQ_TYPE_LEVEL_LOW, "hall_m1120_down",(void *)p_m1120_data->client)) { + MOTOR_ERR("IRQ LINE NOT AVAILABLE!!\n"); + return -EINVAL; + } + irq_set_irq_wake(p_m1120_data->irq, 1); + + p_m1120_data->irq_enabled = 1; + } + } else { // polling mode + if (p_m1120_data->irq_enabled) { + data = p_m1120_data->reg.map.intsrs & (0xFF - M1120_DETECTION_MODE_INTERRUPT); + + err = m1120_i2c_write_block(p_m1120_data, M1120_REG_INTSRS, &data, 1); + if (err < 0) { + MOTOR_ERR("config interupt fail %d \n",err); + return err; + } + + disable_irq(p_m1120_data->irq); + free_irq(p_m1120_data->irq, NULL); + + p_m1120_data->irq_enabled = 0; + } + } + + return 0; +} + +static int m1120_set_reg_1(int reg, int val) +{ + + u8 data = (u8)val; + + printk(KERN_INFO "%s", __func__); + if(p_m1120_data == NULL) { + MOTOR_ERR("p_m1120_data == NULL"); + return -EINVAL; + } + + m1120_i2c_write_block(p_m1120_data, (u8)reg, &data,1); + return 0; +} + +struct dhall_operations m1120_downs_ops = { + .get_data = m1120_get_data, + .enable_irq = m1120_enable_irq, + .clear_irq = m1120_clear_irq, + .get_irq_state = m1120_get_irq_state, + .set_detection_mode = m1120_set_detection_mode_1, + .update_threshold = m1120_update_threshold, + .dump_regs = m1120_dump_reg, + .set_reg = m1120_set_reg_1, + .is_power_on = m1120_is_power_on +}; +/************************************************** + i2c client + **************************************************/ + +static int tri_key_m1120_i2c_drv_probe(struct i2c_client *client, const struct i2c_device_id *id) +{ + m1120_platform_data_t *p_platform; + m1120_data_t *p_data; + int err = 0; + + dbg_func_in(); + + + printk(KERN_INFO " allocation memory for p_m1120_data down %s\n", __func__); + /*(1) allocation memory for p_m1120_data*/ + p_data = kzalloc(sizeof(m1120_data_t), GFP_KERNEL); + if (!p_data) { + mxerr(&client->dev, "kernel memory alocation was failed"); + err = -ENOMEM; + goto error_0; + } + + printk(KERN_INFO " init mutex variable \n"); + /*(2) init mutex variable*/ + mutex_init(&p_data->mtx.enable); + mutex_init(&p_data->mtx.data); + p_data->power_enabled = false; + + printk(KERN_INFO " config i2c client %s\n", __func__); + /*(3) config i2c client*/ + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { + mxerr(&client->dev, "i2c_check_functionality was failed"); + err = -ENODEV; + goto error_1; + } + i2c_set_clientdata(client, p_data); + p_data->client = client; + p_m1120_data = p_data; + + if (client->dev.of_node) { + dev_err(&client->dev, "Use client->dev.of_node\n"); + err = tri_key_m1120_parse_dt(&client->dev, p_data); + if (err) { + dev_err(&client->dev, "Failed to parse device tree \n"); + err = -EINVAL; + goto error_1; + } + } else { + p_platform = client->dev.platform_data; + dev_err(&client->dev, "Use platform data \n"); + } + /*(5) setup interrupt gpio*/ + /*if (p_data->igpio != -1) { + err = gpio_request(p_data->igpio, "m1120_irq"); + if (err) { + mxerr(&client->dev, "gpio_request was failed(%d)", err); + goto error_1; + } + mxinfo(&client->dev, "gpio_request was success"); + err = gpio_direction_input(p_data->igpio); + if (err < 0) { + mxerr(&client->dev, "gpio_direction_input was failed(%d)", err); + goto error_2; + } + mxinfo(&client->dev, "gpio_direction_input was success"); + }*/ + + //pull pm8150 gpio_04 down + // err = set_gpio_state(&client->dev); + // if (err) { + // dev_err(&client->dev, "Failed to set gpio state\n"); + // } + //gpio irq request + if (gpio_is_valid(p_data->irq_gpio)) { + err = gpio_request(p_data->irq_gpio, "m1120_down_irq"); + if (err) { + mxerr(&client->dev, "unable to request gpio [%d]", p_data->irq_gpio); + } else { + err = gpio_direction_input(p_data->irq_gpio); + msleep(50); + p_data->irq = gpio_to_irq(p_data->irq_gpio); + mxerr(&client->dev, " irq : %d", p_data->irq); + } + + } + + err = m1120_power_init(p_data); + if (err) { + dev_err(&client->dev, "Failed to get sensor regulators\n"); + err = -EINVAL; + goto error_1; + } + err = m1120_power_ctl(p_data, true); + if (err) { + dev_err(&client->dev, "Failed to enable sensor power\n"); + err = -EINVAL; + goto error_1; + } + + printk(KERN_INFO " reset and init device %s\n", __func__); + /*(6) reset and init device*/ + err = m1120_init_device(&p_data->client->dev); + if (err) { + mxerr(&client->dev, "m1120_init_device was failed(%d)", err); + goto error_1; + } + mxinfo(&client->dev, "%s was found", id->name); + + printk(KERN_INFO " config work function\n", __func__); + /*(7) config work function*/ + //INIT_DELAYED_WORK(&p_data->work, m1120_work_func); + + printk(KERN_INFO " init input device\n", __func__); + /*(8) init input device*/ + err = m1120_input_dev_init(p_data); + if (err) { + mxerr(&client->dev, "m1120_input_dev_init was failed(%d)", err); + goto error_1; + } + mxinfo(&client->dev, "%s was initialized", M1120_DRIVER_NAME_DOWN); + + printk(KERN_INFO " create sysfs group\n", __func__); + /*(9) create sysfs group*/ + err = sysfs_create_group(&p_data->input_dev->dev.kobj, &m1120_attribute_group); + if (err) { + mxerr(&client->dev, "sysfs_create_group was failed(%d)", err); + goto error_3; + } + + /*(10) register misc device*/ + // err = misc_register(&m1120_misc_dev); + // if (err) { + // mxerr(&client->dev, "misc_register was failed(%d)", err); + // goto error_4; + // } + + /*(11) register ops to abstrace level*/ + oneplus_register_hall("hall_m1120_down", &m1120_downs_ops);//ÍùÆäÀï±ß×¢²áhall + + printk(KERN_INFO " i2c addr : %d\n", client->addr); + + + + /*(12) imigrate p_data to p_m1120_data*/ + dbg("%s : %s was probed.\n", __func__, M1120_DRIVER_NAME_DOWN); + + return 0; + +//error_4: + // sysfs_remove_group(&p_data->input_dev->dev.kobj, &m1120_attribute_group); + +error_3: + m1120_input_dev_terminate(p_data); + + + +error_1: + kfree(p_data); + +error_0: + p_m1120_data = NULL; + return err; +} + +static int m1120_i2c_drv_remove(struct i2c_client *client) +{ + m1120_data_t *p_data = i2c_get_clientdata(client); + + m1120_set_enable(&client->dev, 0); + // misc_deregister(&m1120_misc_dev); + sysfs_remove_group(&p_data->input_dev->dev.kobj, &m1120_attribute_group); + m1120_input_dev_terminate(p_data); + if (p_data->igpio != -1) { + gpio_free(p_data->igpio); + } + kfree(p_data); + + return 0; +} + +/* +static int m1120_i2c_drv_suspend(struct i2c_client *client, pm_message_t mesg) +{ + m1120_data_t *p_data = i2c_get_clientdata(client); + + dbg_func_in(); + + mutex_lock(&p_data->mtx.enable); + + if (m1120_get_enable(&client->dev)) { + if (p_data->reg.map.intsrs & M1120_DETECTION_MODE_INTERRUPT) { + m1120_set_operation_mode(&client->dev, OPERATION_MODE_MEASUREMENT); + } else { + cancel_delayed_work_sync(&p_data->work); + m1120_set_detection_mode(&client->dev, M1120_DETECTION_MODE_INTERRUPT); + } + } + + mutex_unlock(&p_data->mtx.enable); + + dbg_func_out(); + + return 0; +} + +static int m1120_i2c_drv_resume(struct i2c_client *client) +{ + m1120_data_t *p_data = i2c_get_clientdata(client); + + dbg_func_in(); + + mutex_lock(&p_data->mtx.enable); + + if (m1120_get_enable(&client->dev)) { + if (p_data->reg.map.intsrs & M1120_DETECTION_MODE_INTERRUPT) { + m1120_set_detection_mode(&client->dev, M1120_DETECTION_MODE_POLLING); + schedule_delayed_work(&p_data->work, msecs_to_jiffies(m1120_get_delay(&client->dev))); + } + } + + mutex_unlock(&p_data->mtx.enable); + + dbg_func_out(); + + return 0; +} +*/ + +static const struct i2c_device_id m1120_i2c_drv_id_table[] = { + {"hall_m1120_down", 0 }, + { } +}; + + +static const struct of_device_id m1120_of_match[] = { + { .compatible = "tri_key_magnachip,tk_mxm1120,down", }, + { }, +}; + +static struct i2c_driver m1120_driver = { + .driver = { + .owner = THIS_MODULE, + .name = M1120_DRIVER_NAME_DOWN, + .of_match_table = m1120_of_match, + }, + .probe = tri_key_m1120_i2c_drv_probe, + .remove = m1120_i2c_drv_remove, + .id_table = m1120_i2c_drv_id_table, + //.suspend = m1120_i2c_drv_suspend, + //.resume = m1120_i2c_drv_resume, +}; + +static int __init tri_key_m1120_driver_init_down(void) +{ + int res = 0; + printk(KERN_INFO " log %s\n", __func__); + res = i2c_add_driver(&m1120_driver); + printk(KERN_INFO " log %s, res : %d\n", __func__, res); + return res;//i2c_add_driver(&m1120_driver); +} +module_init(tri_key_m1120_driver_init_down); + +static void __exit m1120_driver_exit_down(void) +{ + printk(KERN_INFO "%s\n", __func__); + i2c_del_driver(&m1120_driver); +} +module_exit(m1120_driver_exit_down); + +MODULE_AUTHOR("shpark "); +MODULE_VERSION(M1120_DRIVER_VERSION); +MODULE_DESCRIPTION("M1120 hallswitch driver"); +MODULE_LICENSE("GPL"); + diff --git a/drivers/extcon/hall_ic/hall_mxm1120_up.c b/drivers/extcon/hall_ic/hall_mxm1120_up.c new file mode 100644 index 0000000000000000000000000000000000000000..91946a6e38fdbce57b1682a2ec077f95100250fe --- /dev/null +++ b/drivers/extcon/hall_ic/hall_mxm1120_up.c @@ -0,0 +1,1461 @@ +/* + * m1120.c - Linux kernel modules for hall switch + * + * Copyright (C) 2013 Seunghwan Park + * Copyright (C) 2014 MagnaChip Semiconductor. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "hall_mxm1120.h" +#include "../oneplus_tri_key.h" + +/***********************************************************/ +/*customer config*/ +/***********************************************************/ +#define M1120_DBG_ENABLE // for debugging +#define M1120_DETECTION_MODE M1120_DETECTION_MODE_INTERRUPT/*M1120_DETECTION_MODE_POLLING /James*/ +#define M1120_INTERRUPT_TYPE M1120_VAL_INTSRS_INTTYPE_BESIDE +//#define M1120_INTERRUPT_TYPE M1120_VAL_INTSRS_INTTYPE_WITHIN +#define M1120_SENSITIVITY_TYPE M1120_VAL_INTSRS_SRS_10BIT_0_068mT +#define M1120_PERSISTENCE_COUNT M1120_VAL_PERSINT_COUNT(15) +#define M1120_OPERATION_FREQUENCY M1120_VAL_OPF_FREQ_80HZ +#define M1120_OPERATION_RESOLUTION M1120_VAL_OPF_BIT_10 +#define M1120_DETECT_RANGE_HIGH (60)/*Need change via test.*/ +#define M1120_DETECT_RANGE_LOW (50)/*Need change via test.*/ +#define M1120_RESULT_STATUS_A (0x01) // result status A ----> ==180Degree. +#define M1120_RESULT_STATUS_B (0x02) // result status B ----> != 180Degree. +#define M1120_EVENT_TYPE EV_ABS // EV_KEY +#define M1120_EVENT_CODE ABS_X // KEY_F1 +#define M1120_EVENT_DATA_CAPABILITY_MIN (-32768) +#define M1120_EVENT_DATA_CAPABILITY_MAX (32767) + +/*MagnaChip Hall Sensor power supply VDD 2.7V~3.6V, VIO 1.65~VDD*/ +#define M1120_VDD_MIN_UV 2700000 +#define M1120_VDD_MAX_UV 3600000 +#define M1120_VIO_MIN_UV 1650000 +#define M1120_VIO_MAX_UV 3600000 + +/***********************************************************/ +/*debug macro*/ +/***********************************************************/ +#ifdef M1120_DBG_ENABLE +#define dbg(fmt, args...) printk("[M1120-DBG] %s(L%04d) : " fmt "\n", __func__, __LINE__, ##args) +#define dbgn(fmt, args...) printk(fmt, ##args) +#else +#define dbg(fmt, args...) +#define dbgn(fmt, args...) +#endif // M1120_DBG_ENABLE +#define dbg_func_in() dbg("[M1120-DBG-F.IN] %s", __func__) +#define dbg_func_out() dbg("[M1120-DBG-F.OUT] %s", __func__) +#define dbg_line() dbg("[LINE] %d(%s)", __LINE__, __func__) +/***********************************************************/ + + +/***********************************************************/ +/*error display macro*/ +/***********************************************************/ +#define mxerr(pdev, fmt, args...) \ + dev_err(pdev, "[M1120-ERR] %s(L%04d) : " fmt "\n", __func__, __LINE__, ##args) +#define mxinfo(pdev, fmt, args...) \ + dev_info(pdev, "[M1120-INFO] %s(L%04d) : " fmt "\n", __func__, __LINE__, ##args) +/***********************************************************/ + +/***********************************************************/ +/*static variable*/ +/***********************************************************/ +static m1120_data_t *p_m1120_data; +/***********************************************************/ + + +/***********************************************************/ +/*function protyps*/ +/***********************************************************/ +/*i2c interface*/ +static int m1120_i2c_read_block(m1120_data_t* m1120_data, u8 addr, u8 *data, u8 len); +static int m1120_i2c_write_block(m1120_data_t* m1120_data, u8 addr, u8 *data, u8 len); +static void m1120_short_to_2byte(m1120_data_t* m1120_data, short x, u8 *hbyte, u8 *lbyte); +static short m1120_2byte_to_short(m1120_data_t* m1120_data, u8 hbyte, u8 lbyte); +/*vdd / vid power control*/ +static int m1120_set_power(struct device *dev, bool on); + + +static int m1120_get_enable(struct device *dev); +static void m1120_set_enable(struct device *dev, int enable); +static int m1120_get_delay(struct device *dev); +static void m1120_set_delay(struct device *dev, int delay); +static int m1120_get_debug(struct device *dev); +static void m1120_set_debug(struct device *dev, int debug); +static int m1120_clear_interrupt(struct device *dev); +static int m1120_set_operation_mode(struct device *dev, int mode); +static int m1120_init_device(struct device *dev); +static int m1120_reset_device(struct device *dev); +static int m1120_power_ctl(m1120_data_t *data, bool on); +static int m1120_get_data( short *data); +/***********************************************************/ + + +/***********************************************************/ +/*functions for i2c interface*/ +/***********************************************************/ +#define M1120_I2C_BUF_SIZE (17) + + +static int m1120_i2c_read_block(m1120_data_t* m1120_data, u8 addr, u8 *data, u8 len) +{ + u8 reg_addr = addr; + int err = 0; + struct i2c_client *client = NULL; + struct i2c_msg msgs[2]={{0},{0}}; + + if (!m1120_data) { + MOTOR_ERR("m1120_data == NULL\n"); + return -EINVAL; + } + client = m1120_data->client; + + if (!client) { + MOTOR_ERR("client null\n"); + return -EINVAL; + } else if (len >= M1120_I2C_BUF_SIZE) { + MOTOR_ERR(" length %d exceeds %d\n", len, M1120_I2C_BUF_SIZE); + return -EINVAL; + } + //mutex_lock(&m1120_i2c_mutex); Ëø¾ßÌåÔõôÀ´ÓÃ,µÈºóÃæÔÙ¿´,ÏÈ×¢Ê͵ô + + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len =1; + msgs[0].buf = ®_addr; + + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len =len; + msgs[1].buf = data; + + err = i2c_transfer(client->adapter, msgs, (sizeof(msgs) / sizeof(msgs[0]))); + + if (err < 0) { + MOTOR_ERR("i2c_transfer error: (%d %p %d) %d\n",addr, data, len, err); + err = -EIO; + } else { + err = 0; + } + //mutex_unlock(&m1120_i2c_mutex); + + return err; + +} + +static int m1120_i2c_write_block(m1120_data_t* m1120_data, u8 addr, u8 *data, u8 len) +{ + int err = 0; + int idx = 0; + int num = 0; + char buf[M1120_I2C_BUF_SIZE] ={0}; + struct i2c_client *client = NULL; + + if (!m1120_data) { + MOTOR_ERR("m1120_data == NULL\n"); + return -EINVAL; + } + client = m1120_data->client; + + if (!client) { + MOTOR_ERR("client null\n"); + return -EINVAL; + } else if (len >= M1120_I2C_BUF_SIZE) { + MOTOR_ERR(" length %d exceeds %d\n", len, M1120_I2C_BUF_SIZE); + return -EINVAL; + } + + //mutex_lock(&m1120_i2c_mutex); + + buf[num++] = addr; + for (idx = 0; idx < len; idx++) { + buf[num++] = data[idx]; + } + + err = i2c_master_send(client, buf, num); + if (err < 0) { + MOTOR_ERR("send command error!! %d\n",err); + } + + //store reg written + if (len == 1) { + switch(addr){ + case M1120_REG_PERSINT: + m1120_data->reg.map.persint = data[0]; + break; + case M1120_REG_INTSRS: + m1120_data->reg.map.intsrs = data[0]; + break; + case M1120_REG_LTHL: + m1120_data->reg.map.lthl = data[0]; + break; + case M1120_REG_LTHH: + m1120_data->reg.map.lthh = data[0]; + break; + case M1120_REG_HTHL: + m1120_data->reg.map.hthl = data[0]; + break; + case M1120_REG_HTHH: + m1120_data->reg.map.hthh = data[0]; + break; + case M1120_REG_I2CDIS: + m1120_data->reg.map.i2cdis = data[0]; + break; + case M1120_REG_SRST: + m1120_data->reg.map.srst = data[0]; + break; + case M1120_REG_OPF: + m1120_data->reg.map.opf = data[0]; + break; + } + } + + //mutex_unlock(&m1120_i2c_mutex); + return err; +} + +static void m1120_short_to_2byte(m1120_data_t* m1120_data, short x, u8 *hbyte, u8 *lbyte) +{ + if (!m1120_data) { + MOTOR_ERR("m1120_data == NULL\n"); + return ; + } + + if ((m1120_data->reg.map.opf & M1120_VAL_OPF_BIT_8) == M1120_VAL_OPF_BIT_8) { + /* 8 bit resolution */ + if (x < -128) { + x = -128; + } else if(x > 127) { + x = 127; + } + + if (x >= 0) { + *lbyte = x & 0x7F; + } else { + *lbyte = ( (0x80 - (x*(-1))) & 0x7F ) | 0x80; + } + *hbyte = 0x00; + } else { + /* 10 bit resolution */ + if (x < -512) { + x = -512; + } else if (x > 511) { + x = 511; + } + + if (x >=0 ) { + *lbyte = x & 0xFF; + *hbyte = (((x & 0x100) >> 8) & 0x01) << 6; + } else { + *lbyte = (0x0200 - (x*(-1))) & 0xFF; + *hbyte = ((((0x0200 - (x*(-1))) & 0x100) >> 8) << 6) | 0x80; + } + } +} +/***********************************************************/ + + +static short m1120_2byte_to_short(m1120_data_t* m1120_data, u8 hbyte, u8 lbyte) +{ + short x = 0; + + if (!m1120_data) { + MOTOR_ERR("m1120_data == NULL\n"); + return -EINVAL; + } + + if( (m1120_data->reg.map.opf & M1120_VAL_OPF_BIT_8) == M1120_VAL_OPF_BIT_8) { + /* 8 bit resolution */ + x = lbyte & 0x7F; + if (lbyte & 0x80) { + x -= 0x80; + } + } else { + /* 10 bit resolution */ + x = ( ( (hbyte & 0x40) >> 6) << 8 ) | lbyte; + if (hbyte & 0x80) { + x -= 0x200; + } + } + + return x; +} + +/***********************************************************/ +/*vdd / vid power control*/ +/***********************************************************/ +static int m1120_set_power(struct device *dev, bool on) +{ + m1120_power_ctl(p_m1120_data, on); + + return 0; +} +/***********************************************************/ + + +static irqreturn_t m1120_up_irq_handler(int irq, void *dev_id) +{ + MOTOR_LOG("call \n"); + + if (!p_m1120_data) { + MOTOR_LOG("p_m1120_data NULL \n"); + return -EINVAL; + } + + disable_irq_nosync(p_m1120_data->irq); + oneplus_hall_irq_handler(0);//DHALL_UP + + return IRQ_HANDLED; +} + + +static int m1120_get_enable(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + m1120_data_t *p_data = i2c_get_clientdata(client); + + return atomic_read(&p_data->atm.enable); +} + + +static void m1120_set_enable(struct device *dev, int enable) +{ + struct i2c_client *client = to_i2c_client(dev); + m1120_data_t *p_data = i2c_get_clientdata(client); +// int delay = m1120_get_delay(dev); + + mutex_lock(&p_data->mtx.enable); + MOTOR_LOG("enable : %d\n", enable); + if (enable) { /*enable if state will be changed*/ + if (!atomic_cmpxchg(&p_data->atm.enable, 0, 1)) { + //m1120_set_detection_mode(dev, p_data->reg.map.intsrs & M1120_DETECTION_MODE_INTERRUPT); + //m1120_set_detection_mode(dev, p_data->reg.map.intsrs & M1120_DETECTION_MODE_POLLING); + m1120_set_operation_mode(&p_m1120_data->client->dev, OPERATION_MODE_MEASUREMENT); + /*if(!(p_data->reg.map.intsrs & M1120_DETECTION_MODE_INTERRUPT))*/ + // if (0) { + // schedule_delayed_work(&p_data->work, msecs_to_jiffies(delay)); + // } + } + } else { /*disable if state will be changed*/ + if (atomic_cmpxchg(&p_data->atm.enable, 1, 0)) { + //cancel_delayed_work_sync(&p_data->work); + m1120_set_operation_mode(&p_m1120_data->client->dev, OPERATION_MODE_POWERDOWN); + } + } + atomic_set(&p_data->atm.enable, enable); + + mutex_unlock(&p_data->mtx.enable); +} + +static int m1120_get_delay(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + m1120_data_t *p_data = i2c_get_clientdata(client); + + int delay = 0; + + delay = atomic_read(&p_data->atm.delay); + + return delay; +} + +static void m1120_set_delay(struct device *dev, int delay) +{ + struct i2c_client *client = to_i2c_client(dev); + m1120_data_t *p_data = i2c_get_clientdata(client); + + if (delay < M1120_DELAY_MIN) + delay = M1120_DELAY_MIN; + atomic_set(&p_data->atm.delay, delay); + + mutex_lock(&p_data->mtx.enable); + + if (m1120_get_enable(dev)) { + if (!(p_data->reg.map.intsrs & M1120_DETECTION_MODE_INTERRUPT)) { + cancel_delayed_work_sync(&p_data->work); + schedule_delayed_work(&p_data->work, msecs_to_jiffies(delay)); + } + } + + mutex_unlock(&p_data->mtx.enable); +} + +static int m1120_get_debug(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + m1120_data_t *p_data = i2c_get_clientdata(client); + + return atomic_read(&p_data->atm.debug); +} + +static void m1120_set_debug(struct device *dev, int debug) +{ + struct i2c_client *client = to_i2c_client(dev); + m1120_data_t *p_data = i2c_get_clientdata(client); + + atomic_set(&p_data->atm.debug, debug); +} + +static int m1120_clear_interrupt(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + m1120_data_t *p_data = i2c_get_clientdata(client); + int ret = 0; + u8 data = 0x00; + + data = p_data->reg.map.persint | 0x01; + ret = m1120_i2c_write_block(p_data, M1120_REG_PERSINT, &data,1); + + return ret; +} + +static int m1120_set_operation_mode(struct device *dev, int mode) +{ + struct i2c_client *client = to_i2c_client(dev); + m1120_data_t *p_data = i2c_get_clientdata(client); + u8 opf = p_data->reg.map.opf; + int err = -1; + + switch (mode) { + case OPERATION_MODE_POWERDOWN: + opf &= (0xFF - M1120_VAL_OPF_HSSON_ON); + err = m1120_i2c_write_block(p_data, M1120_REG_OPF, &opf, 1); + mxinfo(&client->dev, "operation mode was chnaged to OPERATION_MODE_POWERDOWN"); + break; + case OPERATION_MODE_MEASUREMENT: + opf &= (0xFF - M1120_VAL_OPF_EFRD_ON); + opf |= M1120_VAL_OPF_HSSON_ON; + err = m1120_i2c_write_block(p_data, M1120_REG_OPF, &opf, 1); + + mxinfo(&client->dev, "operation mode was chnaged to OPERATION_MODE_MEASUREMENT"); + break; + case OPERATION_MODE_FUSEROMACCESS: + opf |= M1120_VAL_OPF_EFRD_ON; + opf |= M1120_VAL_OPF_HSSON_ON; + err = m1120_i2c_write_block(p_data, M1120_REG_OPF, &opf, 1); + mxinfo(&client->dev, "operation mode was chnaged to OPERATION_MODE_FUSEROMACCESS"); + break; + } + mxinfo(&client->dev, "opf = ox%x \n", opf); + return err; +} + +static int m1120_init_device(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + m1120_data_t *p_data = i2c_get_clientdata(client); + int err = -1; + + /*(1) vdd and vid power up*/ + err = m1120_set_power(dev, 1); + if (err) { + mxerr(&client->dev, "m1120 power-on was failed (%d)", err); + return err; + } + + /*(2) init variables*/ + atomic_set(&p_data->atm.enable, 0); + atomic_set(&p_data->atm.delay, M1120_DELAY_MIN); +#ifdef M1120_DBG_ENABLE + atomic_set(&p_data->atm.debug, 1); +#else + atomic_set(&p_data->atm.debug, 0); +#endif + p_data->calibrated_data = 0; + p_data->last_data = 0; + p_data->irq_enabled = 0; + p_data->irq_first = 1; + p_data->thrhigh = M1120_DETECT_RANGE_HIGH; + p_data->thrlow = M1120_DETECT_RANGE_LOW; + m1120_set_delay(&client->dev, M1120_DELAY_MAX); + m1120_set_debug(&client->dev, 0); + + /*(3) reset registers*/ + err = m1120_reset_device(dev); + if (err < 0) { + mxerr(&client->dev, "m1120_reset_device was failed (%d)", err); + return err; + } + + mxinfo(&client->dev, "initializing device was success"); + + return 0; +} + +static int m1120_reset_device(struct device *dev) +{ + int err = 0; + u8 id = 0xFF, data = 0x00; + + struct i2c_client *client = to_i2c_client(dev); + m1120_data_t *p_data = i2c_get_clientdata(client); + + if ((p_data == NULL) || (p_data->client == NULL)) + return -ENODEV; + + /*(1) sw reset*/ + data = M1120_VAL_SRST_RESET; + err = m1120_i2c_write_block(p_data, M1120_REG_SRST, &data,1); + if (err < 0) { + mxerr(&client->dev, "sw-reset was failed(%d)", err); + return err; + } + msleep(5); + dbg("wait 5ms after vdd power up"); + + /*(2) check id*/ + err = m1120_i2c_read_block(p_data, M1120_REG_DID, &id, 1); + if (err < 0) + return err; + if (id != M1120_VAL_DID) { + mxerr(&client->dev, "current device id(0x%02X) is not M1120 device id(0x%02X)", id, M1120_VAL_DID); + return -ENXIO; + } + + /*(3) init variables*/ + /*(3-1) persint*/ + data = M1120_PERSISTENCE_COUNT; + err = m1120_i2c_write_block(p_data, M1120_REG_PERSINT, &data,1); + if (err <0) { + mxerr(&client->dev, "cm1120_i2c_write_block error, data : %d", data); + return err; + } + /*(3-2) intsrs*/ + data = M1120_DETECTION_MODE | M1120_SENSITIVITY_TYPE; + if (data & M1120_DETECTION_MODE_INTERRUPT) { + data |= M1120_INTERRUPT_TYPE; + } + err = m1120_i2c_write_block(p_data, M1120_REG_INTSRS, &data, 1); + if (err < 0) { + mxerr(&client->dev, "cm1120_i2c_write_block error, data : %d", data); + return err; + } + /*(3-3) opf*/ + data = M1120_OPERATION_FREQUENCY | M1120_OPERATION_RESOLUTION; + err = m1120_i2c_write_block(p_data, M1120_REG_OPF, &data, 1); + if (err < 0) { + mxerr(&client->dev, "cm1120_i2c_write_block error, data : %d", data); + return err; + } + + /*(4) write variable to register*/ + // err = m1120_set_detection_mode(dev, M1120_DETECTION_MODE); + // if (err) { + // mxerr(&client->dev, "m1120_set_detection_mode was failed(%d)", err); + // return err; + // } + + + /*(5) set power-on mode*/ + err = m1120_set_operation_mode(dev, OPERATION_MODE_MEASUREMENT); + if (err < 0) { + mxerr(&client->dev, "m1120_set_detection_mode was failed(%d)", err); + return err; + } + + return err; +} + +/************************************************** + input device interface + **************************************************/ +static int m1120_input_dev_init(m1120_data_t *p_data) +{ + struct input_dev *dev; + int err; + + dev = input_allocate_device(); + if (!dev) { + return -ENOMEM; + } + dev->name = M1120_DRIVER_NAME_UP; + dev->id.bustype = BUS_I2C; + +#if (M1120_EVENT_TYPE == EV_ABS) + input_set_drvdata(dev, p_data); + input_set_capability(dev, M1120_EVENT_TYPE, ABS_MISC); + input_set_abs_params(dev, M1120_EVENT_CODE, M1120_EVENT_DATA_CAPABILITY_MIN, M1120_EVENT_DATA_CAPABILITY_MAX, 0, 0); +#elif (M1120_EVENT_TYPE == EV_KEY) + input_set_drvdata(dev, p_data); + input_set_capability(dev, M1120_EVENT_TYPE, M1120_EVENT_CODE); +#else +#error ("[ERR] M1120_EVENT_TYPE is not defined.") +#endif + + err = input_register_device(dev); + if (err < 0) { + input_free_device(dev); + return err; + } + + p_data->input_dev = dev; + + return 0; +} + +static void m1120_input_dev_terminate(m1120_data_t *p_data) +{ + struct input_dev *dev = p_data->input_dev; + + input_unregister_device(dev); + input_free_device(dev); +} + +/************************************************** + sysfs attributes + **************************************************/ +static ssize_t m1120_enable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return snprintf(buf, 20, "%d\n", m1120_get_enable(dev)); +} + +static ssize_t m1120_enable_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + unsigned long enable = simple_strtoul(buf, NULL, 10); + + if ((enable == 0) || (enable == 1)) { + m1120_set_enable(dev, enable); + } + + return count; +} + +static ssize_t m1120_delay_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return snprintf(buf, 20, "%d\n", m1120_get_delay(dev)); +} + +static ssize_t m1120_delay_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + unsigned long delay = simple_strtoul(buf, NULL, 10); + + if (delay > M1120_DELAY_MAX) { + delay = M1120_DELAY_MAX; + } + + m1120_set_delay(dev, delay); + + return count; +} + +static ssize_t m1120_debug_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return snprintf(buf, 20, "%d\n", m1120_get_debug(dev)); +} + +static ssize_t m1120_debug_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + unsigned long debug = simple_strtoul(buf, NULL, 10); + + m1120_set_debug(dev, debug); + + return count; +} + +static ssize_t m1120_wake_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + return 0; +} + +static ssize_t m1120_data_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + //struct i2c_client *client = to_i2c_client(dev); + //m1120_data_t *p_data = i2c_get_clientdata(client); + short raw = 0; + m1120_get_data(&raw); + return snprintf(buf, 10, "%d\n", raw); +} + +static int m1120_i2c_read(struct i2c_client *client, u8 reg, u8 *rdata, u8 len) +{ +#if 0////add by James. + int rc; + struct i2c_msg msg[] = { + { + .addr = client->addr, + .flags = 0, + .len = 1, + .buf = ®, + }, + { + .addr = client->addr, + .flags = I2C_M_RD, + .len = len, + .buf = rdata, + }, + }; + if (client == NULL) { + mxerr(&client->dev, "client is NULL"); + return -ENODEV; + } + rc = i2c_transfer(client->adapter, msg, 2); + if (rc < 0) { + mxerr(&client->dev, "i2c_transfer was failed(%d)", rc); + return rc; + } +#else + /*Add By James for i2c_smbus_read_i2c_block_data */ + i2c_smbus_read_i2c_block_data(client, reg, len, rdata); +#endif + return 0; +} + +static int m1120_i2c_get_reg(struct i2c_client *client, u8 reg, u8 *rdata) +{ + return m1120_i2c_read(client, reg, rdata, 1); +} + +static void m1120_get_reg(struct device *dev, int *regdata) +{ + struct i2c_client *client = to_i2c_client(dev); + int err; + u8 rega = (((*regdata) >> 8) & 0xFF); + u8 regd = 0; + err = m1120_i2c_get_reg(client, rega, ®d); + *regdata = 0; + *regdata |= (err == 0) ? 0x0000 : 0xFF00; + *regdata |= regd; +} + +static ssize_t m1120_dump_show(struct device *dev,struct device_attribute *attr, char *buf) +{ + int reg = 0; + int reg_l = M1120_REG_HSL; + int reg_h = M1120_REG_HSH; + int i = 0; + for (i = 0; i < 11; i++) { + reg = i<<8; + m1120_get_reg(&p_m1120_data->client->dev, ®); + printk(KERN_ERR"dkk: the reg 0x%02X value: 0x%02X\n", i, reg); + } + m1120_get_reg(&p_m1120_data->client->dev, ®_l); + printk(KERN_ERR"dkk: the reg_l is 0x%02X\n", (u8)(reg_l&0xFF)); + m1120_get_reg(&p_m1120_data->client->dev, ®_h); + printk(KERN_ERR"dkk: the reg_h is 0x%02X", (u8)(reg_h&0xFF)); + reg = ((reg_h&0xC0) << 2)|reg_l; + printk(KERN_ERR"dkk: the down hall reg measure is 0x%02X\n", reg); + return snprintf(buf, 10, "%d\n", reg); +//return 0; + } + + +static DEVICE_ATTR(enable, S_IRUGO|S_IWUSR|S_IWGRP, m1120_enable_show, m1120_enable_store); +static DEVICE_ATTR(delay, S_IRUGO|S_IWUSR|S_IWGRP, m1120_delay_show, m1120_delay_store); +static DEVICE_ATTR(debug, S_IRUGO|S_IWUSR|S_IWGRP, m1120_debug_show, m1120_debug_store); +static DEVICE_ATTR(wake, S_IWUSR|S_IWGRP, NULL, m1120_wake_store); +static DEVICE_ATTR(rawdata, S_IRUGO|S_IWUSR|S_IWGRP, m1120_data_show, NULL); +static DEVICE_ATTR(dump, S_IRUGO|S_IWUSR|S_IWGRP, m1120_dump_show, NULL); + +static struct attribute *m1120_attributes[] = { + &dev_attr_enable.attr, + &dev_attr_delay.attr, + &dev_attr_debug.attr, + &dev_attr_wake.attr, + &dev_attr_rawdata.attr, + &dev_attr_dump.attr, + NULL +}; + +static struct attribute_group m1120_attribute_group = { + .attrs = m1120_attributes +}; + +static int m1120_power_ctl(m1120_data_t *data, bool on) +{ + int ret = 0; + int err = 0; + + if (!on && data->power_enabled) { + ret = regulator_disable(data->vdd); + if (ret) { + dev_err(&data->client->dev, + "Regulator vdd disable failed ret=%d\n", ret); + return ret; + } + + ret = regulator_disable(data->vio); + if (ret) { + dev_err(&data->client->dev, + "Regulator vio disable failed ret=%d\n", ret); + err = regulator_enable(data->vdd); + return ret; + } + data->power_enabled = on; + } else if (on && !data->power_enabled) { + ret = regulator_enable(data->vdd); + if (ret) { + dev_err(&data->client->dev, + "Regulator vdd enable failed ret=%d\n", ret); + return ret; + } + msleep(8);////>=5ms OK. + ret = regulator_enable(data->vio); + if (ret) { + dev_err(&data->client->dev, + "Regulator vio enable failed ret=%d\n", ret); + err = regulator_disable(data->vdd); + return ret; + } + msleep(10); // wait 10ms + data->power_enabled = on; + } else { + dev_info(&data->client->dev, + "Power on=%d. enabled=%d\n", + on, data->power_enabled); + } + + return ret; +} + +static int m1120_power_init(m1120_data_t *data) +{ + int ret; + + data->vdd = regulator_get(&data->client->dev, "vdd"); + if (IS_ERR(data->vdd)) { + ret = PTR_ERR(data->vdd); + dev_err(&data->client->dev, + "Regulator get failed vdd ret=%d\n", ret); + return ret; + } + + if (regulator_count_voltages(data->vdd) > 0) { + ret = regulator_set_voltage(data->vdd, + M1120_VDD_MIN_UV, + M1120_VDD_MAX_UV); + if (ret) { + dev_err(&data->client->dev, + "Regulator set failed vdd ret=%d\n", + ret); + goto reg_vdd_put; + } + } + + data->vio = regulator_get(&data->client->dev, "vio"); + if (IS_ERR(data->vio)) { + ret = PTR_ERR(data->vio); + dev_err(&data->client->dev, + "Regulator get failed vio ret=%d\n", ret); + goto reg_vdd_set; + } + + if (regulator_count_voltages(data->vio) > 0) { + ret = regulator_set_voltage(data->vio, + M1120_VIO_MIN_UV, + M1120_VIO_MAX_UV); + if (ret) { + dev_err(&data->client->dev, + "Regulator set failed vio ret=%d\n", ret); + goto reg_vio_put; + } + } + + return 0; + +reg_vio_put: + regulator_put(data->vio); +reg_vdd_set: + if (regulator_count_voltages(data->vdd) > 0) + regulator_set_voltage(data->vdd, 0, M1120_VDD_MAX_UV); +reg_vdd_put: + regulator_put(data->vdd); + return ret; +} + + +static int tri_key_m1120_parse_dt(struct device *dev, + m1120_data_t *pdata) +{ + struct device_node *np = dev->of_node; + struct pinctrl *key_pinctrl; + struct pinctrl_state *set_state; + u32 temp_val; + int rc; + struct i2c_client *client = to_i2c_client(dev); + m1120_data_t *p_data = i2c_get_clientdata(client); + + dev_err(dev, "======> %s", __func__); + rc = of_property_read_u32(np, "magnachip,init-interval", &temp_val); + if (rc && (rc != -EINVAL)) { + dev_err(dev, "Unable to read init-interval\n"); + return rc; + } else { + if (temp_val < M1120_DELAY_MIN) + temp_val = M1120_DELAY_MIN; + atomic_set(&p_data->atm.delay, temp_val); + } + + p_data->int_en = of_property_read_bool(np, "magnachip,use-interrupt"); + + p_data->igpio = of_get_named_gpio_flags(dev->of_node, + "magnachip,gpio-int", 0, NULL); + + p_data->irq_gpio = of_get_named_gpio(np, "dhall,irq-gpio", 0); + dev_err(dev, "irq_gpio : %d", p_data->irq_gpio); + + p_data->use_hrtimer = of_property_read_bool(np, "magnachip,use-hrtimer"); + + key_pinctrl = devm_pinctrl_get(dev); + + if (IS_ERR_OR_NULL(key_pinctrl)) { + dev_err(dev, "Failed to get pinctrl\n"); + } + set_state = pinctrl_lookup_state(key_pinctrl, + "uphall_tri_state_key_active"); + if (IS_ERR_OR_NULL(set_state)) { + dev_err(dev, "Failed to lookup_state\n"); + } + + pinctrl_select_state(key_pinctrl,set_state); + + + return 0; +} + +//interface implement for op_motor.c + +static int m1120_get_data( short *data) +{ + int err = 0; + u8 buf[3] = {0}; + short value = 0; + + printk(KERN_INFO "======> %s", __func__); + if(!p_m1120_data) { + MOTOR_ERR("p_m1120_data == NULL"); + return -1; + } + // (1) read data + err = m1120_i2c_read_block(p_m1120_data, M1120_REG_ST1, buf, sizeof(buf)); + if (err < 0) { + MOTOR_LOG(" fail %d \n",err); + return err; + } + + // (2) collect data + if (buf[0] & 0x01) { + value = m1120_2byte_to_short(p_m1120_data, buf[2], buf[1]); + } else { + MOTOR_LOG("m1120: st1(0x%02X) is not DRDY.\n", buf[0]); + return err; + } + *data = value; + MOTOR_LOG("up, value : %d\n", value); + return 0; +} + +static int m1120_enable_irq(bool enable) +{ + printk(KERN_INFO "======> %s", __func__); + + if(p_m1120_data == NULL) { + MOTOR_ERR("p_m1120_data == NULL"); + return -EINVAL; + } + + if (enable) { + enable_irq(p_m1120_data->irq); + } else { + disable_irq_nosync(p_m1120_data->irq); + } + + return 0; +} + +static int m1120_clear_irq() +{ + printk(KERN_INFO "======> %s", __func__); + if(p_m1120_data == NULL) { + MOTOR_ERR("p_m1120_data == NULL"); + return -EINVAL; + } + + m1120_clear_interrupt(&p_m1120_data->client->dev); + return 0; +} + +static int m1120_get_irq_state() +{ + printk(KERN_INFO "======> %s", __func__); + if(p_m1120_data == NULL) { + MOTOR_ERR("p_m1120_data == NULL"); + return -EINVAL; + } + + return ((p_m1120_data->reg.map.intsrs & M1120_DETECTION_MODE_INTERRUPT) ? 1 : 0); +} + +static bool m1120_update_threshold(int position, short lowthd, short highthd) +{ + + u8 lthh, lthl, hthh, hthl; + int err = 0; + + printk(KERN_INFO "======> %s", __func__); + if (p_m1120_data == NULL) { + MOTOR_LOG("p_m1120_data == NULL \n"); + return -EINVAL; + } + + MOTOR_LOG("m1120_up ,low:%d, high:%d \n",lowthd, highthd); + + err = m1120_clear_interrupt(&p_m1120_data->client->dev); + + //if (p_m1120_data->reg.map.intsrs & M1120_VAL_INTSRS_INTTYPE_BESIDE) { + if (p_m1120_data->reg.map.intsrs & M1120_DETECTION_MODE_INTERRUPT) { + printk("up hall m1120_update_threshold, lowthd=%d, highthd=%d.\n", lowthd, highthd); + m1120_short_to_2byte(p_m1120_data, highthd, &hthh, &hthl); + m1120_short_to_2byte(p_m1120_data, lowthd, <hh, <hl); + + err |= m1120_i2c_write_block(p_m1120_data, M1120_REG_HTHH,&hthh, 1); + err |= m1120_i2c_write_block(p_m1120_data, M1120_REG_HTHL,&hthl, 1); + err |= m1120_i2c_write_block(p_m1120_data, M1120_REG_LTHH,<hh, 1); + err |= m1120_i2c_write_block(p_m1120_data, M1120_REG_LTHL,<hl, 1); + } + + if (err < 0) { + MOTOR_ERR("tri_key:fail %d\n",err); + return false; + } else { + return true; + } + + return true; +} + +static void m1120_dump_reg(u8* buf) +{ + int i, err; + u8 val; + u8 buffer[512] = {0}; + u8 _buf[20] = {0}; + + printk(KERN_INFO "======> %s", __func__); + if (p_m1120_data == NULL) { + MOTOR_LOG("p_m1120_data == NULL \n"); + return ; + } + + for (i = 0; i <= 0x12; i++) { + memset(_buf, 0, sizeof(_buf)); + + err = m1120_i2c_read_block(p_m1120_data, i, &val, 1); + if (err < 0) { + snprintf(buf, PAGE_SIZE, "read reg error!\n"); + return; + } + + snprintf(_buf, sizeof(_buf), "reg 0x%x:0x%x\n", i, val); + strcat(buffer, _buf); + } + snprintf(buf, PAGE_SIZE, "%s\n", buffer); + MOTOR_LOG("%s \n",buf); + return; +} + +static bool m1120_is_power_on() +{ + printk(KERN_INFO "======> %s", __func__); + if (p_m1120_data == NULL) { + MOTOR_LOG("p_m1120_data == NULL \n"); + return false; + } + + return p_m1120_data->power_enabled > 0 ? true : false; +} + +static int m1120_set_detection_mode_1(u8 mode) +{ + u8 data = 0; + int err = 0; + + printk(KERN_INFO "======> %s", __func__); + if(p_m1120_data == NULL) { + MOTOR_ERR("p_m1120_data == NULL"); + return -EINVAL; + } + + MOTOR_LOG("m1120 up detection mode : %s\n", (mode == 0)? "POLLING":"INTERRUPT"); + + if(mode & DETECTION_MODE_INTERRUPT) { //interrupt mode + if (!p_m1120_data->irq_enabled) { + data = p_m1120_data->reg.map.intsrs | M1120_DETECTION_MODE_INTERRUPT; + + err = m1120_i2c_write_block(p_m1120_data, M1120_REG_INTSRS, &data, 1);// + if (err < 0) { + MOTOR_ERR("config interupt fail %d \n",err); + return err; + } + + err = m1120_clear_interrupt(&p_m1120_data->client->dev); + if (err < 0) { + MOTOR_ERR("clear interupt fail %d \n",err); + return err; + } + + /* requst irq */ + MOTOR_LOG("m1120 down enter irq handler\n"); + if (request_irq(p_m1120_data->irq, &m1120_up_irq_handler, IRQ_TYPE_LEVEL_LOW, "hall_m1120_up",(void *)p_m1120_data->client)) { + MOTOR_ERR("IRQ LINE NOT AVAILABLE!!\n"); + return -EINVAL; + } + irq_set_irq_wake(p_m1120_data->irq, 1); + + p_m1120_data->irq_enabled = 1; + } + } else { // polling mode + if (p_m1120_data->irq_enabled) { + data = p_m1120_data->reg.map.intsrs & (0xFF - M1120_DETECTION_MODE_INTERRUPT); + + err = m1120_i2c_write_block(p_m1120_data, M1120_REG_INTSRS, &data, 1); + if (err < 0) { + MOTOR_ERR("config interupt fail %d \n",err); + return err; + } + + disable_irq(p_m1120_data->irq); + free_irq(p_m1120_data->irq, NULL); + + p_m1120_data->irq_enabled = 0; + } + } + + return 0; +} + +static int m1120_set_reg_1(int reg, int val) +{ + + u8 data = (u8)val; + + printk(KERN_INFO "======> %s", __func__); + if(p_m1120_data == NULL) { + MOTOR_ERR("p_m1120_data == NULL"); + return -EINVAL; + } + + m1120_i2c_write_block(p_m1120_data, (u8)reg, &data,1); + return 0; +} + +struct dhall_operations m1120_ups_ops = { + .get_data = m1120_get_data, + .enable_irq = m1120_enable_irq, + .clear_irq = m1120_clear_irq, + .get_irq_state = m1120_get_irq_state, + .set_detection_mode = m1120_set_detection_mode_1, + .update_threshold = m1120_update_threshold, + .dump_regs = m1120_dump_reg, + .set_reg = m1120_set_reg_1, + .is_power_on = m1120_is_power_on +}; + +/************************************************** + i2c client + **************************************************/ + +static int tri_key_m1120_i2c_drv_probe(struct i2c_client *client, const struct i2c_device_id *id) +{ + m1120_platform_data_t *p_platform; + m1120_data_t *p_data; + int err = 0; + + dbg_func_in(); + + printk(KERN_INFO "======> allocation memory for p_m1120_data up %s\n", __func__); + /*(1) allocation memory for p_m1120_data*/ + p_data = kzalloc(sizeof(m1120_data_t), GFP_KERNEL); + if (!p_data) { + mxerr(&client->dev, "kernel memory alocation was failed"); + err = -ENOMEM; + goto error_0; + } + + /*(2) init mutex variable*/ + mutex_init(&p_data->mtx.enable); + mutex_init(&p_data->mtx.data); + p_data->power_enabled = false; + printk(KERN_INFO "======> init mutex variable \n"); + /*(3) config i2c client*/ + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { + mxerr(&client->dev, "i2c_check_functionality was failed"); + err = -ENODEV; + goto error_1; + } + i2c_set_clientdata(client, p_data); + p_data->client = client; + p_m1120_data = p_data; + + if (client->dev.of_node) { + dev_err(&client->dev, "Use client->dev.of_node\n"); + err = tri_key_m1120_parse_dt(&client->dev, p_data); + if (err) { + dev_err(&client->dev, "Failed to parse device tree\n"); + err = -EINVAL; + goto error_1; + } + } else { + p_platform = client->dev.platform_data; + dev_err(&client->dev, "Use platform data\n"); + } + /*(5) setup interrupt gpio*/ + /*if (p_data->igpio != -1) { + err = gpio_request(p_data->igpio, "m1120_irq"); + if (err) { + mxerr(&client->dev, "gpio_request was failed(%d)", err); + goto error_1; + } + mxinfo(&client->dev, "gpio_request was success"); + err = gpio_direction_input(p_data->igpio); + if (err < 0) { + mxerr(&client->dev, "gpio_direction_input was failed(%d)", err); + goto error_2; + } + mxinfo(&client->dev, "gpio_direction_input was success"); + }*/ + + //pull pm8150 gpio_04 down + // err = set_gpio_state(&client->dev); + // if (err) { + // dev_err(&client->dev, "Failed to set gpio state\n"); + // } + //gpio irq request + if (gpio_is_valid(p_data->irq_gpio)) { + err = gpio_request(p_data->irq_gpio, "m1120_up_irq"); + if (err) { + mxerr(&client->dev, "unable to request gpio [%d]", p_data->irq_gpio); + } else { + err = gpio_direction_input(p_data->irq_gpio); + msleep(50); + p_data->irq = gpio_to_irq(p_data->irq_gpio); + mxerr(&client->dev, "======> irq : %d", p_data->irq); + } + + } + + err = m1120_power_init(p_data); + if (err) { + dev_err(&client->dev, "Failed to get sensor regulators\n"); + err = -EINVAL; + goto error_1; + } + err = m1120_power_ctl(p_data, true); + if (err) { + dev_err(&client->dev, "Failed to enable sensor power\n"); + err = -EINVAL; + goto error_1; + } + + + /*(6) reset and init device*/ + err = m1120_init_device(&p_data->client->dev); + if (err) { + mxerr(&client->dev, "m1120_init_device was failed(%d)", err); + goto error_1; + } + mxinfo(&client->dev, "%s was found", id->name); + + /*(7) config work function*/ + //INIT_DELAYED_WORK(&p_data->work, m1120_work_func); + + /*(8) init input device*/ + err = m1120_input_dev_init(p_data); + if (err) { + mxerr(&client->dev, "m1120_input_dev_init was failed(%d)", err); + goto error_1; + } + mxinfo(&client->dev, "%s was initialized", M1120_DRIVER_NAME_UP); + + /*(9) create sysfs group*/ + err = sysfs_create_group(&p_data->input_dev->dev.kobj, &m1120_attribute_group); + if (err) { + mxerr(&client->dev, "sysfs_create_group was failed(%d)", err); + goto error_3; + } + + /*(10) register misc device*/ + // err = misc_register(&m1120_misc_dev); + // if (err) { + // mxerr(&client->dev, "misc_register was failed(%d)", err); + // goto error_4; + // } + + /*(11) register ops to abstrace level*/ + oneplus_register_hall("hall_m1120_up",&m1120_ups_ops); + + printk(KERN_INFO "======> i2c addr : %d\n", client->addr); + /*(12) imigrate p_data to p_m1120_data*/ + dbg("%s : %s was probed.\n", __func__, M1120_DRIVER_NAME_UP); + + return 0; + +//error_4: + // sysfs_remove_group(&p_data->input_dev->dev.kobj, &m1120_attribute_group); + +error_3: + m1120_input_dev_terminate(p_data); + + +error_1: + kfree(p_data); + +error_0: + p_m1120_data = NULL; + return err; +} + +static int m1120_i2c_drv_remove(struct i2c_client *client) +{ + m1120_data_t *p_data = i2c_get_clientdata(client); + + m1120_set_enable(&client->dev, 0); + // misc_deregister(&m1120_misc_dev); + sysfs_remove_group(&p_data->input_dev->dev.kobj, &m1120_attribute_group); + m1120_input_dev_terminate(p_data); + if (p_data->igpio != -1) { + gpio_free(p_data->igpio); + } + kfree(p_data); + + return 0; +} + +/* +static int m1120_i2c_drv_suspend(struct i2c_client *client, pm_message_t mesg) +{ + m1120_data_t *p_data = i2c_get_clientdata(client); + + dbg_func_in(); + + mutex_lock(&p_data->mtx.enable); + + if (m1120_get_enable(&client->dev)) { + if (p_data->reg.map.intsrs & M1120_DETECTION_MODE_INTERRUPT) { + m1120_set_operation_mode(&client->dev, OPERATION_MODE_MEASUREMENT); + } else { + cancel_delayed_work_sync(&p_data->work); + m1120_set_detection_mode(&client->dev, M1120_DETECTION_MODE_INTERRUPT); + } + } + + mutex_unlock(&p_data->mtx.enable); + + dbg_func_out(); + + return 0; +} + +static int m1120_i2c_drv_resume(struct i2c_client *client) +{ + m1120_data_t *p_data = i2c_get_clientdata(client); + + dbg_func_in(); + + mutex_lock(&p_data->mtx.enable); + + if (m1120_get_enable(&client->dev)) { + if (p_data->reg.map.intsrs & M1120_DETECTION_MODE_INTERRUPT) { + m1120_set_detection_mode(&client->dev, M1120_DETECTION_MODE_POLLING); + schedule_delayed_work(&p_data->work, msecs_to_jiffies(m1120_get_delay(&client->dev))); + } + } + + mutex_unlock(&p_data->mtx.enable); + + dbg_func_out(); + + return 0; +} +*/ + +static const struct i2c_device_id m1120_i2c_drv_id_table[] = { + {"hall_m1120_up", 0 }, + { } +}; + + +static const struct of_device_id m1120_of_match[] = { + { .compatible = "tri_key_magnachip,tk_mxm1120,up", }, + { }, +}; + +static struct i2c_driver m1120_driver = { + .driver = { + .owner = THIS_MODULE, + .name = M1120_DRIVER_NAME_UP, + .of_match_table = m1120_of_match, + }, + .probe = tri_key_m1120_i2c_drv_probe, + .remove = m1120_i2c_drv_remove, + .id_table = m1120_i2c_drv_id_table, + //.suspend = m1120_i2c_drv_suspend, + //.resume = m1120_i2c_drv_resume, +}; + +static int __init tri_key_m1120_driver_init_up(void) +{ + int res = 0; + printk(KERN_INFO "======>log %s\n", __func__); + res = i2c_add_driver(&m1120_driver); + printk(KERN_INFO "======>log %s, res : %d\n", __func__, res); + return res; +} +module_init(tri_key_m1120_driver_init_up); + +static void __exit m1120_driver_exit_up(void) +{ + printk(KERN_INFO "%s\n", __func__); + i2c_del_driver(&m1120_driver); +} +module_exit(m1120_driver_exit_up); + +MODULE_AUTHOR("shpark "); +MODULE_VERSION(M1120_DRIVER_VERSION); +MODULE_DESCRIPTION("M1120 hallswitch driver"); +MODULE_LICENSE("GPL"); + diff --git a/drivers/extcon/oneplus_tri_key.c b/drivers/extcon/oneplus_tri_key.c new file mode 100644 index 0000000000000000000000000000000000000000..b4d6fa4e5b93c9bfd5a42980789d0fe6ca1d8ae5 --- /dev/null +++ b/drivers/extcon/oneplus_tri_key.c @@ -0,0 +1,1277 @@ +/************************************************************************************ +** Copyright (C), 2013-2018, Oneplus Mobile Comm Corp., Ltd +** File: oneplus_tri_key.c +** +** Description: +** Definitions for m1120 tri_state_key data process. +** +** Version: 1.0 +**************************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#include +#include +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0)) +#include +#endif +#include "oneplus_tri_key.h" +#include "extcon.h" + +enum { + MODE_UNKNOWN, + MODE_MUTE, + MODE_DO_NOT_DISTURB, + MODE_NORMAL, + MODE_MAX_NUM + } tri_mode; + + +unsigned int tristate_extcon_tab[] = { + MODE_MUTE, + MODE_DO_NOT_DISTURB, + MODE_NORMAL, + }; + +static struct hrtimer tri_key_timer; +struct work_struct tri_key_timeout_work; + +static struct extcon_dev_data *g_the_chip = NULL; +static int last_d0 = 0; +static int last_d1 = 0; +static int last_position = -1; +static int last_interf = -1; +static int interf_count; +static int time = 1; +//static int up_buf[20] = {0}; +//static int down_buf[20] = {0}; + +//static short tol0 = 10; +static short tol1 = 15; +static short tol2 = 22; +static short calib_UpValueSum = 0, calib_MdValueSum = 0, calib_DnValueSum = 0; +static short calib_UpValueMin = 0, calib_MdValueMin = 0, calib_DnValueMin = 0; +static short calib_dnHall_UM_distance = 0, calib_dnHall_MD_distance = 0; +static short calib_upHall_UM_distance = 0, calib_upHall_MD_distance = 0; +static short calib_upHall_UD_distance = 0, calib_dnHall_UD_distance = 0; + + + + +int oneplus_register_hall(const char *name, struct dhall_operations *ops) +{ + if (!name || !ops) { + MOTOR_ERR("name is NULL or ops is NULL, would not register digital hall \n"); + return -EINVAL; + } + + if (!g_the_chip) { + struct extcon_dev_data *chip = kzalloc(sizeof(struct extcon_dev_data), GFP_KERNEL); + if (!chip) { + MOTOR_ERR("kzalloc err \n"); + return -ENOMEM; + } + g_the_chip = chip; + } + MOTOR_LOG("name : %s\n", name); + if (strcmp(name, "hall_m1120_down") == 0) { + MOTOR_LOG("name == hall_m1120_down"); + if (!g_the_chip->dhall_down_ops) { + if (ops) { + g_the_chip->dhall_down_ops = ops; + g_the_chip->d_name = name; + } else { + MOTOR_ERR("dhall_down_ops NULL \n"); + return -EINVAL; + } + } else { + MOTOR_ERR("dhall_down_ops has been register \n"); + return -EINVAL; + } + } + if (strcmp(name, "hall_m1120_up") == 0) { + MOTOR_LOG("name == hall_m1120_up"); + if (!g_the_chip->dhall_up_ops) { + if (ops) { + g_the_chip->dhall_up_ops = ops; + g_the_chip->d_name = name; + } else { + MOTOR_ERR("dhall_up_ops NULL \n"); + return -EINVAL; + } + } else { + MOTOR_ERR("dhall_up_ops has been register \n"); + return -EINVAL; + } + } + + return 0; +} + +int oneplus_hall_enable_irq (unsigned int id, bool enable) +{ + if (!g_the_chip) + return -EINVAL; + + switch (id) { + case DHALL_0: + if (!g_the_chip->dhall_down_ops || !g_the_chip->dhall_down_ops->enable_irq) { + return -EINVAL; + } else { + oneplus_hall_clear_irq(DHALL_0); + oneplus_hall_clear_irq(DHALL_1); + return g_the_chip->dhall_down_ops->enable_irq(enable); + } + case DHALL_1: + if (!g_the_chip->dhall_up_ops || !g_the_chip->dhall_up_ops->enable_irq) { + return -EINVAL; + } else { + oneplus_hall_clear_irq(DHALL_0); + oneplus_hall_clear_irq(DHALL_1); + return g_the_chip->dhall_up_ops->enable_irq(enable); + } + default: + MOTOR_ERR("id : %d is not correct\n", id); + return -EINVAL; + } + + return -EINVAL; +} + +int oneplus_hall_clear_irq (unsigned int id) +{ + if (!g_the_chip) + return -EINVAL; + + MOTOR_ERR("dhall_clear_irq\n"); + switch (id) { + case DHALL_0: + if (!g_the_chip->dhall_down_ops || !g_the_chip->dhall_down_ops->enable_irq) { + return -EINVAL; + } else { + return g_the_chip->dhall_down_ops->clear_irq(); + } + case DHALL_1: + if (!g_the_chip->dhall_up_ops || !g_the_chip->dhall_up_ops->enable_irq) { + return -EINVAL; + } else { + return g_the_chip->dhall_up_ops->clear_irq(); + } + default: + MOTOR_ERR("id : %d is not correct\n", id); + return -EINVAL; + } + + return -EINVAL; +} + +int oneplus_hall_get_data(unsigned int id) +{ + if (!g_the_chip) + return -EINVAL; + + switch (id) { + case DHALL_0: + if (!g_the_chip->dhall_down_ops || !g_the_chip->dhall_down_ops->get_data) { + return -EINVAL; + } else { + return g_the_chip->dhall_down_ops->get_data(&g_the_chip->dhall_data0); + } + case DHALL_1: + if (!g_the_chip->dhall_up_ops || !g_the_chip->dhall_up_ops->get_data) { + return -EINVAL; + } else { + return g_the_chip->dhall_up_ops->get_data(&g_the_chip->dhall_data1); + } + default: + MOTOR_ERR("id : %d is not correct\n", id); + return -EINVAL; + } + +} + +bool oneplus_hall_update_threshold(unsigned int id, int position, short lowthd, short highthd) +{ + if (!g_the_chip) + return -EINVAL; + + switch (id) { + case DHALL_0: + if (!g_the_chip->dhall_down_ops || !g_the_chip->dhall_down_ops->update_threshold) { + return false; + } else { + return g_the_chip->dhall_down_ops->update_threshold(position, lowthd, highthd); + } + case DHALL_1: + if (!g_the_chip->dhall_up_ops || !g_the_chip->dhall_up_ops->update_threshold) { + return false; + } else { + return g_the_chip->dhall_up_ops->update_threshold(position, lowthd, highthd); + } + default: + MOTOR_ERR("id : %d is not correct\n", id); + return -EINVAL; + } + +} + +int oneplus_hall_set_detection_mode(unsigned int id, u8 mode) +{ + if (!g_the_chip) + return -EINVAL; + + switch (id) { + case DHALL_0: + if (!g_the_chip->dhall_down_ops || !g_the_chip->dhall_down_ops->set_detection_mode) { + return -EINVAL; + } else { + return g_the_chip->dhall_down_ops->set_detection_mode(mode); + } + case DHALL_1: + if (!g_the_chip->dhall_up_ops || !g_the_chip->dhall_up_ops->set_detection_mode) { + return -EINVAL; + } else { + return g_the_chip->dhall_up_ops->set_detection_mode(mode); + } + default: + MOTOR_ERR("id : %d is not correct\n", id); + return -EINVAL; + } + +} + +int oneplus_hall_get_irq_state(unsigned int id) +{ + if (!g_the_chip) + return -EINVAL; + + switch (id) { + case DHALL_0: + if (!g_the_chip->dhall_down_ops || !g_the_chip->dhall_down_ops->get_irq_state) { + return -EINVAL; + } else { + return g_the_chip->dhall_down_ops->get_irq_state(); + } + case DHALL_1: + if (!g_the_chip->dhall_up_ops || !g_the_chip->dhall_up_ops->get_irq_state) { + return -EINVAL; + } else { + return g_the_chip->dhall_up_ops->get_irq_state(); + } + default: + MOTOR_ERR("id : %d is not correct\n", id); + return -EINVAL; + } + +} + + + +void oneplus_hall_dump_regs(unsigned int id, u8 *buf) +{ + if (!g_the_chip) + return; + + switch (id) { + case DHALL_0: + if (!g_the_chip->dhall_down_ops || !g_the_chip->dhall_down_ops->dump_regs) { + return; + } else { + g_the_chip->dhall_down_ops->dump_regs(buf); + } + break; + case DHALL_1: + if (!g_the_chip->dhall_up_ops || !g_the_chip->dhall_up_ops->dump_regs) { + return; + } else { + g_the_chip->dhall_up_ops->dump_regs(buf); + } + break; + default: + MOTOR_ERR("id : %d is not correct\n", id); + return; + } +} + +int oneplus_hall_set_reg(unsigned int id, int reg, int val) +{ + if (!g_the_chip) + return -EINVAL; + + switch (id) { + case DHALL_0: + if (!g_the_chip->dhall_down_ops || !g_the_chip->dhall_down_ops->set_reg) { + return -EINVAL; + } else { + return g_the_chip->dhall_down_ops->set_reg(reg, val); + } + case DHALL_1: + if (!g_the_chip->dhall_up_ops || !g_the_chip->dhall_up_ops->set_reg) { + return -EINVAL; + } else { + return g_the_chip->dhall_up_ops->set_reg(reg, val); + } + default: + MOTOR_ERR("id : %d is not correct\n", id); + return -EINVAL; + } + +} + +bool oneplus_hall_is_power_on(void) +{ + if (!g_the_chip || !g_the_chip->dhall_down_ops || !g_the_chip->dhall_down_ops->is_power_on + || !g_the_chip->dhall_up_ops || !g_the_chip->dhall_up_ops->is_power_on) { + return false; + } else { + if (g_the_chip->dhall_down_ops->is_power_on() || g_the_chip->dhall_up_ops->is_power_on()) + return true; + else + return false; + } + +} +static void reboot_get_position(struct extcon_dev_data *chip) +{ + short delta; + short up_data1; + short down_data1; + if (chip->dhall_data1 < 0 || chip->dhall_data0 < 0) { + up_data1 = -chip->dhall_data1; + down_data1 = -chip->dhall_data0; + delta = up_data1 - down_data1; + } else + delta = chip->dhall_data1 - chip->dhall_data0; + if (delta > 30) + chip->position = UP_STATE; + else if (-delta > 30) + chip->position = DOWN_STATE; + else + chip->position = MID_STATE; +} + +static int interf_get_position(struct extcon_dev_data *chip) +{ + short delta0; + short delta1; + delta0 = chip->dhall_data0 - last_d0; + delta1 = chip->dhall_data1 - last_d1; + MOTOR_LOG("tri_key: delta0 is %d ,delta1 is %d,last_postion is %d\n", + delta0, delta1, last_position); + if ((delta1 > calib_upHall_UM_distance - tol1 && + delta1 < calib_upHall_UM_distance + tol1) && + (delta0 > calib_dnHall_UM_distance - tol1 && + delta0 < calib_dnHall_UM_distance + tol1)) { + if (last_position == MID_STATE) + return UP_STATE; + } + if ((delta1 > calib_upHall_UD_distance - tol1 && + delta1 < calib_upHall_UD_distance + tol1) && + (delta0 > calib_dnHall_UD_distance - tol1 && + delta0 < calib_dnHall_UD_distance + tol1)) + return UP_STATE; + if ((delta1 > -calib_upHall_MD_distance - tol1 && + delta1 < -calib_upHall_MD_distance + tol1) && + (delta0 > -calib_dnHall_MD_distance - tol1 && + delta0 < -calib_dnHall_MD_distance + tol1)) { + if (last_position == MID_STATE) + return DOWN_STATE; + } + if ((delta1 > -calib_upHall_UD_distance - tol1 && + delta1 < -calib_upHall_UD_distance + tol1) && + (delta0 > -calib_dnHall_UD_distance - tol1 && + delta0 < -calib_dnHall_UD_distance + tol1)) + return DOWN_STATE; + if ((delta1 > -calib_upHall_UM_distance - tol1 && + delta1 < -calib_upHall_UM_distance + tol1) && + (delta0 > -calib_dnHall_UM_distance - tol1 && + delta0 < -calib_dnHall_UM_distance + tol1)) { + if (last_position == UP_STATE) + return MID_STATE; + } + if ((delta1 > calib_upHall_MD_distance - tol1 && + delta1 < calib_upHall_MD_distance + tol1) && + (delta0 > calib_dnHall_MD_distance - tol1 && + delta0 < calib_dnHall_MD_distance + tol1)) { + if (last_position == DOWN_STATE) + return MID_STATE; + } + return -EINVAL; + +} + +static int get_position(struct extcon_dev_data *chip) +{ + short diff; + diff = chip->dhall_data1 - chip->dhall_data0; + if (chip->dhall_data0 > 0) { + if (diff > calib_UpValueMin - tol1 && + diff < calib_UpValueMin + tol2) + chip->position = UP_STATE; + if (calib_MdValueMin < 0) { + if (diff > calib_MdValueMin - tol1 && + diff < calib_MdValueMin + tol1) + chip->position = MID_STATE; + } + if (calib_MdValueMin > 0 || calib_MdValueMin == 0) { + if (diff > calib_MdValueMin - tol1 && + diff < calib_MdValueMin + tol1) + chip->position = MID_STATE; + } + if (diff > calib_DnValueMin - tol2 && + diff < calib_DnValueMin + tol1) + chip->position = DOWN_STATE; + } else { + if (diff > calib_UpValueMin - tol2 && + diff < calib_UpValueMin + tol1) + chip->position = UP_STATE; + if (calib_MdValueMin < 0) { + if (diff > calib_MdValueMin - tol1 && + diff < calib_MdValueMin + tol1) + chip->position = MID_STATE; + } + if (calib_MdValueMin > 0 || calib_MdValueMin == 0) { + if (diff > calib_MdValueMin - tol1 && + diff < calib_MdValueMin + tol1) + chip->position = MID_STATE; + } + if (diff > calib_DnValueMin - tol1 && + diff < calib_DnValueMin + tol2) + chip->position = DOWN_STATE; + } + return 0; +} + +static int judge_interference(struct extcon_dev_data *chip) +{ + short delta; + short sum; + delta = chip->dhall_data1 - chip->dhall_data0; + MOTOR_LOG("tri_key:delta is %d\n", delta); + sum = chip->dhall_data0 + chip->dhall_data1; + MOTOR_LOG("tri_key:sum is %d\n", sum); + if (chip->dhall_data1 > 0) {//the hall data is positive number + if (delta > calib_UpValueMin - tol1 && + delta < calib_UpValueMin + tol2) { + MOTOR_LOG("tri_key:calib_Min:%d,calib_Sum:%d\n", + calib_UpValueMin, calib_UpValueSum); + if (sum < calib_UpValueSum - tol1 || + sum > calib_UpValueSum + tol2) { + chip->interf = 1; + chip->state = 1; + } else { + chip->interf = 0; + chip->state = 1; + } + return 0; + } + if (calib_MdValueMin < 0) { + if (delta > calib_MdValueMin - tol1 && + delta < calib_MdValueMin + tol1) { + MOTOR_LOG("tri_key:calibMin:%d,calib_Sum:%d\n", + calib_MdValueMin, calib_MdValueSum); + + if (sum > calib_MdValueSum + tol2 || + sum < calib_MdValueSum - tol1) { + chip->interf = 1; + chip->state = 2; + } else { + chip->interf = 0; + chip->state = 2; + } + return 0; + } + } + if (calib_MdValueMin > 0 || calib_MdValueMin == 0) { + if (delta > calib_MdValueMin - tol1 && + delta < calib_MdValueMin + tol1) { + MOTOR_LOG("tri_key:calib_Min:%d,calib_Sum:%d\n", + calib_MdValueMin, calib_MdValueSum); + + if (sum > calib_MdValueSum + tol2 || + sum < calib_MdValueSum - tol1) { + chip->interf = 1; + chip->state = 2; + } else { + chip->interf = 0; + chip->state = 2; + } + return 0; + } + } + if (delta > calib_DnValueMin - tol2 && + delta < calib_DnValueMin + tol1) { + MOTOR_LOG("tri_key:calib_Min:%d,calib_Sum:%d\n", + calib_DnValueMin, calib_DnValueSum); + + if (sum < calib_DnValueSum - tol1 || + sum > calib_DnValueSum + tol2) { + chip->interf = 1; + chip->state = 3; + } else { + chip->interf = 0; + chip->state = 3; + } + return 0; + } + chip->interf = 1; + chip->state = 0; + } else {//the hall data is negative number + if (delta > calib_UpValueMin - tol2 && + delta < calib_UpValueMin + tol1) { + MOTOR_LOG("tri_key:calib_Min:%d,calib_Sum:%d\n", + calib_UpValueMin, calib_UpValueSum); + + if (sum < calib_UpValueSum - tol2 || + sum > calib_UpValueSum + tol1) { + chip->interf = 1; + chip->state = 1; + } else { + chip->interf = 0; + chip->state = 1; + } + return 0; + } + if (calib_MdValueMin < 0) { + if (delta > calib_MdValueMin - tol1 && + delta < calib_MdValueMin + tol1) { + MOTOR_LOG("tri_key:calib_Min:%d,calib_Sum:%d\n", + calib_MdValueMin, calib_MdValueSum); + + if (sum > calib_MdValueSum + tol1 || + sum < calib_MdValueSum - tol2) { + chip->interf = 1; + chip->state = 2; + } else { + chip->interf = 0; + chip->state = 2; + } + return 0; + } + } + if (calib_MdValueMin > 0 || calib_MdValueMin == 0) { + if (delta > calib_MdValueMin - tol1 && + delta < calib_MdValueMin + tol1) { + MOTOR_LOG("tri_key:calib_Min:%d,calib_Sum:%d\n", + calib_MdValueMin, calib_MdValueSum); + + if (sum > calib_MdValueSum + tol1 || + sum < calib_MdValueSum - tol2) { + chip->interf = 1; + chip->state = 2; + } else { + chip->interf = 0; + chip->state = 2; + } + return 0; + } + } + if (delta > calib_DnValueMin - tol1 && + delta < calib_DnValueMin + tol2) { + MOTOR_LOG("tri_key:calib_Min:%d,calib_Sum:%d\n", + calib_DnValueMin, calib_DnValueSum); + + if (sum < calib_DnValueSum - tol2 || + sum > calib_DnValueSum + tol1) { + chip->interf = 1; + chip->state = 3; + } else { + chip->interf = 0; + chip->state = 3; + } + return 0; + } + chip->interf = 1; + chip->state = 0; + } + return -EINVAL; + +} + + +static int oneplus_get_data(struct extcon_dev_data *chip) +{ + int res = 0; + mutex_lock(&chip->mtx); + res = oneplus_hall_get_data(DHALL_0); + if (res < 0) + MOTOR_LOG("tri_key:get DHALL_0 data failed,res =%d\n", res); + res = oneplus_hall_get_data(DHALL_1); + if (res < 0) { + MOTOR_LOG("tri_key:get DHALL_1 data failed,res =%d\n", res); + } + mutex_unlock(&chip->mtx); + return res; +} + +static int reupdata_threshold(struct extcon_dev_data *chip) +{ + int res = 0; + int tolen = 22; + switch (chip->position) { + case UP_STATE: + if (chip->dhall_data0 < 0 || chip->dhall_data1 < 0) { + res = oneplus_hall_update_threshold(DHALL_1, UP_STATE, + chip->dhall_data1-tolen, chip->dhall_data1+tolen); + if (res < 0) { + MOTOR_LOG("updata_threshold fail:%d\n", res); + goto fail; + } + MOTOR_LOG("tri_key:updata_threshold up:low:%d,high: %d\n", + chip->dhall_data1-tolen, chip->dhall_data1+tolen); + } else { + res = oneplus_hall_update_threshold(DHALL_1, UP_STATE, + chip->dhall_data1-tolen, chip->dhall_data1+tolen); + if (res < 0) { + MOTOR_LOG("updata_threshold fail:%d\n", res); + goto fail; + } + MOTOR_LOG("tri_key:updata_threshold up:low:%d,high: %d\n", + chip->dhall_data1-tolen, chip->dhall_data1+tolen); + } + oneplus_hall_clear_irq(DHALL_1); + res = oneplus_hall_update_threshold(DHALL_0, UP_STATE, -500, 500); + if (res < 0) { + MOTOR_LOG("updata_threshold fail:%d\n", res); + goto fail; + } + break; + case MID_STATE: + if (chip->dhall_data0 < 0 || chip->dhall_data1 < 0) { + res = oneplus_hall_update_threshold(DHALL_1, MID_STATE, + chip->dhall_data1-tolen, chip->dhall_data1+tolen); + if (res < 0) { + MOTOR_LOG("updata_threshold fail:%d\n", res); + goto fail; + } + MOTOR_LOG("tri_key:updata_threshold up:low:%d,high:%d\n", + chip->dhall_data1-tolen, chip->dhall_data1+tolen); + } else { + res = oneplus_hall_update_threshold(DHALL_1, MID_STATE, + chip->dhall_data1-tolen, chip->dhall_data1+tolen); + if (res < 0) { + MOTOR_LOG("updata_threshold fail:%d\n", res); + goto fail; + } + MOTOR_LOG("tri_key:updata_threshold up:low:%d,high:%d\n", + chip->dhall_data1-tolen, chip->dhall_data1+tolen); + } + oneplus_hall_clear_irq(DHALL_1); + if (chip->dhall_data0 < 0 || chip->dhall_data1 < 0) { + res = oneplus_hall_update_threshold(DHALL_0, MID_STATE, + chip->dhall_data0-tolen, chip->dhall_data0+tolen); + if (res < 0) { + MOTOR_LOG("updata_threshold fail:%d\n", res); + goto fail; + } + MOTOR_LOG("tri_key:updata_threshold down:low:%d,high:%d\n", + chip->dhall_data0-tolen, chip->dhall_data0+tolen); + } else { + res = oneplus_hall_update_threshold(DHALL_0, MID_STATE, + chip->dhall_data0-tolen, chip->dhall_data0+tolen); + if (res < 0) { + MOTOR_LOG("updata_threshold fail:%d\n", res); + goto fail; + } + MOTOR_LOG("tri_key:updata_threshold down:low:%d,high:%d\n", + chip->dhall_data0-tolen, chip->dhall_data0+tolen); + } + oneplus_hall_clear_irq(DHALL_0); + break; + case DOWN_STATE: + res = oneplus_hall_update_threshold(DHALL_1, DOWN_STATE, -500, 500); + if (res < 0) { + MOTOR_LOG("updata_threshold fail:%d\n", res); + goto fail; + } + if (chip->dhall_data0 < 0 || chip->dhall_data1 < 0) { + res = oneplus_hall_update_threshold(DHALL_0, DOWN_STATE, + chip->dhall_data0-tolen, chip->dhall_data0+tolen); + if (res < 0) { + MOTOR_LOG("updata_threshold fail:%d\n", res); + goto fail; + } + MOTOR_LOG("tri_key:updata_threshold down:low:%d,high:%d\n", + chip->dhall_data0-tolen, chip->dhall_data0+tolen); + } else { + res = oneplus_hall_update_threshold(DHALL_0, DOWN_STATE, + chip->dhall_data0-tolen, chip->dhall_data0+tolen); + if (res < 0) { + MOTOR_LOG("updata_threshold fail:%d\n", res); + goto fail; + } + MOTOR_LOG("tri_key:updata_threshold down:low:%d,high:%d\n", + chip->dhall_data0-tolen, chip->dhall_data0+tolen); + } + oneplus_hall_clear_irq(DHALL_0); + break; + } +fail: + last_d0 = chip->dhall_data0; + last_d1 = chip->dhall_data1; + last_interf = chip->interf; + MOTOR_LOG("tri_key:last_d0 is %d ,last_d1 is %d\n", last_d0, last_d1); + oneplus_hall_clear_irq(DHALL_0); + oneplus_hall_clear_irq(DHALL_1); + return res; +} + +static void report_key_value(struct extcon_dev_data *chip) +{ + if (chip->position == DOWN_STATE) { + extcon_set_state_sync(chip->edev, 1, 0); + extcon_set_state_sync(chip->edev, 2, 1); + extcon_set_state_sync(chip->edev, 3, 1); + chip->state = 3; + MOTOR_LOG("tri_key: report down key successful!\n"); + } + if (chip->position == UP_STATE) { //near up hall + extcon_set_state_sync(chip->edev, 1, 1); + extcon_set_state_sync(chip->edev, 2, 1); + extcon_set_state_sync(chip->edev, 3, 0); + chip->state = 1; + MOTOR_LOG("tri_key: report up key successful!\n"); + } + if (chip->position == MID_STATE) { + extcon_set_state_sync(chip->edev, 1, 1); + extcon_set_state_sync(chip->edev, 2, 0); + extcon_set_state_sync(chip->edev, 3, 1); + chip->state = 2; + MOTOR_LOG("tri_key: report mid key successful!\n"); + } else + MOTOR_LOG("no report\n"); +} + +//note:work in irq context +int oneplus_hall_irq_handler(unsigned int id) +{ + MOTOR_LOG("%d tri_key:call :%s\n", id, __func__); + if (!g_the_chip) { + MOTOR_LOG("g_the_chip null\n "); + return -EINVAL; + } else { + schedule_work(&g_the_chip->dwork); + } + return IRQ_HANDLED; +} + + +static void tri_key_dev_work(struct work_struct *work) +{ + struct extcon_dev_data *chip = container_of(work, + struct extcon_dev_data, dwork); + int res = 0; + int position = -1; + int diff0 = 0; + int diff1 = 0; + int count = 0; + int dhall0_sum = 0; + int dhall1_sum = 0; + int aver0 = 0; + int aver1 = 0; + ktime_t starttime, endtime; + u64 usecs64; + int usecs; + + starttime = ktime_get(); +// msleep(50); +//get data + res = oneplus_get_data(chip); + if (res < 0) { + MOTOR_LOG("tri_key:get hall data failed!\n"); + goto fail; + } + MOTOR_LOG("tri_key:data1 is %d, data0 is %d\n", + chip->dhall_data1, chip->dhall_data0); + +//judge interference + res = judge_interference(chip); + MOTOR_LOG("tri_key:chip->interf is %d ,chip->state is %d\n", + chip->interf, chip->state); + if (!last_interf && chip->interf) { + msleep(500); + oneplus_get_data(chip); + MOTOR_LOG("tri_key:data1 is %d, data0 is %d\n", + chip->dhall_data1, chip->dhall_data0); + + judge_interference(chip); + } +//get position + if (!chip->interf) { + hrtimer_cancel(&tri_key_timer); + time = 1; + if (!last_interf) { + interf_count = 0; + get_position(chip); + MOTOR_LOG("tri_key:the position is %d\n", chip->position); + } else { + msleep(50); + oneplus_get_data(chip); + judge_interference(chip); + if (chip->interf) + goto FINAL; + else + get_position(chip); + } + } + else { + hrtimer_cancel(&tri_key_timer); + MOTOR_LOG("tri_key:time0 is %d\n", time); + hrtimer_start(&tri_key_timer, ktime_set(time, 0), + HRTIMER_MODE_REL); + while (count < 4) { + msleep(35); + oneplus_hall_get_data(DHALL_0); + oneplus_hall_get_data(DHALL_1); + dhall0_sum += chip->dhall_data0; + dhall1_sum += chip->dhall_data1; + count++; + } + aver0 = dhall0_sum / 4; + aver1 = dhall1_sum / 4; + if (!last_interf) {//from no interference to constant interference + diff0 = aver0 - chip->dhall_data0; + diff1 = aver1 - chip->dhall_data1; + MOTOR_LOG("tri_key:diff0 is %d,diff1 is %d\n", + diff0, diff1); + if ((diff0 > -10 && diff0 < 10) && (diff1 > -10 && diff1 < 10)) { + chip->position = last_position; + goto UPDATA_HTRES; + } else {//inconstant interference + last_interf = chip->interf; + goto FINAL; + } + } + diff0 = aver0 - chip->dhall_data0; + diff1 = aver1 - chip->dhall_data1; + MOTOR_LOG("tri_key:diff0 is %d,diff1 is %d\n", + diff0, diff1); + +//inconstantly interference + if ((diff0 < -10 || diff0 > 10) && + (diff1 < -10 || diff1 > 10)) { + interf_count++; + if (interf_count == 15) { + MOTOR_LOG("tri_key:count = 15,msleep 5s\n"); + msleep(5000); + interf_count = 0; + goto FINAL; + } + MOTOR_LOG("tri_key:inconstantlt interference\n"); + //last_interf = chip->interf; + reupdata_threshold(chip); + goto FINAL; + } + + chip->dhall_data0 = aver0; + chip->dhall_data1 = aver1; + position = interf_get_position(chip); + if (position == -22) { + MOTOR_LOG("tri_key:get position failed\n"); + } + else + chip->position = position; + } + MOTOR_LOG("tri_key:t_diff0 is %d,t_diff1 is %d\n", + chip->dhall_data0 - last_d0, chip->dhall_data1 - last_d1); +//updata threshold +UPDATA_HTRES: + res = reupdata_threshold(chip); + if (res < 0) { + MOTOR_LOG("tri_key:updata_threshold failed!\n"); + goto fail; + } + mutex_lock(&chip->mtx); +// report key value + if (chip->position == last_position) + goto FINAL; + else { + report_key_value(chip); + last_position = chip->position; + endtime = ktime_get(); + usecs64 = ktime_to_ns(ktime_sub(endtime, starttime)); + do_div(usecs64, NSEC_PER_USEC); + usecs = usecs64; + if (usecs == 0) + usecs = 1; + MOTOR_LOG("report key after %ld.%03ld msecs\n", + usecs / USEC_PER_MSEC, usecs % USEC_PER_MSEC); + } +fail: + if (res < 0) + MOTOR_LOG("tri_key:dev_work failed,res =%d\n", res); +FINAL: + oneplus_hall_enable_irq(DHALL_0, 1); + oneplus_hall_enable_irq(DHALL_1, 1); + MOTOR_LOG("%s achieve\n", __func__); + mutex_unlock(&chip->mtx); +} + +static ssize_t dhall_data_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + //int fb = -1; + //short hall_up_data[128] = {0}; + //short hall_down_data[128] = {0}; + //char hall_data_bufs[512] = {0}; + //char hall_data_buf[16] = {0}; + //int data_count = 0; + //int i = 0; + //int up_sum = 0; + //int down_sum = 0; + if (!g_the_chip) { + MOTOR_ERR("g_the_chip null\n"); + return snprintf(buf, PAGE_SIZE, "%d\n", 0); + } + + oneplus_hall_get_data(DHALL_0); + oneplus_hall_get_data(DHALL_1); +//save hall data +/* hall_up_data[data_count] = g_the_chip->dhall_data0; + hall_down_data[data_count] = g_the_chip->dhall_data1; + data_count++; + fd = sys_open("/sdcard/trikey_hall_data.csv", O_WRONLY | O_CREAT | O_APPEND, 0); + if (fd < 0) { + MOTOR_ERR("open log file /sdcard/hall_data.csv failed.\n"); + } + if (fd >= 0) { +// if (g_the_chip->state) +// sys_write(fd, "1\n", 2); +// else //interference +// sys_write(fd, "0\n", 2); + for (i = 0; i < data_count; i++) { + memset(hall_data_buf, 0, sizeof(hall_data_buf)); + sprintf(hall_data_buf, "%d, ", hall_up_data[i]); + strcat(hall_data_bufs, hall_data_buf); + } + strcat(hall_data_bufs, "\n"); + sys_write(fd, hall_data_bufs, strlen(hall_data_bufs)); + memset(hall_data_bufs, 0 , sizeof(hall_data_bufs)); + + for (i = 0; i < data_count; i++) { + memset(hall_data_buf, 0, sizeof(hall_data_buf)); + sprintf(hall_data_buf, "%d,", hall_down_data[i]); + strcat(hall_data_bufs, hall_data_buf); + } + strcat(hall_data_bufs, "\n"); + sys_write(fd, hall_data_bufs, strlen(hall_data_bufs)); + sys_write(fd, "\n", 1); + sys_close(fd); + } +*/ + + return snprintf(buf, PAGE_SIZE, "%d, %d\n", + g_the_chip->dhall_data0, g_the_chip->dhall_data1); +} + + +static ssize_t tri_state_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + //int position =-1; + if (!g_the_chip) { + MOTOR_ERR("g_the_chip null\n"); + return snprintf(buf, PAGE_SIZE, "%d\n", 0); + } + oneplus_hall_get_data(DHALL_0); + oneplus_hall_get_data(DHALL_1); +// judge_interference(g_the_chip); + //position = get_position(g_the_chip); + + return snprintf(buf, PAGE_SIZE, "%d\n", g_the_chip->state); +} + +static enum hrtimer_restart tri_key_status_timeout(struct hrtimer *timer) +{ + schedule_work(&tri_key_timeout_work); + return HRTIMER_NORESTART; +} + +static void tri_key_timeout_work_func(struct work_struct *work) +{ + oneplus_get_data(g_the_chip); + judge_interference(g_the_chip); + if (g_the_chip->interf) { + time = time * 2; + MOTOR_LOG("tri_key:time1 is %d\n", time); + if (time > 2) + time = 2; + } + else { + get_position(g_the_chip); + if (g_the_chip->position == last_position) + return; + reupdata_threshold(g_the_chip); + report_key_value(g_the_chip); + last_position = g_the_chip->position; + time = 1; + } + return; +} + + +static short Sum(short value0, short value1) +{ + short sum = 0; + sum = value0 + value1; + return sum; +} +static short Minus(short value0, short value1) +{ + short minus = 0; + minus = value0 - value1; + return minus; +} + +void initialCalibValue(short calib_dnHall_UpV, short calib_dnHall_MdV, + short calib_dnHall_DnV, short calib_upHall_UpV, + short calib_upHall_MdV, short calib_upHall_DnV) +{ + calib_UpValueSum = Sum(calib_dnHall_UpV,calib_upHall_UpV); + calib_MdValueSum = Sum(calib_dnHall_MdV,calib_upHall_MdV); + calib_DnValueSum = Sum(calib_dnHall_DnV,calib_upHall_DnV); + calib_UpValueMin = Minus(calib_upHall_UpV,calib_dnHall_UpV); + calib_MdValueMin = Minus(calib_upHall_MdV,calib_dnHall_MdV); + calib_DnValueMin = Minus(calib_upHall_DnV,calib_dnHall_DnV); + calib_upHall_UM_distance = Minus(calib_upHall_UpV, calib_upHall_MdV); + calib_upHall_MD_distance = Minus(calib_upHall_MdV, calib_upHall_DnV); + calib_dnHall_UM_distance = Minus(calib_dnHall_UpV, calib_dnHall_MdV); + calib_dnHall_MD_distance = Minus(calib_dnHall_MdV, calib_dnHall_DnV); + calib_upHall_UD_distance = Minus(calib_upHall_UpV, calib_upHall_DnV); + calib_dnHall_UD_distance = Minus(calib_dnHall_UpV, calib_dnHall_DnV); +} + + +static ssize_t hall_data_calib_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + if (!g_the_chip) { + MOTOR_ERR("g_the_chip null\n"); + return snprintf(buf, PAGE_SIZE, "%d\n%d\n",-1,-1); + } + return snprintf(buf, PAGE_SIZE, "%d,%d,%d,%d,%d,%d\n", + g_the_chip->dnHall_UpV, g_the_chip->upHall_UpV, + g_the_chip->dnHall_MdV, g_the_chip->upHall_MdV, + g_the_chip->dnHall_DnV, g_the_chip->upHall_DnV); +} + +static ssize_t hall_data_calib_store(struct device *pdev, + struct device_attribute *attr, const char *buf, size_t count) +{ + int data[6] = {0}; + char temp[35] = {0}; + if (!g_the_chip) { + MOTOR_ERR("g_the_chip null\n"); + return count; + } + strlcpy(temp, buf, sizeof(temp)); + MOTOR_LOG("temp is %s:\n", temp); + if (sscanf(temp, "%d,%d,%d,%d,%d,%d", &data[0], &data[1], &data[2], + &data[3], &data[4], &data[5]) == 6) { + g_the_chip->dnHall_UpV = data[0]; + g_the_chip->upHall_UpV = data[1]; + g_the_chip->dnHall_MdV = data[2]; + g_the_chip->upHall_MdV = data[3]; + g_the_chip->dnHall_DnV = data[4]; + g_the_chip->upHall_DnV = data[5]; + MOTOR_ERR("data[%d %d %d %d %d %d]\n", data[0], data[1], + data[2], data[3], data[4], data[5]); + } else { + MOTOR_ERR("fail\n"); + } + initialCalibValue(g_the_chip->dnHall_UpV, g_the_chip->dnHall_MdV, + g_the_chip->dnHall_DnV, g_the_chip->upHall_UpV, + g_the_chip->upHall_MdV, g_the_chip->upHall_DnV); + return count; +} + +static DEVICE_ATTR(hall_data, S_IRUGO | S_IWUSR, dhall_data_show, NULL); +static DEVICE_ATTR(tri_state, S_IRUGO | S_IWUSR, tri_state_show, NULL); +static DEVICE_ATTR(hall_data_calib, 0644, + hall_data_calib_show, hall_data_calib_store); + +static struct attribute *tri_key_attributes[] = { + &dev_attr_tri_state.attr, + &dev_attr_hall_data.attr, + &dev_attr_hall_data_calib.attr, + NULL +}; + + +static struct attribute_group tri_key_attribute_group = { + .attrs = tri_key_attributes +}; + +static int tri_key_platform_probe(struct platform_device *pdev) +{ + struct extcon_dev_data *chip = NULL; + int err = 0; + int res = 0; + //int hall_value_min = 0; + + MOTOR_LOG("call %s\n", __func__); + + if (!g_the_chip) { + chip = kzalloc(sizeof(struct extcon_dev_data), GFP_KERNEL); + if (!chip) { + MOTOR_ERR("kzalloc err\n"); + return -ENOMEM; + } + g_the_chip = chip; + } else { + chip = g_the_chip; + } + mutex_init(&chip->mtx); + chip->dev = &pdev->dev; + err = sysfs_create_group(&pdev->dev.kobj, &tri_key_attribute_group); + if (err) { + MOTOR_ERR("tri_key:sysfs_create_group was failed(%d)\n", err); + goto sysfs_create_fail; + } + + if (0 && (!chip->dhall_up_ops || !chip->dhall_down_ops)) { + MOTOR_ERR("no dhall available\n"); + goto fail; + } +// extcon registration + chip->edev = devm_extcon_dev_allocate(chip->dev, tristate_extcon_tab); + chip->edev->name = "tri_state_key"; + err = devm_extcon_dev_register(chip->dev, chip->edev); + + if (err < 0) { + MOTOR_ERR("%s register extcon dev failed\n", __func__); + goto err_extcon_dev_register; + } + + INIT_WORK(&chip->dwork, tri_key_dev_work); + hrtimer_init(&tri_key_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + tri_key_timer.function = tri_key_status_timeout; + INIT_WORK(&tri_key_timeout_work, tri_key_timeout_work_func); +//get data when reboot + res = oneplus_get_data(chip); + if (res < 0) { + MOTOR_LOG("tri_key:get hall data failed!\n"); + goto fail; + } + MOTOR_LOG("tri_key:data1 is %d, data0 is %d\n", + chip->dhall_data1, chip->dhall_data0); + +//get position when reboot + reboot_get_position(chip); +//set threshold when reboot; + err = reupdata_threshold(chip); + if (err < 1) { + MOTOR_ERR("%s reupdata_threshold failed\n", __func__); + goto fail; + } +//report key value + report_key_value(chip); + last_position = chip->position; + err = oneplus_hall_set_detection_mode(DHALL_0, DETECTION_MODE_INTERRUPT); + MOTOR_LOG("tri_key:set 0 detection mode\n"); + if (err < 0) { + MOTOR_ERR("%s set HALL0 detection mode failed %d\n", + __func__, err); + goto fail; + } + err = oneplus_hall_set_detection_mode(DHALL_1, DETECTION_MODE_INTERRUPT); + MOTOR_LOG("tri_key:set 1 detection mode\n"); + if (err < 0) { + MOTOR_ERR("%s set HALL1 detection mode failed %d\n", __func__, err); + goto fail; + } + MOTOR_LOG("%s probe success.\n", __func__); + return 0; + +fail: + kfree(chip); + g_the_chip = NULL; + MOTOR_LOG("fail\n"); + return -EINVAL; +sysfs_create_fail: + sysfs_remove_group(&pdev->dev.kobj, &tri_key_attribute_group); + +err_extcon_dev_register: + devm_extcon_dev_unregister(chip->dev, chip->edev); + MOTOR_LOG("fail\n"); + return -EINVAL; + +} + +static int tri_key_platform_remove(struct platform_device *pdev) +{ + if (g_the_chip) { + cancel_work_sync(&g_the_chip->dwork); + extcon_dev_unregister(g_the_chip->edev); + kfree(g_the_chip); + g_the_chip = NULL; + } + return 0; +} + +static const struct of_device_id tristate_dev_of_match[] = { + { .compatible = "oneplus,hall_tri_state_key"}, + {}, +}; +MODULE_DEVICE_TABLE(of, of_motor_match); + +static struct platform_driver tri_key_platform_driver = { + .probe = tri_key_platform_probe, + .remove = tri_key_platform_remove, + .driver = { + .name = "tri_state_key", + .of_match_table = tristate_dev_of_match, + }, +}; + +static int __init tri_key_platform_init(void) +{ + int res = 0; + MOTOR_LOG("call : %s\n", __func__); + res = platform_driver_register(&tri_key_platform_driver); + if (res < 0) + MOTOR_LOG("%s failed\n", __func__); + return res; +} + +module_init(tri_key_platform_init); + +static void __exit tri_key_platform_exit(void) +{ + platform_driver_unregister(&tri_key_platform_driver); +} +module_exit(tri_key_platform_exit); +MODULE_DESCRIPTION("oem tri_state_key driver"); +MODULE_LICENSE("GPL v2"); + diff --git a/drivers/extcon/oneplus_tri_key.h b/drivers/extcon/oneplus_tri_key.h new file mode 100644 index 0000000000000000000000000000000000000000..879a060d7f49853f0d9de586d58e5dfc43a4f044 --- /dev/null +++ b/drivers/extcon/oneplus_tri_key.h @@ -0,0 +1,126 @@ +/************************************************************************************ +** Copyright (C), 2013-2018, Oneplus Mobile Comm Corp., Ltd +** File: oneplus_tri_key.h +** +** Description: +** Definitions for m1120 tri_state_key data process. +** +** Version: 1.0 +**************************************************************************************/ + +#include +#include + +#define MOTOR_TAG "[tri_state_key] " +#define MOTOR_ERR(fmt, args...) printk(KERN_ERR MOTOR_TAG" %s : "fmt, __FUNCTION__, ##args) +#define MOTOR_LOG(fmt, args...) printk(KERN_INFO MOTOR_TAG" %s : "fmt, __FUNCTION__, ##args) + +/* +#define MODE_MUTE 1 +#define MODE_DO_NOT_DISTURB 2 +#define MODE_NORMAL 3 +*/ +enum dhall_id { + DHALL_0 = 0, + DHALL_1, +}; +// enum dhall_id { +// DHALL_DOWN = 0, +// DHALL_UP, +// }; + +enum dhall_detection_mode { + DETECTION_MODE_POLLING = 0, + DETECTION_MODE_INTERRUPT, + DETECTION_MODE_INVALID, +}; + +enum motor_direction { + MOTOR_DOWN = 0, + MOTOR_UPWARD, +}; + +enum tri_key_position { + UP_STATE, + DOWN_STATE, + MID_STATE, +}; + +extern unsigned int tristate_extcon_tab[]; + + +typedef struct { + short data0; + short data1; +} dhall_data_t; + +struct dhall_operations { + int (*get_data) (short *data); + int (*set_detection_mode) (u8 mode); + int (*enable_irq) (bool enable); + int (*clear_irq) (void); + int (*get_irq_state) (void); + bool (*update_threshold) (int position, short lowthd, short highthd); + void (*dump_regs) (u8 *buf); + int (*set_reg) (int reg, int val); + bool (*is_power_on) (void); +}; + + struct extcon_dev_data { + + struct work_struct dwork; + struct extcon_dev *edev; //change 1 + struct device *dev; + struct timer_list s_timer; + struct pinctrl *key_pinctrl; + struct pinctrl_state *set_state; + struct delayed_work up_work; + struct delayed_work down_work; + struct dhall_operations *dhall_up_ops; + struct dhall_operations *dhall_down_ops; + struct mutex mtx; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 9, 0)) + //struct wake_lock suspend_lock; +#else + //struct wakeup_source *suspend_ws; +#endif + const char *d_name; + const char *m_name; + int position; + int last_position; + int interf;//interference + short state; + short dhall_data0; + short dhall_data1; + short dnHall_UpV; + short dnHall_MdV; + short dnHall_DnV; + short upHall_UpV; + short upHall_MdV; + short upHall_DnV; + //short dnHall_UpV_pre; + //short dnHall_MdV_pre; + //short dnHall_DnV_pre; + //short upHall_UpV_pre; + //short upHall_MdV_pre; + //short upHall_DnV_pre; + int manual2auto_up_switch; + int manual2auto_down_switch; + int irq; + //bool irq_monitor_started; + //bool is_irq_abnormal; +}; + +extern int oneplus_register_hall(const char *name, struct dhall_operations *ops); +//dhall control api +extern int oneplus_hall_get_data(unsigned int id); +extern int oneplus_hall_set_detection_mode(unsigned int id, u8 mode); +extern int oneplus_hall_enable_irq (unsigned int id, bool enable); +extern int oneplus_hall_clear_irq (unsigned int id); +extern int oneplus_hall_irq_handler(unsigned int id); +extern int oneplus_hall_get_irq_state(unsigned int id); +extern void oneplus_hall_dump_regs(unsigned int id, u8 *buf); +extern int oneplus_hall_set_reg(unsigned int id, int reg, int val); +extern bool oneplus_hall_update_threshold(unsigned int id, int position, short lowthd, short highthd); +extern bool oneplus_hall_is_power_on(void); + diff --git a/drivers/extcon/tri_state_key.c b/drivers/extcon/tri_state_key.c new file mode 100644 index 0000000000000000000000000000000000000000..eb48d6e3054b7ab361fb8e2bb87fe8c4ba25a794 --- /dev/null +++ b/drivers/extcon/tri_state_key.c @@ -0,0 +1,393 @@ +/* + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include +#include +#include "extcon.h" +//#include + +#define DRV_NAME "tri-state-key" + +/* + * + * KEY1(GPIO1) KEY2(GPIO92) + * pin1 connect to pin4 0 1 | MUTE + * pin2 connect to pin5 1 1 | Do Not Disturb + * pin4 connect to pin3 1 0 | Normal + */ +enum { + MODE_UNKNOWN, + MODE_MUTE, + MODE_DO_NOT_DISTURB, + MODE_NORMAL, + MODE_MAX_NUM + } tri_mode_t; + +static const unsigned int tristate_extcon_tab[] = { + MODE_MUTE, + MODE_DO_NOT_DISTURB, + MODE_NORMAL, + EXTCON_NONE, +}; + +struct extcon_dev_data { + int irq_key3; + int irq_key2; + int irq_key1; + int key1_gpio; + int key2_gpio; + int key3_gpio; + + struct regulator *vdd_io; + + struct work_struct work; + struct extcon_dev *edev; //change 1 + struct device *dev; + + struct timer_list s_timer; + struct pinctrl *key_pinctrl; + struct pinctrl_state *set_state; + +}; + +static struct extcon_dev_data *extcon_data; +static DEFINE_MUTEX(sem); +static int set_gpio_by_pinctrl(void) +{ + return pinctrl_select_state(extcon_data->key_pinctrl, + extcon_data->set_state); +} +/*op add to fix GCE-7551 begin*/ +extern int aw8697_op_haptic_stop(void); +/*op add to fix GCE-7551 end*/ + +static void extcon_dev_work(struct work_struct *work) +{ + int key[3] = {0, 0, 0}; + int hw_version = 0; + /*op add to fix ISTRACKING-34823 begin*/ + static int pre_key0, pre_key1, pre_key2; + /*op add to fix ISTRACKING-34823 end*/ + /*hw 13 use special tri state key no use key2*/ + //hw_version=get_hw_version(); + pr_err("%s, hw_version=%d\n", + __func__, hw_version); + if (hw_version == 13) { + key[0] = gpio_get_value(extcon_data->key1_gpio); + key[2] = gpio_get_value(extcon_data->key3_gpio); + + pr_err("%s ,key[0]=%d,key[1]=%d,key[2]=%d\n", + __func__, key[0], key[1], key[2]); + if (key[0] == 1 && key[2] == 1) { + extcon_set_state_sync(extcon_data->edev, 1, 1); + extcon_set_state_sync(extcon_data->edev, 2, 0); + extcon_set_state_sync(extcon_data->edev, 3, 1); + } else if (key[0] == 0 && key[2] == 1) { + extcon_set_state_sync(extcon_data->edev, 1, 0); + extcon_set_state_sync(extcon_data->edev, 2, 1); + extcon_set_state_sync(extcon_data->edev, 3, 1); + } else if (key[0] == 1 && key[2] == 0) { + extcon_set_state_sync(extcon_data->edev, 1, 1); + extcon_set_state_sync(extcon_data->edev, 2, 1); + extcon_set_state_sync(extcon_data->edev, 3, 0); + } + } else { + key[0] = gpio_get_value(extcon_data->key1_gpio); + key[1] = gpio_get_value(extcon_data->key2_gpio); + key[2] = gpio_get_value(extcon_data->key3_gpio); + pr_err("%s ,key[0]=%d,key[1]=%d,key[2]=%d\n", + __func__, key[0], key[1], key[2]); + /*op add to fix ISTRACKING-34823 begin*/ + if (!key[0] || !key[1] || !key[2]) { + if (pre_key0 == key[0] && pre_key1 == key[1] + && pre_key2 == key[2]) { + pre_key0 = key[0]; + pre_key1 = key[1]; + pre_key2 = key[2]; + return; + } + } + /*op add to fix ISTRACKING-34823 end*/ + /*op add to fix GCE-7551 begin*/ + if (key[0] && key[1] && key[2]) + return; + if (!key[0] && !key[1] && !key[2]) + return; + if (!key[0] && !key[1] && key[2]) + return; + if (!key[0] && key[1] && !key[2]) + return; + if (key[0] && !key[1] && !key[2]) + return; + /*op add to fix GCE-7551 end*/ + extcon_set_state_sync( + extcon_data->edev, 1, key[0]); + extcon_set_state_sync( + extcon_data->edev, 2, key[1]); + extcon_set_state_sync( + extcon_data->edev, 3, key[2]); + /*op add to fix GCE-7551 begin*/ + if (!key[2] || !key[1]) + aw8697_op_haptic_stop(); + /*op add to fix GCE-7551 end*/ + /*op add to fix ISTRACKING-34823 begin*/ + if (!key[0] || !key[1] || !key[2]) { + pre_key0 = key[0]; + pre_key1 = key[1]; + pre_key2 = key[2]; + } + /*op add to fix ISTRACKING-34823 end*/ + } +} + + +static irqreturn_t extcon_dev_interrupt(int irq, void *_dev) +{ + schedule_work(&extcon_data->work); + return IRQ_HANDLED; +} + +static void timer_handle(unsigned long arg) +{ + schedule_work(&extcon_data->work); +} + +#ifdef CONFIG_OF +static int extcon_dev_get_devtree_pdata(struct device *dev) +{ + struct device_node *node; + + node = dev->of_node; + if (!node) + return -EINVAL; + + extcon_data->key3_gpio = + of_get_named_gpio(node, "tristate,gpio_key3", 0); + if ((!gpio_is_valid(extcon_data->key3_gpio))) + return -EINVAL; + pr_err("extcon_data->key3_gpio=%d\n", extcon_data->key3_gpio); + + extcon_data->key2_gpio = + of_get_named_gpio(node, "tristate,gpio_key2", 0); + if ((!gpio_is_valid(extcon_data->key2_gpio))) + return -EINVAL; + pr_err("extcon_data->key2_gpio=%d\n", extcon_data->key2_gpio); + + extcon_data->key1_gpio = + of_get_named_gpio(node, "tristate,gpio_key1", 0); + if ((!gpio_is_valid(extcon_data->key1_gpio))) + return -EINVAL; + pr_err("extcon_data->key1_gpio=%d\n", extcon_data->key1_gpio); + + return 0; +} +#else +static inline int +extcon_dev_get_devtree_pdata(struct device *dev) +{ + pr_info("%s inline function", __func__); + return 0; +} +#endif + +static int tristate_dev_probe(struct platform_device *pdev) +{ + struct device *dev; + int ret = 0; + + dev = &pdev->dev; + + extcon_data = kzalloc(sizeof(struct extcon_dev_data), GFP_KERNEL); + if (!extcon_data) + return -ENOMEM; + + extcon_data->dev = dev; + + + extcon_data->key_pinctrl = devm_pinctrl_get(extcon_data->dev); + + if (IS_ERR_OR_NULL(extcon_data->key_pinctrl)) { + dev_err(extcon_data->dev, "Failed to get pinctrl\n"); + goto err_extcon_dev_register; + } + extcon_data->set_state = pinctrl_lookup_state(extcon_data->key_pinctrl, + "pmx_tri_state_key_active"); + if (IS_ERR_OR_NULL(extcon_data->set_state)) { + dev_err(extcon_data->dev, "Failed to lookup_state\n"); + goto err_extcon_dev_register; + } + + set_gpio_by_pinctrl(); + + ret = extcon_dev_get_devtree_pdata(dev); + if (ret) { + dev_err(dev, "parse device tree fail!!!\n"); + goto err_extcon_dev_register; + } + + + /* extcon registration */ + extcon_data->edev = + devm_extcon_dev_allocate(extcon_data->dev, tristate_extcon_tab); + extcon_data->edev->name = DRV_NAME; + + ret = devm_extcon_dev_register(extcon_data->dev, extcon_data->edev); + if (ret < 0) + goto err_extcon_dev_register; + + //config irq gpio and request irq + ret = gpio_request(extcon_data->key1_gpio, "tristate_key1"); + if (ret < 0) + goto err_request_gpio; + + ret = gpio_direction_input(extcon_data->key1_gpio); + if (ret < 0) + goto err_set_gpio_input; + + extcon_data->irq_key1 = gpio_to_irq(extcon_data->key1_gpio); + if (extcon_data->irq_key1 < 0) { + ret = extcon_data->irq_key1; + goto err_detect_irq_num_failed; + } + + ret = request_irq(extcon_data->irq_key1, extcon_dev_interrupt, + IRQF_TRIGGER_FALLING|IRQF_TRIGGER_RISING, + "tristate_key1", extcon_data); + if (ret < 0) + goto err_request_irq; + + ret = gpio_request(extcon_data->key2_gpio, + "tristate_key2"); + if (ret < 0) + goto err_request_gpio; + + ret = gpio_direction_input(extcon_data->key2_gpio); + if (ret < 0) + goto err_set_gpio_input; + + extcon_data->irq_key2 = gpio_to_irq(extcon_data->key2_gpio); + if (extcon_data->irq_key2 < 0) { + ret = extcon_data->irq_key2; + goto err_detect_irq_num_failed; + } + + ret = request_irq(extcon_data->irq_key2, extcon_dev_interrupt, + IRQF_TRIGGER_FALLING|IRQF_TRIGGER_RISING, + "tristate_key2", extcon_data); + if (ret < 0) + goto err_request_irq; + + ret = gpio_request(extcon_data->key3_gpio, + "tristate_key3"); + if (ret < 0) + goto err_request_gpio; + + ret = gpio_direction_input(extcon_data->key3_gpio); + if (ret < 0) + goto err_set_gpio_input; + + extcon_data->irq_key3 = gpio_to_irq(extcon_data->key3_gpio); + if (extcon_data->irq_key3 < 0) { + ret = extcon_data->irq_key3; + goto err_detect_irq_num_failed; + } + + ret = request_irq(extcon_data->irq_key3, extcon_dev_interrupt, + IRQF_TRIGGER_FALLING|IRQF_TRIGGER_RISING, + "tristate_key3", extcon_data); + if (ret < 0) + goto err_request_irq; + + INIT_WORK(&extcon_data->work, extcon_dev_work); + + init_timer(&extcon_data->s_timer); + extcon_data->s_timer.function = &timer_handle; + extcon_data->s_timer.expires = jiffies + 5*HZ; + + add_timer(&extcon_data->s_timer); + + enable_irq_wake(extcon_data->irq_key1); + enable_irq_wake(extcon_data->irq_key2); + enable_irq_wake(extcon_data->irq_key3); + + return 0; + +err_request_gpio: + devm_extcon_dev_unregister(extcon_data->dev, extcon_data->edev); +err_request_irq: +err_detect_irq_num_failed: +err_set_gpio_input: + gpio_free(extcon_data->key2_gpio); + gpio_free(extcon_data->key1_gpio); + gpio_free(extcon_data->key3_gpio); +err_extcon_dev_register: + kfree(extcon_data); + + return ret; +} + +static int tristate_dev_remove(struct platform_device *pdev) +{ + cancel_work_sync(&extcon_data->work); + gpio_free(extcon_data->key1_gpio); + gpio_free(extcon_data->key2_gpio); + gpio_free(extcon_data->key3_gpio); + extcon_dev_unregister(extcon_data->edev); + kfree(extcon_data); + + return 0; +} +#ifdef CONFIG_OF +static const struct of_device_id tristate_dev_of_match[] = { + { .compatible = "oneplus, tri-state-key", }, + { }, +}; +MODULE_DEVICE_TABLE(of, tristate_dev_of_match); +#endif + +static struct platform_driver tristate_dev_driver = { + .probe = tristate_dev_probe, + .remove = tristate_dev_remove, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + .of_match_table = tristate_dev_of_match, + }, +}; +static int __init oem_tristate_init(void) +{ + return platform_driver_register(&tristate_dev_driver); +} +module_init(oem_tristate_init); + +static void __exit oem_tristate_exit(void) +{ + platform_driver_unregister(&tristate_dev_driver); +} +module_exit(oem_tristate_exit); +MODULE_DESCRIPTION("oem tri_state_key driver"); +MODULE_LICENSE("GPL v2"); + diff --git a/drivers/firmware/qcom/tz_log.c b/drivers/firmware/qcom/tz_log.c index 8909b31e142f8fc529668e5e43ccab96e812c9a6..57088eca1b64ea9a22b256b520ee829bbbbfdd31 100644 --- a/drivers/firmware/qcom/tz_log.c +++ b/drivers/firmware/qcom/tz_log.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -904,6 +905,96 @@ static void tzdbg_register_qsee_log_buf(struct platform_device *pdev) return; } +//add tz and qsee log to logkit +static ssize_t proc_qsee_log_func(struct file *file, char __user *user_buf, size_t count, loff_t *ppos) +{ + int len = 0; + memcpy_fromio((void *)tzdbg.diag_buf, tzdbg.virt_iobase, + debug_rw_buf_size); + memcpy_fromio((void *)tzdbg.hyp_diag_buf, tzdbg.hyp_virt_iobase, + tzdbg.hyp_debug_rw_buf_size); + len = _disp_qsee_log_stats(count); + *ppos = 0; + + if (len > count) + len = count; + + return simple_read_from_buffer(user_buf, len, ppos, tzdbg.stat[6].data, len); +} + + +static const struct file_operations proc_qsee_log_fops = { + .read = proc_qsee_log_func, + .open = simple_open, + .owner = THIS_MODULE, +}; + +static ssize_t proc_tz_log_func(struct file *file, char __user *user_buf, size_t count, loff_t *ppos) +{ + int len = 0; + memcpy_fromio((void *)tzdbg.diag_buf, tzdbg.virt_iobase, + debug_rw_buf_size); + memcpy_fromio((void *)tzdbg.hyp_diag_buf, tzdbg.hyp_virt_iobase, + tzdbg.hyp_debug_rw_buf_size); + + if (TZBSP_DIAG_MAJOR_VERSION_LEGACY < + (tzdbg.diag_buf->version >> 16)) { + len = _disp_tz_log_stats(count); + *ppos = 0; + } else { + len = _disp_tz_log_stats_legacy(); + } + + if (len > count) + len = count; + + return simple_read_from_buffer(user_buf, len, ppos, tzdbg.stat[5].data, len); +} + +static const struct file_operations proc_tz_log_fops = { + .read = proc_tz_log_func, + .open = simple_open, + .owner = THIS_MODULE, +}; + +static int tzprocfs_init(struct platform_device *pdev) +{ + + int rc = 0; + struct proc_dir_entry *prEntry_tmp = NULL; + struct proc_dir_entry *prEntry_dir = NULL; + + prEntry_dir = proc_mkdir("tzdbg", NULL); + + if (prEntry_dir == NULL) { + dev_err(&pdev->dev, "tzdbg procfs_create_dir failed\n"); + return -ENOMEM; + } + + prEntry_tmp = proc_create("qsee_log", 0666, prEntry_dir, &proc_qsee_log_fops); + + if (prEntry_tmp == NULL) { + dev_err(&pdev->dev, "TZ procfs_create_file qsee_log failed\n"); + rc = -ENOMEM; + goto err; + } + + prEntry_tmp = proc_create("tz_log", 0666, prEntry_dir, &proc_tz_log_fops); + + if (prEntry_tmp == NULL) { + dev_err(&pdev->dev, "TZ procfs_create_file tz_log failed\n"); + rc = -ENOMEM; + goto err; + } + + return 0; +err: + proc_remove(prEntry_dir); + + return rc; +} + + static int tzdbgfs_init(struct platform_device *pdev) { int rc = 0; @@ -1099,6 +1190,11 @@ static int tz_log_probe(struct platform_device *pdev) if (tzdbgfs_init(pdev)) goto err; + //add tz and qsee log to logkit + if (tzprocfs_init(pdev)) + goto err; + + tzdbg_register_qsee_log_buf(pdev); tzdbg_get_tz_version(); diff --git a/drivers/gpu/drm/drm_internal.h b/drivers/gpu/drm/drm_internal.h index fbc3f308fa1997ab5889f3f25fb7357106ea5909..cd92c20783ec60364021e4a17794e2251456569c 100644 --- a/drivers/gpu/drm/drm_internal.h +++ b/drivers/gpu/drm/drm_internal.h @@ -106,6 +106,60 @@ int drm_gem_open_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); void drm_gem_open(struct drm_device *dev, struct drm_file *file_private); void drm_gem_release(struct drm_device *dev, struct drm_file *file_private); +int dsi_display_set_hbm_mode(struct drm_connector *connector, int level); +int dsi_display_get_hbm_mode(struct drm_connector *connector); + + +int dsi_display_get_serial_number(struct drm_connector *connector); +int dsi_display_get_serial_number_year(struct drm_connector *connector); +int dsi_display_get_serial_number_mon(struct drm_connector *connector); +int dsi_display_get_serial_number_day(struct drm_connector *connector); +int dsi_display_get_serial_number_hour(struct drm_connector *connector); +int dsi_display_get_serial_number_min(struct drm_connector *connector); +int dsi_display_set_acl_mode(struct drm_connector *connector, int level); +int dsi_display_get_acl_mode(struct drm_connector *connector); +int dsi_display_set_hbm_mode(struct drm_connector *connector, int level); +int dsi_display_get_hbm_mode(struct drm_connector *connector); +int dsi_display_set_hbm_brightness(struct drm_connector *connector, int level); +int dsi_display_get_hbm_brightness(struct drm_connector *connector); +int dsi_display_set_aod_mode(struct drm_connector *connector, int level); +int dsi_display_get_aod_mode(struct drm_connector *connector); +int dsi_display_set_dci_p3_mode(struct drm_connector *connector, int level); +int dsi_display_get_dci_p3_mode(struct drm_connector *connector); +int dsi_display_set_night_mode(struct drm_connector *connector, int level); +int dsi_display_get_night_mode(struct drm_connector *connector); +int dsi_display_get_serial_number(struct drm_connector *connector); +int dsi_display_get_serial_number_year(struct drm_connector *connector); +int dsi_display_get_serial_number_mon(struct drm_connector *connector); +int dsi_display_get_serial_number_day(struct drm_connector *connector); +int dsi_display_get_serial_number_hour(struct drm_connector *connector); +int dsi_display_get_serial_number_min(struct drm_connector *connector); +int dsi_display_get_serial_number_sec(struct drm_connector *connector); +uint64_t dsi_display_get_serial_number_id(uint64_t serial_number); +int dsi_display_get_stage_info(struct drm_connector *connector); +int dsi_display_get_production_info(struct drm_connector *connector); +int dsi_display_panel_mismatch_check(struct drm_connector *connector); +int dsi_display_panel_mismatch(struct drm_connector *connector); +int dsi_display_set_aod_disable(struct drm_connector *connector, int disable); +int dsi_display_get_aod_disable(struct drm_connector *connector); +int dsi_display_set_fp_hbm_mode(struct drm_connector *connector, int level); +int dsi_display_get_fp_hbm_mode(struct drm_connector *connector); +int dsi_display_update_dsi_on_command(struct drm_connector *connector, const char *buf, size_t count); +int dsi_display_get_dsi_on_command(struct drm_connector *connector, char *buf); +int dsi_display_set_native_display_p3_mode(struct drm_connector *connector, int level); +int dsi_display_get_native_display_p3_mode(struct drm_connector *connector); +int dsi_display_set_native_display_wide_color_mode(struct drm_connector *connector, int level); +int dsi_display_get_native_display_wide_color_mode(struct drm_connector *connector); +int dsi_display_set_native_display_srgb_color_mode(struct drm_connector *connector, int level); +int dsi_display_get_native_display_srgb_color_mode(struct drm_connector *connector); +int dsi_display_set_native_loading_effect_mode(struct drm_connector *connector, int level); +int dsi_display_get_native_display_loading_effect_mode(struct drm_connector *connector); +int dsi_display_set_customer_srgb_mode(struct drm_connector *connector, int level); +int dsi_display_set_customer_p3_mode(struct drm_connector *connector, int level); +int dsi_display_get_customer_srgb_mode(struct drm_connector *connector); +int dsi_display_get_customer_p3_mode(struct drm_connector *connector); +int dsi_display_update_panel_id_and_gamma_para(struct drm_connector *connector); + /* drm_debugfs.c drm_debugfs_crc.c */ #if defined(CONFIG_DEBUG_FS) diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c index 0746ac89fcc59672bd8f15b78f318ce36c11c876..c82db8c5ce6350418189d6de86d01003af1e4674 100644 --- a/drivers/gpu/drm/drm_mipi_dsi.c +++ b/drivers/gpu/drm/drm_mipi_dsi.c @@ -561,8 +561,10 @@ EXPORT_SYMBOL(mipi_dsi_set_maximum_return_packet_size); * Return: The number of bytes transmitted on success or a negative error code * on failure. */ -ssize_t mipi_dsi_generic_write(struct mipi_dsi_device *dsi, const void *payload, - size_t size) +//ssize_t mipi_dsi_generic_write(struct mipi_dsi_device *dsi, const void *payload, +// size_t size) +ssize_t mipi_dsi_generic_write(struct mipi_dsi_device *dsi, void *payload, + size_t size) { struct mipi_dsi_msg msg = { .channel = dsi->channel, @@ -606,8 +608,10 @@ EXPORT_SYMBOL(mipi_dsi_generic_write); * Return: The number of bytes successfully read or a negative error code on * failure. */ -ssize_t mipi_dsi_generic_read(struct mipi_dsi_device *dsi, const void *params, - size_t num_params, void *data, size_t size) +ssize_t mipi_dsi_generic_read(struct mipi_dsi_device *dsi, void *params, + size_t num_params, void *data, size_t size) +//ssize_t mipi_dsi_generic_read(struct mipi_dsi_device *dsi, const void *params, +// size_t num_params, void *data, size_t size) { struct mipi_dsi_msg msg = { .channel = dsi->channel, @@ -650,8 +654,10 @@ EXPORT_SYMBOL(mipi_dsi_generic_read); * Return: The number of bytes successfully transmitted or a negative error * code on failure. */ +//ssize_t mipi_dsi_dcs_write_buffer(struct mipi_dsi_device *dsi, +// const void *data, size_t len) ssize_t mipi_dsi_dcs_write_buffer(struct mipi_dsi_device *dsi, - const void *data, size_t len) + void *data, size_t len) { struct mipi_dsi_msg msg = { .channel = dsi->channel, @@ -1092,6 +1098,42 @@ int mipi_dsi_dcs_get_display_brightness(struct mipi_dsi_device *dsi, return 0; } EXPORT_SYMBOL(mipi_dsi_dcs_get_display_brightness); +/** + * mipi_dsi_dcs_set_display_brightness_samsung() - sets the brightness value of the + * display + * @dsi: DSI peripheral device + * @brightness: brightness value + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_dcs_set_display_brightness_samsung(struct mipi_dsi_device *dsi, + u16 brightness) +{ + u8 payload[2] = {brightness >> 8, brightness & 0xff}; + ssize_t err; + + err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, + payload, sizeof(payload)); + if (err < 0) + return err; + + return 0; +} +EXPORT_SYMBOL(mipi_dsi_dcs_set_display_brightness_samsung); + +int mipi_dsi_dcs_write_c1(struct mipi_dsi_device *dsi, + u16 read_number) +{ + u8 payload[3] = {0x0A, read_number >> 8, read_number & 0xff}; + ssize_t err; + + err = mipi_dsi_dcs_write(dsi, 0xC1,payload, sizeof(payload)); + if (err < 0) + return err; + + return 0; +} +EXPORT_SYMBOL(mipi_dsi_dcs_write_c1); static int mipi_dsi_drv_probe(struct device *dev) { diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c index 4a3f68a33844589ad25a7f02f59c6470c0d2e891..aa927c0fec6d3b0defe6e33c05309e3c67a9bb84 100644 --- a/drivers/gpu/drm/drm_modes.c +++ b/drivers/gpu/drm/drm_modes.c @@ -730,8 +730,8 @@ void drm_mode_set_name(struct drm_display_mode *mode) { bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); - snprintf(mode->name, DRM_DISPLAY_MODE_LEN, "%dx%d%s", - mode->hdisplay, mode->vdisplay, + snprintf(mode->name, DRM_DISPLAY_MODE_LEN, "%dx%d-%d%s", + mode->hdisplay, mode->vdisplay,mode->vrefresh, interlaced ? "i" : ""); } EXPORT_SYMBOL(drm_mode_set_name); diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c old mode 100644 new mode 100755 index 1c5b5ce1fd7f4861f40064cfcaf73963ebd0fcee..a8645545eba503e66720deb165cc4b4e7d21d950 --- a/drivers/gpu/drm/drm_sysfs.c +++ b/drivers/gpu/drm/drm_sysfs.c @@ -21,10 +21,20 @@ #include #include #include "drm_internal.h" +#include +#include +#include +#include +#include +#include +#include #define to_drm_minor(d) dev_get_drvdata(d) #define to_drm_connector(d) dev_get_drvdata(d) +#define DSI_PANEL_SAMSUNG_S6E3HC2 0 +extern char gamma_para[2][413]; +extern char dsi_panel_name; /** * DOC: overview * @@ -228,17 +238,864 @@ static ssize_t modes_show(struct device *device, return written; } +static ssize_t acl_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int acl_mode = 0; + + acl_mode = dsi_display_get_acl_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "acl mode = %d\n" + "0--acl mode(off)\n" + "1--acl mode(5)\n" + "2--acl mode(10)\n" + "3--acl mode(15)\n", + acl_mode); + return ret; +} + +static ssize_t acl_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int acl_mode = 0; + + ret = kstrtoint(buf, 10, &acl_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_acl_mode(connector, acl_mode); + if (ret) + pr_err("set acl mode(%d) fail\n", acl_mode); + + return count; +} +static ssize_t hbm_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int hbm_mode = 0; + + hbm_mode = dsi_display_get_hbm_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "hbm mode = %d\n" + "0--hbm mode(off)\n" + "1--hbm mode(XX)\n" + "2--hbm mode(XX)\n" + "3--hbm mode(XX)\n" + "4--hbm mode(XX)\n" + "5--hbm mode(670)\n", + hbm_mode); + return ret; +} + +static ssize_t hbm_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int hbm_mode = 0; + + ret = kstrtoint(buf, 10, &hbm_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_hbm_mode(connector, hbm_mode); + if (ret) + pr_err("set hbm mode(%d) fail\n", hbm_mode); + + return count; +} + +static ssize_t hbm_brightness_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int hbm_brightness = 0; + + hbm_brightness = dsi_display_get_hbm_brightness(connector); + + ret = scnprintf(buf, PAGE_SIZE, "%d\n", hbm_brightness); + return ret; +} + +static ssize_t hbm_brightness_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int hbm_brightness = 0; + + ret = kstrtoint(buf, 10, &hbm_brightness); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + ret = dsi_display_set_hbm_brightness(connector, hbm_brightness); + if (ret) + pr_err("set hbm brightness (%d) failed\n", hbm_brightness); + return count; +} + +static ssize_t op_friginer_print_hbm_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int op_hbm_mode = 0; + + op_hbm_mode = dsi_display_get_fp_hbm_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "OP_FP mode = %d\n" + "0--finger-hbm mode(off)\n" + "1--finger-hbm mode(600)\n", + op_hbm_mode); + return ret; +} + +static ssize_t op_friginer_print_hbm_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int op_hbm_mode = 0; + + ret = kstrtoint(buf, 10, &op_hbm_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_fp_hbm_mode(connector, op_hbm_mode); + if (ret) + pr_err("set hbm mode(%d) fail\n", op_hbm_mode); + + return count; +} + +static ssize_t aod_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int aod_mode = 0; + + aod_mode = dsi_display_get_aod_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "%d\n", aod_mode); + return ret; +} + +static ssize_t aod_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int aod_mode = 0; + + ret = kstrtoint(buf, 10, &aod_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + ret = dsi_display_set_aod_mode(connector, aod_mode); + if (ret) + pr_err("set AOD mode(%d) fail\n", aod_mode); + return count; +} + +static ssize_t aod_disable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int aod_disable = 0; + + aod_disable = dsi_display_get_aod_disable(connector); + + ret = scnprintf(buf, PAGE_SIZE, "AOD disable = %d\n" + "0--AOD enable\n" + "1--AOD disable\n", + aod_disable); + return ret; +} + +static ssize_t aod_disable_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int aod_disable = 0; + + ret = kstrtoint(buf, 10, &aod_disable); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_aod_disable(connector, aod_disable); + if (ret) + pr_err("set AOD disable(%d) fail\n", aod_disable); + + return count; +} + +static ssize_t DCI_P3_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int dci_p3_mode = 0; + + dci_p3_mode = dsi_display_get_dci_p3_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "dci-p3 mode = %d\n" + "0--dci-p3 mode Off\n" + "1--dci-p3 mode On\n", + dci_p3_mode); + return ret; +} + +static ssize_t DCI_P3_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int dci_p3_mode = 0; + + ret = kstrtoint(buf, 10, &dci_p3_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_dci_p3_mode(connector, dci_p3_mode); + if (ret) { + pr_err("set dci-p3 mode(%d) fail\n", dci_p3_mode); + } + return count; +} + +static ssize_t night_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int night_mode = 0; + + night_mode = dsi_display_get_night_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "night mode = %d\n" + "0--night mode Off\n" + "1--night mode On\n", + night_mode); + return ret; +} + +static ssize_t night_mode_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int night_mode = 0; + + ret = kstrtoint(buf, 10, &night_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_night_mode(connector, night_mode); + if (ret) { + pr_err("set night mode(%d) fail\n", night_mode); + } + return count; +} + +static ssize_t native_display_p3_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_p3_mode = 0; + + native_display_p3_mode = dsi_display_get_native_display_p3_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "native display p3 mode = %d\n" + "0--native display p3 mode Off\n" + "1--native display p3 mode On\n", + native_display_p3_mode); + return ret; +} + +static ssize_t native_display_p3_mode_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_p3_mode = 0; + + ret = kstrtoint(buf, 10, &native_display_p3_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_native_display_p3_mode(connector, native_display_p3_mode); + if (ret) { + pr_err("set native_display_p3 mode(%d) fail\n", native_display_p3_mode); + } + return count; +} +static ssize_t native_display_wide_color_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_wide_color_mode = 0; + + native_display_wide_color_mode = dsi_display_get_native_display_wide_color_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "native display wide color mode = %d\n" + "0--native display wide color mode Off\n" + "1--native display wide color mode On\n", + native_display_wide_color_mode); + return ret; +} + +static ssize_t native_display_loading_effect_mode_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_loading_effect_mode = 0; + + ret = kstrtoint(buf, 10, &native_display_loading_effect_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_native_loading_effect_mode(connector, native_display_loading_effect_mode); + if (ret) { + pr_err("set loading effect mode(%d) fail\n", native_display_loading_effect_mode); + } + return count; +} + +static ssize_t native_display_loading_effect_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_loading_effect_mode = 0; + + native_display_loading_effect_mode = dsi_display_get_native_display_loading_effect_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "native display loading effect mode = %d\n" + "0--native display loading effect mode Off\n" + "1--native display loading effect mode On\n", + native_display_loading_effect_mode); + return ret; +} + +static ssize_t native_display_customer_p3_mode_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_customer_p3_mode = 0; + + ret = kstrtoint(buf, 10, &native_display_customer_p3_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_customer_p3_mode(connector, native_display_customer_p3_mode); + if (ret) { + pr_err("set customer p3 mode(%d) fail\n", native_display_customer_p3_mode); + } + return count; +} + +static ssize_t native_display_customer_p3_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_customer_p3_mode = 0; + + native_display_customer_p3_mode = dsi_display_get_customer_p3_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "native display customer p3 mode = %d\n" + "0--native display customer p3 mode Off\n" + "1--native display customer p3 mode On\n", + native_display_customer_p3_mode); + return ret; +} +static ssize_t native_display_customer_srgb_mode_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_customer_srgb_mode = 0; + + ret = kstrtoint(buf, 10, &native_display_customer_srgb_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_customer_srgb_mode(connector, native_display_customer_srgb_mode); + if (ret) { + pr_err("set customer srgb mode(%d) fail\n", native_display_customer_srgb_mode); + } + return count; +} + +static ssize_t native_display_customer_srgb_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_customer_srgb_mode = 0; + + native_display_customer_srgb_mode = dsi_display_get_customer_srgb_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "native display customer srgb mode = %d\n" + "0--native display customer srgb mode Off\n" + "1--native display customer srgb mode On\n", + native_display_customer_srgb_mode); + return ret; +} + + +static ssize_t native_display_wide_color_mode_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_wide_color_mode = 0; + + ret = kstrtoint(buf, 10, &native_display_wide_color_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_native_display_wide_color_mode(connector, native_display_wide_color_mode); + if (ret) { + pr_err("set native_display_p3 mode(%d) fail\n", native_display_wide_color_mode); + } + return count; +} + +static ssize_t native_display_srgb_color_mode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_srgb_color_mode = 0; + + native_display_srgb_color_mode = dsi_display_get_native_display_srgb_color_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "native display srgb color mode = %d\n" + "0--native display srgb color mode Off\n" + "1--native display srgb color mode On\n", + native_display_srgb_color_mode); + return ret; +} + +static ssize_t native_display_srgb_color_mode_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int native_display_srgb_color_mode = 0; + + ret = kstrtoint(buf, 10, &native_display_srgb_color_mode); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_native_display_srgb_color_mode(connector, native_display_srgb_color_mode); + if (ret) { + pr_err("set native_display_srgb mode(%d) fail\n", native_display_srgb_color_mode); + } + return count; +} + +static ssize_t gamma_test_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int gamma_test_flag = 0; + int panel_stage_info = 0; + int pvt_mp_panel_flag = 0; + + ret = dsi_display_update_panel_id_and_gamma_para(connector); + if (ret) { + pr_err("Failed to update panel id and gamma para!\n"); + } + + if (dsi_panel_name == DSI_PANEL_SAMSUNG_S6E3HC2) { + if ((gamma_para[0][18] == 0xFF) && (gamma_para[0][19] == 0xFF) && (gamma_para[0][20] == 0xFF)) { + gamma_test_flag = 0; + } + else { + gamma_test_flag = 1; + } + + panel_stage_info = dsi_display_get_stage_info(connector); + if ((0x07 == panel_stage_info) || (0x10 == panel_stage_info) || (0x11 == panel_stage_info)) { + pvt_mp_panel_flag = 1; + } + else { + pvt_mp_panel_flag = 0; + } + + ret = scnprintf(buf, PAGE_SIZE, "%d\n", (gamma_test_flag << 1) + pvt_mp_panel_flag); + return ret; + } + else { + ret = scnprintf(buf, PAGE_SIZE, "%d\n", 3); + pr_err("It is not S6E3HC2 panel!\n"); + return ret; + } +} + +static ssize_t panel_serial_number_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int panel_year = 0; + int panel_mon = 0; + int panel_day = 0; + int panel_hour = 0; + int panel_min = 0; + int panel_sec = 0; + int panel_stage_info = 0; + int panel_production_info = 0; + char * production_string_info = NULL; + char * stage_string_info = NULL; + int ret = 0; + + + dsi_display_get_serial_number(connector); + + panel_year = dsi_display_get_serial_number_year(connector); + panel_mon = dsi_display_get_serial_number_mon(connector); + panel_day = dsi_display_get_serial_number_day(connector); + panel_hour = dsi_display_get_serial_number_hour(connector); + panel_min = dsi_display_get_serial_number_min(connector); + panel_sec = dsi_display_get_serial_number_sec(connector); + panel_stage_info = dsi_display_get_stage_info(connector); + panel_production_info = dsi_display_get_production_info(connector); + + if (0x02 == panel_stage_info) { + stage_string_info = "STAGE: EVT2"; + } + else if (0x03 == panel_stage_info) { + stage_string_info = "STAGE: EVT2(NEW_DIMMING_SET)"; + } + else if (0x99 == panel_stage_info) { + stage_string_info = "STAGE: EVT2(113MHZ_OSC)"; + } + else if (0x04 == panel_stage_info) { + stage_string_info = "STAGE: DVT1"; + } + else if (0x05 == panel_stage_info) { + stage_string_info = "STAGE: DVT2"; + } + else if (0x06 == panel_stage_info) { + stage_string_info = "STAGE: DVT3"; + } + else if (0x07 == panel_stage_info) { + stage_string_info = "STAGE: PVT(112MHZ_OSC)"; + } + else if (0x10 == panel_stage_info) { + stage_string_info = "STAGE: PVT(113MHZ_OSC)"; + } + else if (0x11 == panel_stage_info) { + stage_string_info = "STAGE: PVT(113MHZ_OSC+X_TALK_IMPROVEMENT)"; + } + else { + stage_string_info = "STAGE: UNKNOWN"; + } + + if (0x0C == panel_production_info) { + production_string_info = "TPIC: LSI\nCOVER: JNTC\nOTP_GAMMA: 90HZ"; + } + else if (0x0E == panel_production_info) { + production_string_info = "TPIC: LSI\nCOVER: LENS\nOTP_GAMMA: 90HZ"; + } + else if (0x1C == panel_production_info) { + production_string_info = "TPIC: STM\nCOVER: JNTC\nOTP_GAMMA: 90HZ"; + } + else if (0x6C == panel_production_info) { + production_string_info = "TPIC: LSI\nCOVER: JNTC\nOTP_GAMMA: 60HZ"; + } + else if (0x6E == panel_production_info) { + production_string_info = "TPIC: LSI\nCOVER: LENS\nOTP_GAMMA: 60HZ"; + } + else if (0x1E == panel_production_info) { + production_string_info = "TPIC: STM\nCOVER: LENS\nOTP_GAMMA: 90HZ"; + } + else if (0x0D == panel_production_info) { + production_string_info = "TPIC: LSI\nID3: 0x0D\nOTP_GAMMA: 90HZ"; + } + else { + production_string_info = "TPIC: UNKNOWN\nCOVER: UNKNOWN\nOTP_GAMMA: UNKNOWN"; + } + + if((0xff ==panel_stage_info) && (0xff == panel_production_info)) + ret = scnprintf(buf, PAGE_SIZE, "%04d/%02d/%02d %02d:%02d:%02d\n", + panel_year, + panel_mon, + panel_day, + panel_hour, + panel_min, + panel_sec); + else + ret = scnprintf(buf, PAGE_SIZE, "%04d/%02d/%02d %02d:%02d:%02d\n%s\n%s\n", + panel_year, + panel_mon, + panel_day, + panel_hour, + panel_min, + panel_sec, + stage_string_info, + production_string_info); + + pr_err("panel year = %d, mon = %d, day = %d, hour = %d, min = %d\n", + panel_year, panel_mon, panel_day, panel_hour, panel_min); + + return ret; +} + +static ssize_t panel_serial_number_AT_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + + int ret = 0; + uint64_t serial_number = 0; + + ret = scnprintf(buf, PAGE_SIZE, "%llu\n",dsi_display_get_serial_number_id(serial_number)); + + return ret; +} + +static ssize_t dsi_on_command_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + + ret = dsi_display_get_dsi_on_command(connector, buf); + + return ret; +} + +static ssize_t dsi_on_command_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + + ret = dsi_display_update_dsi_on_command(connector, buf, count); + if (ret) + pr_err("Failed to update dsi on command, ret=%d\n", ret); + + return count; +} + +int current_freq = 0; +static ssize_t dynamic_dsitiming_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int ret = 0; + + ret = scnprintf(buf, PAGE_SIZE, "current_freq = %d\n", + current_freq); + return ret; +} + +static ssize_t dynamic_dsitiming_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + int ret = 0; + int freq_value = 0; + + ret = kstrtoint(buf, 10, &freq_value); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + current_freq = freq_value; + + pr_err("freq setting=%d\n", current_freq); + + if (ret) { + pr_err("set dsi freq (%d) fail\n", current_freq); + } + return count; +} + +static ssize_t panel_mismatch_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + int wrong_panel = 0; + + dsi_display_panel_mismatch_check(connector); + + wrong_panel = dsi_display_panel_mismatch(connector); + ret = scnprintf(buf, PAGE_SIZE, "panel mismatch = %d\n" + "0--(panel match)\n" + "1--(panel mismatch)\n", + wrong_panel); + return ret; +} + +int oneplus_panel_alpha =0; +int oneplus_force_screenfp = 0; +extern int oneplus_get_panel_brightness_to_alpha(void); + +static ssize_t oneplus_display_get_dim_alpha(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", oneplus_get_panel_brightness_to_alpha()); +} + +static ssize_t oneplus_display_set_dim_alpha(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + sscanf(buf, "%d", &oneplus_panel_alpha); + return count; +} + +static ssize_t oneplus_display_get_forcescreenfp(struct device *dev, + struct device_attribute *attr, char *buf) +{ + + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + oneplus_force_screenfp = dsi_display_get_fp_hbm_mode(connector); + + ret = scnprintf(buf, PAGE_SIZE, "OP_FP mode = %d\n" + "0--finger-hbm mode(off)\n" + "1--finger-hbm mode(600)\n", + oneplus_force_screenfp); + return sprintf(buf, "%d\n", oneplus_force_screenfp); + +} + +static ssize_t oneplus_display_set_forcescreenfp(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + //sscanf(buf, "%x", &oneplus_force_screenfp); + struct drm_connector *connector = to_drm_connector(dev); + int ret = 0; + ret = kstrtoint(buf, 10, &oneplus_force_screenfp); + if (ret) { + pr_err("kstrtoint failed. ret=%d\n", ret); + return ret; + } + + ret = dsi_display_set_fp_hbm_mode(connector, oneplus_force_screenfp); + if (ret) + pr_err("set hbm mode(%d) fail\n", oneplus_force_screenfp); + return count; +} + +extern ssize_t oneplus_display_notify_fp_press(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count); + +extern ssize_t oneplus_display_notify_dim(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count); + +extern ssize_t oneplus_display_notify_aod_hid(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count); static DEVICE_ATTR_RW(status); static DEVICE_ATTR_RO(enabled); static DEVICE_ATTR_RO(dpms); static DEVICE_ATTR_RO(modes); +static DEVICE_ATTR_RW(acl); +static DEVICE_ATTR_RW(hbm); +static DEVICE_ATTR_RW(hbm_brightness); +static DEVICE_ATTR_RW(op_friginer_print_hbm); +static DEVICE_ATTR_RW(aod); +static DEVICE_ATTR_RW(aod_disable); +static DEVICE_ATTR_RW(DCI_P3); +static DEVICE_ATTR_RW(night_mode); +static DEVICE_ATTR_RW(native_display_p3_mode); +static DEVICE_ATTR_RW(native_display_wide_color_mode); +static DEVICE_ATTR_RW(native_display_loading_effect_mode); +static DEVICE_ATTR_RW(native_display_srgb_color_mode); +static DEVICE_ATTR_RW(native_display_customer_p3_mode); +static DEVICE_ATTR_RW(native_display_customer_srgb_mode); +static DEVICE_ATTR_RO(gamma_test); +static DEVICE_ATTR_RO(panel_serial_number); +static DEVICE_ATTR_RO(panel_serial_number_AT); +static DEVICE_ATTR_RW(dsi_on_command); +static DEVICE_ATTR_RW(dynamic_dsitiming); +static DEVICE_ATTR_RO(panel_mismatch); +static DEVICE_ATTR(dim_alpha, S_IRUGO|S_IWUSR, oneplus_display_get_dim_alpha, oneplus_display_set_dim_alpha); +static DEVICE_ATTR(force_screenfp, S_IRUGO|S_IWUSR, oneplus_display_get_forcescreenfp, oneplus_display_set_forcescreenfp); +static DEVICE_ATTR(notify_fppress, S_IRUGO|S_IWUSR, NULL, oneplus_display_notify_fp_press); +static DEVICE_ATTR(notify_dim, S_IRUGO|S_IWUSR, NULL, oneplus_display_notify_dim); +static DEVICE_ATTR(notify_aod, S_IRUGO|S_IWUSR, NULL, oneplus_display_notify_aod_hid); static struct attribute *connector_dev_attrs[] = { &dev_attr_status.attr, &dev_attr_enabled.attr, &dev_attr_dpms.attr, &dev_attr_modes.attr, + &dev_attr_acl.attr, + &dev_attr_hbm.attr, + &dev_attr_hbm_brightness.attr, + &dev_attr_op_friginer_print_hbm.attr, + &dev_attr_aod.attr, + &dev_attr_aod_disable.attr, + &dev_attr_DCI_P3.attr, + &dev_attr_night_mode.attr, + &dev_attr_native_display_p3_mode.attr, + &dev_attr_native_display_wide_color_mode.attr, + &dev_attr_native_display_loading_effect_mode.attr, + &dev_attr_native_display_srgb_color_mode.attr, + &dev_attr_native_display_customer_p3_mode.attr, + &dev_attr_native_display_customer_srgb_mode.attr, + &dev_attr_gamma_test.attr, + &dev_attr_panel_serial_number.attr, + &dev_attr_panel_serial_number_AT.attr, + &dev_attr_dsi_on_command.attr, + &dev_attr_dynamic_dsitiming.attr, + &dev_attr_panel_mismatch.attr, + &dev_attr_force_screenfp.attr, + &dev_attr_dim_alpha.attr, + &dev_attr_notify_fppress.attr, + &dev_attr_notify_dim.attr, + &dev_attr_notify_aod.attr, NULL }; diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c index 3219628f95a7dae58df78e11220993dcfb39d623..709935a39ac526bf6133f0175cfb0390354795e8 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.c +++ b/drivers/gpu/drm/msm/dp/dp_parser.c @@ -711,7 +711,7 @@ static int dp_parser_mst(struct dp_parser *parser) "qcom,mst-enable"); parser->has_mst_sideband = parser->has_mst; - pr_debug("mst parsing successful. mst:%d\n", parser->has_mst); + pr_err("mst parsing successful. mst:%d\n", parser->has_mst); return 0; } diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c index b03e46a136b684cfd73572818d862726f1b91887..33afaa047bc9e4caa73e3f33eed05ab2862b6b36 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -71,6 +71,8 @@ static void dsi_catalog_cmn_init(struct dsi_ctrl_hw *ctrl, dsi_ctrl_hw_cmn_wait_for_cmd_mode_mdp_idle; ctrl->ops.setup_avr = dsi_ctrl_hw_cmn_setup_avr; ctrl->ops.set_continuous_clk = dsi_ctrl_hw_cmn_set_continuous_clk; + ctrl->ops.wait4dynamic_refresh_done = + dsi_ctrl_hw_cmn_wait4dynamic_refresh_done; switch (version) { case DSI_CTRL_VERSION_1_4: @@ -226,6 +228,14 @@ static void dsi_catalog_phy_3_0_init(struct dsi_phy_hw *phy) phy->ops.clamp_ctrl = dsi_phy_hw_v3_0_clamp_ctrl; phy->ops.phy_lane_reset = dsi_phy_hw_v3_0_lane_reset; phy->ops.toggle_resync_fifo = dsi_phy_hw_v3_0_toggle_resync_fifo; + phy->ops.dyn_refresh_ops.dyn_refresh_config = + dsi_phy_hw_v3_0_dyn_refresh_config; + phy->ops.dyn_refresh_ops.dyn_refresh_pipe_delay = + dsi_phy_hw_v3_0_dyn_refresh_pipe_delay; + phy->ops.dyn_refresh_ops.dyn_refresh_helper = + dsi_phy_hw_v3_0_dyn_refresh_helper; + phy->ops.dyn_refresh_ops.cache_phy_timings = + dsi_phy_hw_v3_0_cache_phy_timings; } /** diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h index e6c148ba12d45861660af1715a115370d8e685dc..5e8921faa058687ab1e8c7b67afc8882beb77570 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -66,15 +66,17 @@ int dsi_phy_timing_calc_init(struct dsi_phy_hw *phy, * @mode: DSI mode information. * @host: DSI host configuration. * @timing: DSI phy lane configurations. + * @use_mode_bit_clk: Boolean to indicate whether to recalculate bit clk. * * This function setups the catalog information in the dsi_phy_hw object. * * return: error code for failure and 0 for success. */ int dsi_phy_hw_calculate_timing_params(struct dsi_phy_hw *phy, - struct dsi_mode_info *mode, - struct dsi_host_common_cfg *host, - struct dsi_phy_per_lane_cfgs *timing); + struct dsi_mode_info *mode, + struct dsi_host_common_cfg *host, + struct dsi_phy_per_lane_cfgs *timing, + bool use_mode_bit_clk); /* Definitions for 14nm PHY hardware driver */ void dsi_phy_hw_v2_0_regulator_enable(struct dsi_phy_hw *phy, @@ -248,4 +250,14 @@ void dsi_ctrl_hw_22_config_clk_gating(struct dsi_ctrl_hw *ctrl, bool enable, void dsi_ctrl_hw_cmn_set_continuous_clk(struct dsi_ctrl_hw *ctrl, bool enable); +/* dynamic refresh specific functions */ +void dsi_phy_hw_v3_0_dyn_refresh_helper(struct dsi_phy_hw *phy, u32 offset); +void dsi_phy_hw_v3_0_dyn_refresh_config(struct dsi_phy_hw *phy, + struct dsi_phy_cfg *cfg, bool is_master); +void dsi_phy_hw_v3_0_dyn_refresh_pipe_delay(struct dsi_phy_hw *phy, + struct dsi_dyn_clk_delay *delay); + +int dsi_ctrl_hw_cmn_wait4dynamic_refresh_done(struct dsi_ctrl_hw *ctrl); +int dsi_phy_hw_v3_0_cache_phy_timings(struct dsi_phy_per_lane_cfgs *timings, + u32 *dst, u32 size); #endif /* _DSI_CATALOG_H_ */ diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_clk.h b/drivers/gpu/drm/msm/dsi-staging/dsi_clk.h index 721a71705a7182f045d1bda9ec1c49ce8463e779..7c2461bb46c1e93e5304a2bc8f94c44a64d318ef 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_clk.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_clk.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -261,13 +261,13 @@ void *dsi_register_clk_handle(void *clk_mngr, char *client); int dsi_deregister_clk_handle(void *client); /** - * dsi_display_link_clk_force_update_ctrl() - force to set link clks + * dsi_display_link_clk_force_update() - force to set link clks * @handle: Handle of desired DSI clock client. * * return: error code in case of failure or 0 for success. */ -int dsi_display_link_clk_force_update_ctrl(void *handle); +int dsi_display_link_clk_force_update(void *handle); /** * dsi_display_clk_ctrl() - set frequencies for link clks @@ -318,4 +318,28 @@ int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index); */ int dsi_clk_update_parent(struct dsi_clk_link_set *parent, struct dsi_clk_link_set *child); +/** + * dsi_clk_req_state() - request to change dsi clock state + * @client: DSI clocl client pointer. + * @clk: DSI clock list. + * @state: Requested state of the clock. + */ + /** + * dsi_clk_prepare_enable() - prepare and enable dsi src clocks + * @clk: list of src clocks. + * + * @return: Zero on success and err no on failure + */ +int dsi_clk_prepare_enable(struct dsi_clk_link_set *clk); + +/** + * dsi_clk_disable_unprepare() - disable and unprepare dsi src clocks + * @clk: list of src clocks. + */ +void dsi_clk_disable_unprepare(struct dsi_clk_link_set *clk); + +int dsi_clk_req_state(void *client, enum dsi_clk_type clk, + enum dsi_clk_state state); + + #endif /* _DSI_CLK_H_ */ diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c b/drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c index 5d6808bf1b1652361771b638ca23721f5b5e08dc..2faccadd829c83a7844deb4aa35f9e6f72b122da 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -113,8 +113,9 @@ int dsi_clk_set_link_frequencies(void *client, struct link_clk_freq freq, /** * dsi_clk_set_pixel_clk_rate() - set frequency for pixel clock - * @clks: DSI link clock information. - * @pixel_clk: Pixel clock rate in KHz. + * @clks: DSI link clock information. + * @pixel_clk: Pixel clock rate in KHz. + * @index: Index of the DSI controller. * * return: error code in case of failure or 0 for success. */ @@ -136,9 +137,9 @@ int dsi_clk_set_pixel_clk_rate(void *client, u64 pixel_clk, u32 index) /** * dsi_clk_set_byte_clk_rate() - set frequency for byte clock - * @client: DSI clock client pointer. - * @byte_clk: Pixel clock rate in Hz. - * @index: Index of the DSI controller. + * @client: DSI clock client pointer. + * @byte_clk: Byte clock rate in Hz. + * @index: Index of the DSI controller. * return: error code in case of failure or 0 for success. */ int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index) @@ -146,6 +147,7 @@ int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index) int rc = 0; struct dsi_clk_client_info *c = client; struct dsi_clk_mngr *mngr; + u64 byte_intf_rate; mngr = c->mngr; rc = clk_set_rate(mngr->link_clks[index].hs_clks.byte_clk, byte_clk); @@ -154,8 +156,16 @@ int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index) else mngr->link_clks[index].freq.byte_clk_rate = byte_clk; - return rc; + if (mngr->link_clks[index].hs_clks.byte_intf_clk) { + byte_intf_rate = mngr->link_clks[index].freq.byte_clk_rate / 2; + rc = clk_set_rate(mngr->link_clks[index].hs_clks.byte_intf_clk, + byte_intf_rate); + if (rc) + pr_err("failed to set clk rate for byte intf clk=%d\n", + rc); + } + return rc; } /** @@ -183,6 +193,41 @@ int dsi_clk_update_parent(struct dsi_clk_link_set *parent, return rc; } +/** + * dsi_clk_prepare_enable() - prepare and enable dsi src clocks + * @clk: list of src clocks. + * + * @return: Zero on success and err no on failure. + */ +int dsi_clk_prepare_enable(struct dsi_clk_link_set *clk) +{ + int rc; + + rc = clk_prepare_enable(clk->byte_clk); + if (rc) { + pr_err("failed to enable byte src clk %d\n", rc); + return rc; + } + + rc = clk_prepare_enable(clk->pixel_clk); + if (rc) { + pr_err("failed to enable pixel src clk %d\n", rc); + return rc; + } + + return 0; +} + +/** + * dsi_clk_disable_unprepare() - disable and unprepare dsi src clocks + * @clk: list of src clocks. + */ +void dsi_clk_disable_unprepare(struct dsi_clk_link_set *clk) +{ + clk_disable_unprepare(clk->pixel_clk); + clk_disable_unprepare(clk->byte_clk); +} + int dsi_core_clk_start(struct dsi_core_clks *c_clks) { int rc = 0; @@ -1210,9 +1255,7 @@ int dsi_clk_req_state(void *client, enum dsi_clk_type clk, return rc; } -DEFINE_MUTEX(dsi_mngr_clk_mutex); - -static int dsi_display_link_clk_force_update(void *client) +int dsi_display_link_clk_force_update(void *client) { int rc = 0; struct dsi_clk_client_info *c = client; @@ -1259,43 +1302,6 @@ static int dsi_display_link_clk_force_update(void *client) } -int dsi_display_link_clk_force_update_ctrl(void *handle) -{ - int rc = 0; - - if (!handle) { - pr_err("%s: Invalid arg\n", __func__); - return -EINVAL; - } - - mutex_lock(&dsi_mngr_clk_mutex); - - rc = dsi_display_link_clk_force_update(handle); - - mutex_unlock(&dsi_mngr_clk_mutex); - - return rc; -} - -int dsi_display_clk_ctrl(void *handle, - enum dsi_clk_type clk_type, enum dsi_clk_state clk_state) -{ - int rc = 0; - - if (!handle) { - pr_err("%s: Invalid arg\n", __func__); - return -EINVAL; - } - - mutex_lock(&dsi_mngr_clk_mutex); - rc = dsi_clk_req_state(handle, clk_type, clk_state); - if (rc) - pr_err("%s: failed set clk state, rc = %d\n", __func__, rc); - mutex_unlock(&dsi_mngr_clk_mutex); - - return rc; -} - void *dsi_register_clk_handle(void *clk_mngr, char *client) { void *handle = NULL; diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c old mode 100644 new mode 100755 index 948a662bc11e4b74302205be3243f7a177c72532..dde8151fb9b04a44c7455762109869175e183e3f --- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -32,6 +32,7 @@ #include "dsi_catalog.h" #include "sde_dbg.h" +#include "sde_trace.h" #define DSI_CTRL_DEFAULT_LABEL "MDSS DSI CTRL" @@ -1105,6 +1106,37 @@ int dsi_message_validate_tx_mode(struct dsi_ctrl *dsi_ctrl, return rc; } +#if 0 +static void print_cmd_desc(const struct mipi_dsi_msg *msg) +{ + + char buf[1024]; + int len = 0; + size_t i; + + /* Packet Info */ + len += snprintf(buf, sizeof(buf) - len, "%02x ", msg->type); + len += snprintf(buf + len, sizeof(buf) - len, "%02x ", + (msg->flags & MIPI_DSI_MSG_LASTCOMMAND) ? 1 : 0); /* Last bit */ + len += snprintf(buf + len, sizeof(buf) - len, "%02x ", msg->channel); + len += snprintf(buf + len, sizeof(buf) - len, "%02x ", + (unsigned int)msg->flags); + len += snprintf(buf + len, sizeof(buf) - len, "%02x ", 0); /* Delay */ + len += snprintf(buf + len, sizeof(buf) - len, "%02x ", + (unsigned int)msg->tx_len); + + /* Packet Payload */ + for (i = 0 ; i < msg->tx_len ; i++) { + len += snprintf(buf + len, sizeof(buf) - len, + "%02x ", msg->tx_buf[i]); + /* Break to prevent show too long command */ + if (i > 250) + break; + } + + printk(KERN_ERR"(%02d) %s\n", (unsigned int)msg->tx_len, buf); +} +#endif static int dsi_message_tx(struct dsi_ctrl *dsi_ctrl, const struct mipi_dsi_msg *msg, @@ -1121,6 +1153,7 @@ static int dsi_message_tx(struct dsi_ctrl *dsi_ctrl, u8 *cmdbuf; struct dsi_mode_info *timing; struct dsi_ctrl_hw_ops dsi_hw_ops = dsi_ctrl->hw.ops; + //print_cmd_desc(msg); /* Select the tx mode to transfer the command */ dsi_message_setup_tx_mode(dsi_ctrl, msg->tx_len, &flags); @@ -2493,7 +2526,7 @@ static int _dsi_ctrl_setup_isr(struct dsi_ctrl *dsi_ctrl) return -EINVAL; if (dsi_ctrl->irq_info.irq_num != -1) return 0; - + SDE_ATRACE_BEGIN("_dsi_ctrl_setup_isr"); init_completion(&dsi_ctrl->irq_info.cmd_dma_done); init_completion(&dsi_ctrl->irq_info.vid_frame_done); init_completion(&dsi_ctrl->irq_info.cmd_frame_done); @@ -2518,6 +2551,7 @@ static int _dsi_ctrl_setup_isr(struct dsi_ctrl *dsi_ctrl) dsi_ctrl->cell_index, irq_num); } } + SDE_ATRACE_END("_dsi_ctrl_setup_isr"); return rc; } @@ -2880,7 +2914,12 @@ int dsi_ctrl_update_host_config(struct dsi_ctrl *ctrl, goto error; } - if (!(flags & (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR))) { + if (!(flags & (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR | + DSI_MODE_FLAG_DYN_CLK))) { + /* + * for dynamic clk switch case link frequence would + * be updated dsi_display_dynamic_clk_switch(). + */ rc = dsi_ctrl_update_link_freqs(ctrl, config, clk_handle); if (rc) { pr_err("[%s] failed to update link frequencies, rc=%d\n", @@ -3595,6 +3634,27 @@ void dsi_ctrl_irq_update(struct dsi_ctrl *dsi_ctrl, bool enable) mutex_unlock(&dsi_ctrl->ctrl_lock); } +/** + * dsi_ctrl_wait4dynamic_refresh_done() - Poll for dynamci refresh + * done interrupt. + * @dsi_ctrl: DSI controller handle. + */ +int dsi_ctrl_wait4dynamic_refresh_done(struct dsi_ctrl *ctrl) +{ + int rc = 0; + + if (!ctrl) + return 0; + + mutex_lock(&ctrl->ctrl_lock); + + if (ctrl->hw.ops.wait4dynamic_refresh_done) + rc = ctrl->hw.ops.wait4dynamic_refresh_done(&ctrl->hw); + + mutex_unlock(&ctrl->ctrl_lock); + return rc; +} + /** * dsi_ctrl_drv_register() - register platform driver for dsi controller */ diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h index 75f43abfbc7f4706c734b5dec7f98ab97595aa29..f49772dace7ad3f552eabd45ef8a255b76945929 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -805,4 +805,11 @@ int dsi_ctrl_pixel_format_to_bpp(enum dsi_pixel_format dst_format); * @enable: variable to control continuous clock. */ void dsi_ctrl_set_continuous_clk(struct dsi_ctrl *dsi_ctrl, bool enable); + +/** + * dsi_ctrl_wait4dynamic_refresh_done() - Poll for dynamic refresh done + * interrupt. + * @dsi_ctrl: DSI controller handle. + */ +int dsi_ctrl_wait4dynamic_refresh_done(struct dsi_ctrl *ctrl); #endif /* _DSI_CTRL_H_ */ diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h index 458d865c2cf4451a98f4e6df0dea727691d09bb0..848dea5b2f0c4fc2aa7e63376293afe9e5ecfa23 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -829,6 +829,12 @@ struct dsi_ctrl_hw_ops { * @enable: Bool to control continuous clock request. */ void (*set_continuous_clk)(struct dsi_ctrl_hw *ctrl, bool enable); + + /** + * hw.ops.wait4dynamic_refresh_done() - Wait for dynamic refresh done + * @ctrl: Pointer to the controller host hardware. + */ + int (*wait4dynamic_refresh_done)(struct dsi_ctrl_hw *ctrl); }; /* diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c index 64d56d77a12e284ca396fb58de87c569258bfe4e..273c7e0f1650d22af641dba0c26a78c7c730fd2c 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -23,6 +23,7 @@ #include "dsi_panel.h" #include "dsi_catalog.h" #include "sde_dbg.h" +#include "sde_trace.h" #define MMSS_MISC_CLAMP_REG_OFF 0x0014 #define DSI_CTRL_DYNAMIC_FORCE_ON (0x23F|BIT(8)|BIT(9)|BIT(11)|BIT(21)) @@ -1516,6 +1517,13 @@ void dsi_ctrl_hw_cmn_mask_error_intr(struct dsi_ctrl_hw *ctrl, u32 idx, bool en) } } + if (idx & BIT(DSI_PLL_UNLOCK_ERR)) { + if (en) + reg |= BIT(28); + else + reg &= ~BIT(28); + } + DSI_W32(ctrl, 0x10c, reg); wmb(); /* ensure error is masked */ } @@ -1562,8 +1570,10 @@ int dsi_ctrl_hw_cmn_wait_for_cmd_mode_mdp_idle(struct dsi_ctrl_hw *ctrl) u32 const sleep_us = 2 * 1000; u32 const timeout_us = 200 * 1000; + SDE_ATRACE_BEGIN("readl_poll_timeout"); rc = readl_poll_timeout(ctrl->base + DSI_STATUS, val, !(val & cmd_mode_mdp_busy_mask), sleep_us, timeout_us); + SDE_ATRACE_END("readl_poll_timeout"); if (rc) pr_err("%s: timed out waiting for idle\n", __func__); @@ -1582,3 +1592,25 @@ void dsi_ctrl_hw_cmn_set_continuous_clk(struct dsi_ctrl_hw *ctrl, bool enable) DSI_W32(ctrl, DSI_LANE_CTRL, reg); wmb(); /* make sure request is set */ } + +int dsi_ctrl_hw_cmn_wait4dynamic_refresh_done(struct dsi_ctrl_hw *ctrl) +{ + int rc; + u32 const sleep_us = 1000; + u32 const timeout_us = 84000; /* approximately 5 vsyncs */ + u32 reg = 0, dyn_refresh_done = BIT(28); + + rc = readl_poll_timeout(ctrl->base + DSI_INT_CTRL, reg, + (reg & dyn_refresh_done), sleep_us, timeout_us); + if (rc) { + pr_err("wait4dynamic refresh timedout %d\n", rc); + return rc; + } + + /* ack dynamic refresh done status */ + reg = DSI_R32(ctrl, DSI_INT_CTRL); + reg |= dyn_refresh_done; + DSI_W32(ctrl, DSI_INT_CTRL, reg); + + return 0; +} diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_reg.h b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_reg.h index 6bf147bb00cb20e6e3b56d8791422736bd9cf988..72ac12dfd4b6beb714444d5890eec2ff2694cffe 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_reg.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_reg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -138,44 +138,7 @@ #define DSI_SCRATCH_REGISTER_1 (0x01F8) #define DSI_SCRATCH_REGISTER_2 (0x01FC) #define DSI_DYNAMIC_REFRESH_CTRL (0x0200) -#define DSI_DYNAMIC_REFRESH_PIPE_DELAY (0x0204) -#define DSI_DYNAMIC_REFRESH_PIPE_DELAY2 (0x0208) -#define DSI_DYNAMIC_REFRESH_PLL_DELAY (0x020C) #define DSI_DYNAMIC_REFRESH_STATUS (0x0210) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL0 (0x0214) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL1 (0x0218) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL2 (0x021C) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL3 (0x0220) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL4 (0x0224) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL5 (0x0228) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL6 (0x022C) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL7 (0x0230) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL8 (0x0234) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL9 (0x0238) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL10 (0x023C) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL11 (0x0240) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL12 (0x0244) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL13 (0x0248) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL14 (0x024C) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL15 (0x0250) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL16 (0x0254) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL17 (0x0258) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL18 (0x025C) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL19 (0x0260) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL20 (0x0264) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL21 (0x0268) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL22 (0x026C) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL23 (0x0270) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL24 (0x0274) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL25 (0x0278) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL26 (0x027C) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL27 (0x0280) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL28 (0x0284) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL29 (0x0288) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL30 (0x028C) -#define DSI_DYNAMIC_REFRESH_PLL_CTRL31 (0x0290) -#define DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR (0x0294) -#define DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR2 (0x0298) #define DSI_VIDEO_COMPRESSION_MODE_CTRL (0x02A0) #define DSI_VIDEO_COMPRESSION_MODE_CTRL2 (0x02A4) #define DSI_COMMAND_COMPRESSION_MODE_CTRL (0x02A8) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h old mode 100644 new mode 100755 index c57f8b17eb3ee54cc42af5019eec2ae26b7d2b58..b83cc74165bc2fb8248da54077f81ea93a6a674e --- a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -82,6 +82,7 @@ enum dsi_op_mode { * @DSI_MODE_FLAG_DMS: Seamless transition is dynamic mode switch * @DSI_MODE_FLAG_VRR: Seamless transition is DynamicFPS. * New timing values are sent from DAL. + * @DSI_MODE_FLAG_DYN_CLK: Seamless transition is dynamic clock change */ enum dsi_mode_flags { DSI_MODE_FLAG_SEAMLESS = BIT(0), @@ -89,6 +90,7 @@ enum dsi_mode_flags { DSI_MODE_FLAG_VBLANK_PRE_MODESET = BIT(2), DSI_MODE_FLAG_DMS = BIT(3), DSI_MODE_FLAG_VRR = BIT(4), + DSI_MODE_FLAG_DYN_CLK = BIT(5), }; /** @@ -273,7 +275,71 @@ enum dsi_cmd_set_type { DSI_CMD_SET_POST_TIMING_SWITCH, DSI_CMD_SET_QSYNC_ON, DSI_CMD_SET_QSYNC_OFF, + DSI_CMD_SET_HBM_BRIGHTNESS_ON, + DSI_CMD_SET_HBM_BRIGHTNESS_OFF, + DSI_CMD_SET_HBM_ON_1, + DSI_CMD_SET_HBM_ON_2, + DSI_CMD_SET_HBM_ON_3, + DSI_CMD_SET_HBM_ON_4, + DSI_CMD_SET_HBM_ON_5, + DSI_CMD_SET_HBM_OFF, + DSI_CMD_SET_PANEL_SERIAL_NUMBER, + DSI_CMD_SET_AOD_ON_1, + DSI_CMD_SET_AOD_ON_2, + DSI_CMD_SET_AOD_OFF, + DSI_CMD_AOD_OFF_HBM_ON_SETTING, + DSI_CMD_SET_AOD_OFF_NEW, + DSI_CMD_HBM_OFF_AOD_ON_SETTING, + DSI_CMD_SET_AOD_OFF_SAMSUNG, +// DSI_CMD_SET_SRGB_ON, +// DSI_CMD_SET_SRGB_OFF, + DSI_CMD_SET_DCI_P3_ON, + DSI_CMD_SET_DCI_P3_OFF, + DSI_CMD_SET_NIGHT_ON, + DSI_CMD_SET_NIGHT_OFF, + DSI_CMD_SET_PANEL_ID, + DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON, + DSI_CMD_SET_PANEL_ID1, + DSI_CMD_SET_PANEL_ID2, + DSI_CMD_SET_PANEL_ID3, + DSI_CMD_SET_PANEL_ID4, + DSI_CMD_SET_PANEL_ID5, + DSI_CMD_SET_PANEL_ID6, + DSI_CMD_SET_PANEL_ID7, + DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF, + DSI_CMD_SET_ACL_MODE, + DSI_CMD_SET_LCDINFO_PRE, + DSI_CMD_SET_LCDINFO_POST, + DSI_CMD_SET_STAGE_INFO, + DSI_CMD_SET_PRODUCTION_INFO, + DSI_CMD_SET_ESD_LOGREAD_PREREAD, + DSI_CMD_SET_GAMMA_FLASH_PRE_READ_1, + DSI_CMD_SET_GAMMA_FLASH_PRE_READ_2, + DSI_CMD_SET_GAMMA_FLASH_READ_FB, + DSI_CMD_SET_LEVEL2_KEY_ENABLE, + DSI_CMD_SET_GAMMA_OTP_READ_C8_SMRPS, + DSI_CMD_SET_GAMMA_OTP_READ_C8, + DSI_CMD_SET_GAMMA_OTP_READ_C9_SMRPS, + DSI_CMD_SET_GAMMA_OTP_READ_C9, + DSI_CMD_SET_GAMMA_OTP_READ_B3_SMRPS, + DSI_CMD_SET_GAMMA_OTP_READ_B3, + DSI_CMD_SET_LEVEL2_KEY_DISABLE, + DSI_CMD_SET_NATIVE_DISPLAY_P3_ON, + DSI_CMD_SET_NATIVE_DISPLAY_P3_OFF, + DSI_CMD_SET_NATIVE_DISPLAY_WIDE_COLOR_ON, + DSI_CMD_SET_NATIVE_DISPLAY_WIDE_COLOR_OFF, + DSI_CMD_SET_NATIVE_DISPLAY_SRGB_COLOR_ON, + DSI_CMD_SET_NATIVE_DISPLAY_SRGB_COLOR_OFF, + DSI_CMD_SET_113MHZ_OSC_ON, + DSI_CMD_POST_ON_BACKLIGHT, + DSI_CMD_LOADING_EFFECT_ON, + DSI_CMD_LOADING_EFFECT_OFF, + DSI_CMD_LOADING_CUSTOMER_RGB_ON, + DSI_CMD_LOADING_CUSTOMER_RGB_OFF, + DSI_CMD_LOADING_CUSTOMER_P3_ON, + DSI_CMD_LOADING_CUSTOMER_P3_OFF, DSI_CMD_SET_MAX + }; /** @@ -635,12 +701,50 @@ struct dsi_event_cb_info { * @DSI_FIFO_OVERFLOW: DSI FIFO Overflow error * @DSI_FIFO_UNDERFLOW: DSI FIFO Underflow error * @DSI_LP_Rx_TIMEOUT: DSI LP/RX Timeout error + * @DSI_PLL_UNLOCK_ERR: DSI PLL unlock error */ enum dsi_error_status { DSI_FIFO_OVERFLOW = 1, DSI_FIFO_UNDERFLOW, DSI_LP_Rx_TIMEOUT, + DSI_PLL_UNLOCK_ERR, DSI_ERR_INTR_ALL, }; +/* structure containing the delays required for dynamic clk */ +struct dsi_dyn_clk_delay { + u32 pipe_delay; + u32 pipe_delay2; + u32 pll_delay; +}; + +/* dynamic refresh control bits */ +enum dsi_dyn_clk_control_bits { + DYN_REFRESH_INTF_SEL = 1, + DYN_REFRESH_SYNC_MODE, + DYN_REFRESH_SW_TRIGGER, + DYN_REFRESH_SWI_CTRL, +}; + +/* convert dsi pixel format into bits per pixel */ +static inline int dsi_pixel_format_to_bpp(enum dsi_pixel_format fmt) +{ + switch (fmt) { + case DSI_PIXEL_FORMAT_RGB888: + case DSI_PIXEL_FORMAT_MAX: + return 24; + case DSI_PIXEL_FORMAT_RGB666: + case DSI_PIXEL_FORMAT_RGB666_LOOSE: + return 18; + case DSI_PIXEL_FORMAT_RGB565: + return 16; + case DSI_PIXEL_FORMAT_RGB111: + return 3; + case DSI_PIXEL_FORMAT_RGB332: + return 8; + case DSI_PIXEL_FORMAT_RGB444: + return 12; + } + return 24; +} #endif /* _DSI_DEFS_H_ */ diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c old mode 100644 new mode 100755 index 862254c369d79299a8dfe449b73e725d42391c87..596b8f6a063e19f422ccfce91fa21f29956c1b4e --- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -18,6 +18,8 @@ #include #include #include +#include +#include #include "msm_drv.h" #include "sde_connector.h" @@ -31,6 +33,14 @@ #include "dsi_pwr.h" #include "sde_dbg.h" #include "dsi_parser.h" +#include +#include +#include +#include +#include +#include +#include "../sde/sde_trace.h" +#include "dsi_parser.h" #define to_dsi_display(x) container_of(x, struct dsi_display, host) #define INT_BASE_10 10 @@ -44,8 +54,14 @@ #define DSI_CLOCK_BITRATE_RADIX 10 #define MAX_TE_SOURCE_ID 2 +DEFINE_MUTEX(dsi_display_clk_mutex); + static char dsi_display_primary[MAX_CMDLINE_PARAM_LEN]; static char dsi_display_secondary[MAX_CMDLINE_PARAM_LEN]; +static char SERIAL_NUMBER_flag = 0; + + + static struct dsi_display_boot_param boot_displays[MAX_DSI_ACTIVE_DISPLAY] = { {.boot_param = dsi_display_primary}, {.boot_param = dsi_display_secondary}, @@ -55,6 +71,13 @@ static const struct of_device_id dsi_display_dt_match[] = { {.compatible = "qcom,dsi-display"}, {} }; +static struct dsi_display *primary_display; +static struct input_dev* brightness_input_dev = NULL; +static struct proc_dir_entry *prEntry_tp = NULL; +static int screen_state_enable = 0; +static int screen_state; +static int screen_last_state = 3; +#define to_dsi_bridge(x) container_of((x), struct dsi_bridge, base) static void dsi_display_mask_ctrl_error_interrupts(struct dsi_display *display, u32 mask, bool enable) @@ -176,6 +199,7 @@ void dsi_rect_intersect(const struct dsi_rect *r1, } } +extern int aod_layer_hide; int dsi_display_set_backlight(struct drm_connector *connector, void *display, u32 bl_lvl) { @@ -184,18 +208,117 @@ int dsi_display_set_backlight(struct drm_connector *connector, u32 bl_scale, bl_scale_ad; u64 bl_temp; int rc = 0; - + static char gamma_read_flag = 0; if (dsi_display == NULL || dsi_display->panel == NULL) return -EINVAL; panel = dsi_display->panel; - mutex_lock(&panel->panel_lock); if (!dsi_panel_initialized(panel)) { + panel->hbm_backlight = bl_lvl; + panel->bl_config.bl_level = bl_lvl; + pr_err("HBM_backight =%d\n",panel->hbm_backlight); rc = -EINVAL; goto error; } + +if (strcmp(dsi_display->panel->name, "samsung s6e3fc2x01 cmd mode dsi panel") == 0){ + + if (bl_lvl != 0 && panel->bl_config.bl_level == 0) { + if (panel->naive_display_p3_mode) { + mdelay(20); + pr_err("Send DSI_CMD_SET_NATIVE_DISPLAY_P3_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_NATIVE_DISPLAY_P3_ON); + } + if (panel->naive_display_wide_color_mode) { + mdelay(20); + pr_err("Send DSI_CMD_SET_NATIVE_DISPLAY_WIDE_COLOR_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_NATIVE_DISPLAY_WIDE_COLOR_ON); + } + if (panel->naive_display_srgb_color_mode) { + mdelay(20); + pr_err("Send DSI_CMD_SET_NATIVE_DISPLAY_SRGB_COLOR_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_NATIVE_DISPLAY_SRGB_COLOR_ON); + } + if (panel->naive_display_loading_effect_mode) { + pr_err("Send DSI_CMD_LOADING_EFFECT_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_EFFECT_ON); + } + else { + pr_err("Send DSI_CMD_LOADING_EFFECT_OFF cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_EFFECT_OFF); + } + + if (panel->naive_display_customer_srgb_mode) { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_RGB_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_RGB_ON); + } + else { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_RGB_OFF cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_RGB_OFF); + } + + if (panel->naive_display_customer_p3_mode) { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_P3_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_P3_ON); + } + else { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_P3_OFF cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_P3_OFF); + } + + } + +} + + if (strcmp(dsi_display->panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0) { + if (bl_lvl != 0 && panel->bl_config.bl_level == 0) { + if (panel->naive_display_p3_mode) { + mdelay(20); + pr_err("Send DSI_CMD_SET_NATIVE_DISPLAY_P3_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_NATIVE_DISPLAY_P3_ON); + } + if (panel->naive_display_wide_color_mode) { + mdelay(20); + pr_err("Send DSI_CMD_SET_NATIVE_DISPLAY_WIDE_COLOR_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_NATIVE_DISPLAY_WIDE_COLOR_ON); + } + if (panel->naive_display_srgb_color_mode) { + mdelay(20); + pr_err("Send DSI_CMD_SET_NATIVE_DISPLAY_SRGB_COLOR_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_NATIVE_DISPLAY_SRGB_COLOR_ON); + } + if (panel->naive_display_loading_effect_mode) { + pr_err("Send DSI_CMD_LOADING_EFFECT_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_EFFECT_ON); + } + else { + pr_err("Send DSI_CMD_LOADING_EFFECT_OFF cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_EFFECT_OFF); + } + + if (panel->naive_display_customer_srgb_mode) { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_RGB_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_RGB_ON); + } + else { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_RGB_OFF cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_RGB_OFF); + } + + if (panel->naive_display_customer_p3_mode) { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_P3_ON cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_P3_ON); + } + else { + pr_err("Send DSI_CMD_LOADING_CUSTOMER_P3_OFF cmds\n"); + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_LOADING_CUSTOMER_P3_OFF); + } + + } + } + panel->bl_config.bl_level = bl_lvl; /* scale backlight */ @@ -219,7 +342,6 @@ int dsi_display_set_backlight(struct drm_connector *connector, rc = dsi_panel_set_backlight(panel, (u32)bl_temp); if (rc) pr_err("unable to set backlight\n"); - rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, DSI_CORE_CLK, DSI_CLK_OFF); if (rc) { @@ -230,7 +352,27 @@ int dsi_display_set_backlight(struct drm_connector *connector, error: mutex_unlock(&panel->panel_lock); - return rc; + + if((strcmp(dsi_display->panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0 + || strcmp(panel->name, "samsung s6e3fc2x01 cmd mode dsi panel") == 0) && (0 == SERIAL_NUMBER_flag)) { + dsi_display_get_serial_number_AT(connector); + } + + if ((gamma_read_flag < 2) && (strcmp(dsi_display->panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0)) { + if (gamma_read_flag < 1) { + gamma_read_flag++; + } + else { +// dsi_display_get_serial_number_AT(connector); + if (((panel->panel_production_info & 0x0F) == 0x0C) || ((panel->panel_production_info & 0x0F) == 0x0E) + || ((panel->panel_production_info & 0x0F) == 0x0D)) { + dsi_display_gamma_read(dsi_display); + } + dsi_panel_parse_gamma_cmd_sets(); + gamma_read_flag ++; + } + } + return rc; } static int dsi_display_cmd_engine_enable(struct dsi_display *display) @@ -698,15 +840,86 @@ static int dsi_display_validate_status(struct dsi_display_ctrl *ctrl, return rc; } +static int dsi_panel_tx_cmd_set_op(struct dsi_panel *panel, + enum dsi_cmd_set_type type) +{ + int rc = 0, i = 0; + ssize_t len; + struct dsi_cmd_desc *cmds; + u32 count; + enum dsi_cmd_set_state state; + struct dsi_display_mode *mode; + const struct mipi_dsi_host_ops *ops = panel->host->ops; + if (!panel || !panel->cur_mode) + return -EINVAL; + + + mode = panel->cur_mode; + + cmds = mode->priv_info->cmd_sets[type].cmds; + count = mode->priv_info->cmd_sets[type].count; + state = mode->priv_info->cmd_sets[type].state; + + if (count == 0) { + pr_debug("[%s] No commands to be sent for state(%d)\n", + panel->name, type); + goto error; + } + for (i = 0; i < count; i++) { + if (state == DSI_CMD_SET_STATE_LP) + cmds->msg.flags |= MIPI_DSI_MSG_USE_LPM; + + if (cmds->last_command) + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + + len = ops->transfer(panel->host, &cmds->msg); + if (len < 0) { + rc = len; + pr_err("failed to set cmds(%d), rc=%d\n", type, rc); + goto error; + } + if (cmds->post_wait_ms) + usleep_range(cmds->post_wait_ms*1000, + ((cmds->post_wait_ms*1000)+10)); + cmds++; + } +error: + return rc; +} + static int dsi_display_status_reg_read(struct dsi_display *display) { int rc = 0, i; struct dsi_display_ctrl *m_ctrl, *ctrl; - - pr_debug(" ++\n"); - + struct dsi_display_mode *mode; + u32 flags = 0; + u32 count =0; + struct dsi_panel *panel = NULL; + struct dsi_cmd_desc *cmds1; + struct dsi_cmd_desc *cmds2; + struct dsi_cmd_desc *cmds3; + struct dsi_cmd_desc *cmds4; + struct dsi_cmd_desc *cmds5; + struct dsi_cmd_desc *cmds6; + struct dsi_cmd_desc *cmds7; + u8 temp_buffer_1[1] = {0}; + u8 temp_buffer_2[1] = {0}; + u8 temp_buffer_3[1] = {0}; + u8 temp_buffer_4[1] = {0}; + u8 temp_buffer_5[2] = {0,}; + u8 temp_buffer_6[16] = {0,}; + u8 temp_buffer_7[34] = {0,}; + u8 buf[48]; + //u8 ESD_TEST1=0; + //u8 ESD_TEST2=0; + //u8 ESD_TEST3=0; + //u8 ESD_TEST4=0; + //u8 ESD_TEST5=0; + //u8 ESD_TEST6=0; + //u8 ESD_TEST7=0; + memset(buf, 0, sizeof(buf)); + //printk(KERN_ERR"dsi_display_status_reg_read start\n"); m_ctrl = &display->ctrl[display->cmd_master_idx]; - if (display->tx_cmd_buf == NULL) { rc = dsi_host_alloc_cmd_tx_buffer(display); if (rc) { @@ -714,14 +927,219 @@ static int dsi_display_status_reg_read(struct dsi_display *display) goto done; } } - rc = dsi_display_cmd_engine_enable(display); if (rc) { pr_err("cmd engine enable failed\n"); return -EPERM; } + mode = display->panel->cur_mode; + panel = display->panel; + if (strcmp(panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0){ + count = mode->priv_info->cmd_sets[DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON].count; + if (!count) { + pr_err("This panel does not read register\n"); + } else { + + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + } + cmds1 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID1].cmds; + if (cmds1->last_command) { + cmds1->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds1->msg.rx_buf = buf; + cmds1->msg.rx_len = 1; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds1->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF); + + memcpy(temp_buffer_1, cmds1->msg.rx_buf, 1); + memset(buf, 0, sizeof(buf)); + + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + cmds2 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID2].cmds; + if (cmds2->last_command) { + cmds2->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds2->msg.rx_buf = buf; + cmds2->msg.rx_len = 1; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds2->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF); + + memcpy(temp_buffer_2, cmds2->msg.rx_buf, 1); + memset(buf, 0, sizeof(buf)); + + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + cmds3 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID3].cmds; + if (cmds3->last_command) { + cmds3->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds3->msg.rx_buf = buf; + cmds3->msg.rx_len = 1; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds3->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF); + + memcpy(temp_buffer_3, cmds3->msg.rx_buf, 1); + + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + cmds4 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID4].cmds; + if (cmds4->last_command) { + cmds4->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds4->msg.rx_buf = buf; + cmds4->msg.rx_len = 1; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds4->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF); + + memcpy(temp_buffer_4, cmds4->msg.rx_buf, 1); + memset(buf, 0, sizeof(buf)); + + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + cmds5 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID5].cmds; + if (cmds5->last_command) { + cmds5->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds5->msg.rx_buf = buf; + cmds5->msg.rx_len = 2; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds5->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF); + + memcpy(temp_buffer_5, cmds5->msg.rx_buf, 2); + memset(buf, 0, sizeof(buf)); + + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + cmds6 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID6].cmds; + if (cmds6->last_command) { + cmds6->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds6->msg.rx_buf = buf; + cmds6->msg.rx_len = 16; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds6->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF); + + memcpy(temp_buffer_6, cmds6->msg.rx_buf, 16); + memset(buf, 0, sizeof(buf)); + + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_SET_ESD_LOGREAD_PREREAD); + + cmds7 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID7].cmds; + if (cmds7->last_command) { + cmds7->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds7->msg.rx_buf = buf; + cmds7->msg.rx_len = 34; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds7->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF); + + memcpy(temp_buffer_7, cmds7->msg.rx_buf, 34); +/**********************************************************************************/ + + //printk(KERN_ERR"Read LCD register 0A = %x\n",temp_buffer_1[0]); + //printk(KERN_ERR"Read LCD register 0E = %x\n",temp_buffer_2[0]); + //printk(KERN_ERR"Read LCD register 0F = %x\n",temp_buffer_3[0]); + //printk(KERN_ERR"Read LCD register C4 = %x\n",temp_buffer_4[0]); + //printk(KERN_ERR"Read LCD register E7 = %x,%x\n",temp_buffer_5[0],temp_buffer_5[1]); + //printk(KERN_ERR"Read MIPI register EA(1-16) = %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x\n",temp_buffer_6[0],temp_buffer_6[1],temp_buffer_6[2],temp_buffer_6[3],temp_buffer_6[4],temp_buffer_6[5],temp_buffer_6[6],temp_buffer_6[7],temp_buffer_6[8],temp_buffer_6[9],temp_buffer_6[10],temp_buffer_6[11],temp_buffer_6[12],temp_buffer_6[13],temp_buffer_6[14],temp_buffer_6[15]); + //printk(KERN_ERR"Read MIPI register FB(1-16) = %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x\n", temp_buffer_7[0], temp_buffer_7[1], temp_buffer_7[2], temp_buffer_7[3], temp_buffer_7[4], temp_buffer_7[5], temp_buffer_7[6], temp_buffer_7[7], temp_buffer_7[8], temp_buffer_7[9], temp_buffer_7[10], temp_buffer_7[11], temp_buffer_7[12], temp_buffer_7[13], temp_buffer_7[14], temp_buffer_7[15]); + //printk(KERN_ERR"Read MIPI register FB(17-33) = %x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x,%x\n", temp_buffer_7[16], temp_buffer_7[17], temp_buffer_7[18], temp_buffer_7[19], temp_buffer_7[20], temp_buffer_7[21], temp_buffer_7[22], temp_buffer_7[23], temp_buffer_7[24], temp_buffer_7[25], temp_buffer_7[26], temp_buffer_7[27], temp_buffer_7[28], temp_buffer_7[29], temp_buffer_7[30], temp_buffer_7[31], temp_buffer_7[32]); + if((temp_buffer_6[0] !=0x80) && (temp_buffer_2[0] != 0x80)) { + rc = -1; + } + else { + rc = 1; + } +}else if(strcmp(panel->name, "samsung s6e3fc2x01 cmd mode dsi panel") == 0){ + + count = mode->priv_info->cmd_sets[DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON].count; + if (!count) { + pr_err("This panel does not read register\n"); + } else { + + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + } + cmds1 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID1].cmds; + if (cmds1->last_command) { + cmds1->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds1->msg.rx_buf = buf; + cmds1->msg.rx_len = 1; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds1->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + memcpy(temp_buffer_1, cmds1->msg.rx_buf, 1); + count = mode->priv_info->cmd_sets[DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON].count; + if (!count) { + pr_err("This panel does not read register\n"); + } else { + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_ON); + } + cmds2 = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID6].cmds; + if (cmds2->last_command) { + cmds2->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds2->msg.rx_buf = buf; + cmds2->msg.rx_len = 2; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds2->msg, flags); + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + memcpy(temp_buffer_6, cmds2->msg.rx_buf, 2); + count = mode->priv_info->cmd_sets[DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF].count; + if (!count) { + pr_err("This panel does not read register\n"); + } else { + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_READ_SAMSUNG_PANEL_REGISTER_OFF); + } +/* + ESD_TEST1=temp_buffer_6[0]; + ESD_TEST2=temp_buffer_6[1]; + ESD_TEST3=temp_buffer_1[0]; +*/ + // printk(KERN_ERR"Read LCD register 0A = %x\n",temp_buffer_1[0]); + // printk(KERN_ERR"Read LCD register E5 = %x,%x\n",temp_buffer_6[0],temp_buffer_6[1]); + if(((temp_buffer_6[0] == 132) && (temp_buffer_6[1] == 0))||(temp_buffer_1[0] != 159)) + rc=-1; + else + rc=1; + + + + +}else{ rc = dsi_display_validate_status(m_ctrl, display->panel); + +} if (rc <= 0) { pr_err("[%s] read status failed on master,rc=%d\n", display->name, rc); @@ -746,9 +1164,10 @@ static int dsi_display_status_reg_read(struct dsi_display *display) exit: dsi_display_cmd_engine_disable(display); done: + + //printk(KERN_ERR"GZM dsi_display_status_reg_read---\n"); return rc; } - static int dsi_display_status_bta_request(struct dsi_display *display) { int rc = 0; @@ -1043,17 +1462,38 @@ static bool dsi_display_get_cont_splash_status(struct dsi_display *display) } return true; } +extern int dsi_panel_set_aod_mode(struct dsi_panel *panel, int level); int dsi_display_set_power(struct drm_connector *connector, int power_mode, void *disp) { struct dsi_display *display = disp; int rc = 0; + struct msm_drm_notifier notifier_data; + int blank; if (!display || !display->panel) { pr_err("invalid display/panel\n"); return -EINVAL; } + printk(KERN_ERR"power_mode= %d\n",power_mode); + + if (power_mode == 1) + screen_state = 2;//aod + else if (power_mode == 0) + screen_state = 1;//on + else + screen_state = 0;//off + + printk(KERN_INFO"screen_state= %d, screen_last_state : %d \n", screen_state, screen_last_state); + + if (screen_state != screen_last_state) { + screen_last_state = screen_state; + if (screen_state_enable) { + input_event(brightness_input_dev, EV_MSC, MSC_RAW, screen_state); + input_sync(brightness_input_dev); + } + } switch (power_mode) { case SDE_MODE_DPMS_LP1: @@ -1064,8 +1504,34 @@ int dsi_display_set_power(struct drm_connector *connector, break; default: rc = dsi_panel_set_nolp(display->panel); + if ((power_mode == SDE_MODE_DPMS_ON) && display->panel->aod_status){ + dsi_panel_set_aod_mode(display->panel, 0); + } else if ((power_mode == SDE_MODE_DPMS_OFF) + && display->panel->aod_status){ + display->panel->aod_status = 0; + display->panel->aod_curr_mode = 0; + } break; } + if (power_mode == SDE_MODE_DPMS_ON) { + blank = MSM_DRM_BLANK_UNBLANK_CUST; + notifier_data.data = ␣ + notifier_data.id = connector_state_crtc_index; + msm_drm_notifier_call_chain(MSM_DRM_EARLY_EVENT_BLANK, + ¬ifier_data); + } else if (power_mode == SDE_MODE_DPMS_LP1) { + blank = MSM_DRM_BLANK_NORMAL; + notifier_data.data = ␣ + notifier_data.id = connector_state_crtc_index; + msm_drm_notifier_call_chain(MSM_DRM_EARLY_EVENT_BLANK, + ¬ifier_data); + } else if (power_mode == SDE_MODE_DPMS_OFF) { + blank = MSM_DRM_BLANK_POWERDOWN_CUST; + notifier_data.data = ␣ + notifier_data.id = connector_state_crtc_index; + msm_drm_notifier_call_chain(MSM_DRM_EARLY_EVENT_BLANK, + ¬ifier_data); + } return rc; } @@ -1628,7 +2094,7 @@ static void adjust_timing_by_ctrl_count(const struct dsi_display *display, mode->timing.h_back_porch /= sublinks_count; mode->timing.h_skew /= sublinks_count; mode->pixel_clk_khz /= sublinks_count; - } else if (display->ctrl_count > 1) { + } else { mode->timing.h_active /= display->ctrl_count; mode->timing.h_front_porch /= display->ctrl_count; mode->timing.h_sync_width /= display->ctrl_count; @@ -2255,7 +2721,7 @@ static int dsi_display_set_clk_src(struct dsi_display *display) m_ctrl = &display->ctrl[display->clk_master_idx]; rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl, - &display->clock_info.src_clks); + &display->clock_info.mux_clks); if (rc) { pr_err("[%s] failed to set source clocks for master, rc=%d\n", display->name, rc); @@ -2269,7 +2735,7 @@ static int dsi_display_set_clk_src(struct dsi_display *display) continue; rc = dsi_ctrl_set_clock_source(ctrl->ctrl, - &display->clock_info.src_clks); + &display->clock_info.mux_clks); if (rc) { pr_err("[%s] failed to set source clocks, rc=%d\n", display->name, rc); @@ -2938,6 +3404,7 @@ static int dsi_display_clocks_init(struct dsi_display *display) struct dsi_clk_link_set *src = &display->clock_info.src_clks; struct dsi_clk_link_set *mux = &display->clock_info.mux_clks; struct dsi_clk_link_set *shadow = &display->clock_info.shadow_clks; + struct dsi_dyn_clk_caps *dyn_clk_caps = &(display->panel->dyn_clk_caps); num_clk = dsi_display_get_clocks_count(display); @@ -2953,7 +3420,34 @@ static int dsi_display_clocks_init(struct dsi_display *display) rc = PTR_ERR(dsi_clk); pr_err("failed to get %s, rc=%d\n", clk_name, rc); - goto error; + + if (dsi_display_check_prefix(mux_byte, clk_name)) { + mux->byte_clk = NULL; + goto error; + } + if (dsi_display_check_prefix(mux_pixel, clk_name)) { + mux->pixel_clk = NULL; + goto error; + } + + if (dyn_clk_caps->dyn_clk_support && + (display->panel->panel_mode == + DSI_OP_VIDEO_MODE)) { + if (dsi_display_check_prefix(src_byte, + clk_name)) + src->byte_clk = NULL; + if (dsi_display_check_prefix(src_pixel, + clk_name)) + src->pixel_clk = NULL; + if (dsi_display_check_prefix(shadow_byte, + clk_name)) + shadow->byte_clk = NULL; + if (dsi_display_check_prefix(shadow_pixel, + clk_name)) + shadow->pixel_clk = NULL; + + dyn_clk_caps->dyn_clk_support = false; + } } if (dsi_display_check_prefix(src_byte, clk_name)) { @@ -3746,119 +4240,452 @@ static bool dsi_display_is_seamless_dfps_possible( return true; } -static int dsi_display_dfps_update(struct dsi_display *display, - struct dsi_display_mode *dsi_mode) +static int dsi_display_update_dsi_bitrate(struct dsi_display *display, + u32 bit_clk_rate) { - struct dsi_mode_info *timing; - struct dsi_display_ctrl *m_ctrl, *ctrl; - struct dsi_display_mode *panel_mode; - struct dsi_dfps_capabilities dfps_caps; int rc = 0; - int i = 0; + int i; - if (!display || !dsi_mode || !display->panel) { - pr_err("Invalid params\n"); - return -EINVAL; + pr_debug("%s:bit rate:%d\n", __func__, bit_clk_rate); + if (!display->panel) { + pr_err("Invalid params\n"); + return -EINVAL; } - timing = &dsi_mode->timing; - dsi_panel_get_dfps_caps(display->panel, &dfps_caps); - if (!dfps_caps.dfps_support) { - pr_err("dfps not supported\n"); - return -ENOTSUPP; + if (bit_clk_rate == 0) { + pr_err("Invalid bit clock rate\n"); + return -EINVAL; } - if (dfps_caps.type == DSI_DFPS_IMMEDIATE_CLK) { - pr_err("dfps clock method not supported\n"); - return -ENOTSUPP; + display->config.bit_clk_rate_hz = bit_clk_rate; + + for (i = 0; i < display->ctrl_count; i++) { + struct dsi_display_ctrl *dsi_disp_ctrl = &display->ctrl[i]; + struct dsi_ctrl *ctrl = dsi_disp_ctrl->ctrl; + u32 num_of_lanes = 0, bpp; + u64 bit_rate, pclk_rate, bit_rate_per_lane, byte_clk_rate; + struct dsi_host_common_cfg *host_cfg; + + mutex_lock(&ctrl->ctrl_lock); + + host_cfg = &display->panel->host_config; + if (host_cfg->data_lanes & DSI_DATA_LANE_0) + num_of_lanes++; + if (host_cfg->data_lanes & DSI_DATA_LANE_1) + num_of_lanes++; + if (host_cfg->data_lanes & DSI_DATA_LANE_2) + num_of_lanes++; + if (host_cfg->data_lanes & DSI_DATA_LANE_3) + num_of_lanes++; + + if (num_of_lanes == 0) { + pr_err("Invalid lane count\n"); + rc = -EINVAL; + goto error; } - /* For split DSI, update the clock master first */ + bpp = dsi_pixel_format_to_bpp(host_cfg->dst_format); - pr_debug("configuring seamless dynamic fps\n\n"); - SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY); + bit_rate = display->config.bit_clk_rate_hz * num_of_lanes; + bit_rate_per_lane = bit_rate; + do_div(bit_rate_per_lane, num_of_lanes); + pclk_rate = bit_rate; + do_div(pclk_rate, bpp); + byte_clk_rate = bit_rate_per_lane; + do_div(byte_clk_rate, 8); + pr_debug("bit_clk_rate = %llu, bit_clk_rate_per_lane = %llu\n", + bit_rate, bit_rate_per_lane); + pr_debug("byte_clk_rate = %llu, pclk_rate = %llu\n", + byte_clk_rate, pclk_rate); - m_ctrl = &display->ctrl[display->clk_master_idx]; - rc = dsi_ctrl_async_timing_update(m_ctrl->ctrl, timing); + ctrl->clk_freq.byte_clk_rate = byte_clk_rate; + ctrl->clk_freq.pix_clk_rate = pclk_rate; + rc = dsi_clk_set_link_frequencies(display->dsi_clk_handle, + ctrl->clk_freq, ctrl->cell_index); if (rc) { - pr_err("[%s] failed to dfps update host_%d, rc=%d\n", - display->name, i, rc); + pr_err("Failed to update link frequencies\n"); goto error; } - /* Update the rest of the controllers */ - display_for_each_ctrl(i, display) { - ctrl = &display->ctrl[i]; - if (!ctrl->ctrl || (ctrl == m_ctrl)) - continue; + ctrl->host_config.bit_clk_rate_hz = bit_clk_rate; +error: + mutex_unlock(&ctrl->ctrl_lock); - rc = dsi_ctrl_async_timing_update(ctrl->ctrl, timing); - if (rc) { - pr_err("[%s] failed to dfps update host_%d, rc=%d\n", - display->name, i, rc); - goto error; - } + /* TODO: recover ctrl->clk_freq in case of failure */ + if (rc) + return rc; } - panel_mode = display->panel->cur_mode; - memcpy(panel_mode, dsi_mode, sizeof(*panel_mode)); - /* - * dsi_mode_flags flags are used to communicate with other drm driver - * components, and are transient. They aren't inherently part of the - * display panel's mode and shouldn't be saved into the cached currently - * active mode. - */ - panel_mode->dsi_mode_flags = 0; - -error: - SDE_EVT32(SDE_EVTLOG_FUNC_EXIT); - return rc; + return 0; } -static int dsi_display_dfps_calc_front_porch( - u32 old_fps, - u32 new_fps, - u32 a_total, - u32 b_total, - u32 b_fp, - u32 *b_fp_out) +static int dsi_display_dynamic_clk_configure_cmd(struct dsi_display *display, + int clk_rate) { - s32 b_fp_new; - int add_porches, diff; + int rc = 0; - if (!b_fp_out) { - pr_err("Invalid params"); + if (clk_rate <= 0) { + pr_err("%s: bitrate should be greater than 0\n", __func__); return -EINVAL; } - if (!a_total || !new_fps) { - pr_err("Invalid pixel total or new fps in mode request\n"); - return -EINVAL; + if (clk_rate == display->cached_clk_rate) { + pr_info("%s: ignore duplicated DSI clk setting\n", __func__); + return rc; } - /* - * Keep clock, other porches constant, use new fps, calc front porch - * new_vtotal = old_vtotal * (old_fps / new_fps ) - * new_vfp - old_vfp = new_vtotal - old_vtotal - * new_vfp = old_vfp + old_vtotal * ((old_fps - new_fps)/ new_fps) - */ - diff = abs(old_fps - new_fps); - add_porches = mult_frac(b_total, diff, new_fps); - - if (old_fps > new_fps) - b_fp_new = b_fp + add_porches; - else - b_fp_new = b_fp - add_porches; - - pr_debug("fps %u a %u b %u b_fp %u new_fp %d\n", - new_fps, a_total, b_total, b_fp, b_fp_new); + display->cached_clk_rate = clk_rate; - if (b_fp_new < 0) { - pr_err("Invalid new_hfp calcluated%d\n", b_fp_new); - return -EINVAL; + rc = dsi_display_update_dsi_bitrate(display, clk_rate); + if (!rc) { + pr_info("%s: bit clk is ready to be configured to '%d'\n", + __func__, clk_rate); + atomic_set(&display->clkrate_change_pending, 1); + } else { + pr_err("%s: Failed to prepare to configure '%d'. rc = %d\n", + __func__, clk_rate, rc); + /* Caching clock failed, so don't go on doing so. */ + atomic_set(&display->clkrate_change_pending, 0); + display->cached_clk_rate = 0; } - /** + return rc; +} + + +static void _dsi_display_calc_pipe_delay(struct dsi_display *display, + struct dsi_dyn_clk_delay *delay, + struct dsi_display_mode *mode) +{ + u32 esc_clk_rate_hz; + u32 pclk_to_esc_ratio, byte_to_esc_ratio, hr_bit_to_esc_ratio; + u32 hsync_period = 0; + struct dsi_display_ctrl *m_ctrl; + struct dsi_ctrl *dsi_ctrl; + struct dsi_phy_cfg *cfg; + + m_ctrl = &display->ctrl[display->clk_master_idx]; + dsi_ctrl = m_ctrl->ctrl; + + cfg = &(m_ctrl->phy->cfg); + + esc_clk_rate_hz = dsi_ctrl->clk_freq.esc_clk_rate * 1000; + pclk_to_esc_ratio = ((dsi_ctrl->clk_freq.pix_clk_rate * 1000) / + esc_clk_rate_hz); + byte_to_esc_ratio = ((dsi_ctrl->clk_freq.byte_clk_rate * 1000) / + esc_clk_rate_hz); + hr_bit_to_esc_ratio = ((dsi_ctrl->clk_freq.byte_clk_rate * 4 * 1000) / + esc_clk_rate_hz); + + hsync_period = DSI_H_TOTAL_DSC(&mode->timing); + delay->pipe_delay = (hsync_period + 1) / pclk_to_esc_ratio; + if (!display->panel->video_config.eof_bllp_lp11_en) + delay->pipe_delay += (17 / pclk_to_esc_ratio) + + ((21 + (display->config.common_config.t_clk_pre + 1) + + (display->config.common_config.t_clk_post + 1)) / + byte_to_esc_ratio) + + ((((cfg->timing.lane_v3[8] >> 1) + 1) + + ((cfg->timing.lane_v3[6] >> 1) + 1) + + ((cfg->timing.lane_v3[3] * 4) + + (cfg->timing.lane_v3[5] >> 1) + 1) + + ((cfg->timing.lane_v3[7] >> 1) + 1) + + ((cfg->timing.lane_v3[1] >> 1) + 1) + + ((cfg->timing.lane_v3[4] >> 1) + 1)) / + hr_bit_to_esc_ratio); + + delay->pipe_delay2 = 0; + if (display->panel->host_config.force_hs_clk_lane) + delay->pipe_delay2 = (6 / byte_to_esc_ratio) + + ((((cfg->timing.lane_v3[1] >> 1) + 1) + + ((cfg->timing.lane_v3[4] >> 1) + 1)) / + hr_bit_to_esc_ratio); + + /* 130 us pll delay recommended by h/w doc */ + delay->pll_delay = ((130 * esc_clk_rate_hz) / 1000000) * 2; +} + +static int _dsi_display_dyn_update_clks(struct dsi_display *display, + struct link_clk_freq *bkp_freq) +{ + int rc = 0, i; + struct dsi_display_ctrl *m_ctrl, *ctrl; + + m_ctrl = &display->ctrl[display->clk_master_idx]; + + dsi_clk_prepare_enable(&display->clock_info.src_clks); + + rc = dsi_clk_update_parent(&display->clock_info.shadow_clks, + &display->clock_info.mux_clks); + if (rc) { + pr_err("failed update mux parent to shadow\n"); + goto exit; + } + + for (i = 0; (i < display->ctrl_count) && + (i < MAX_DSI_CTRLS_PER_DISPLAY); i++) { + ctrl = &display->ctrl[i]; + if (!ctrl->ctrl) + continue; + rc = dsi_clk_set_byte_clk_rate(display->dsi_clk_handle, + ctrl->ctrl->clk_freq.byte_clk_rate, i); + if (rc) { + pr_err("failed to set byte rate for index:%d\n", i); + goto recover_byte_clk; + } + rc = dsi_clk_set_pixel_clk_rate(display->dsi_clk_handle, + ctrl->ctrl->clk_freq.pix_clk_rate, i); + if (rc) { + pr_err("failed to set pix rate for index:%d\n", i); + goto recover_pix_clk; + } + } + + for (i = 0; (i < display->ctrl_count) && + (i < MAX_DSI_CTRLS_PER_DISPLAY); i++) { + ctrl = &display->ctrl[i]; + if (ctrl == m_ctrl) + continue; + dsi_phy_dynamic_refresh_trigger(ctrl->phy, false); + } + dsi_phy_dynamic_refresh_trigger(m_ctrl->phy, true); + + /* wait for dynamic refresh done */ + for (i = 0; (i < display->ctrl_count) && + (i < MAX_DSI_CTRLS_PER_DISPLAY); i++) { + ctrl = &display->ctrl[i]; + rc = dsi_ctrl_wait4dynamic_refresh_done(ctrl->ctrl); + if (rc) { + pr_err("wait4dynamic refresh failed for dsi:%d\n", i); + goto recover_pix_clk; + } else { + pr_info("dynamic refresh done on dsi: %s\n", + i ? "slave" : "master"); + } + } + + for (i = 0; (i < display->ctrl_count) && + (i < MAX_DSI_CTRLS_PER_DISPLAY); i++) { + ctrl = &display->ctrl[i]; + dsi_phy_dynamic_refresh_clear(ctrl->phy); + } + + rc = dsi_clk_update_parent(&display->clock_info.src_clks, + &display->clock_info.mux_clks); + if (rc) + pr_err("could not switch back to src clks %d\n", rc); + + dsi_clk_disable_unprepare(&display->clock_info.src_clks); + + return rc; + +recover_pix_clk: + for (i = 0; (i < display->ctrl_count) && + (i < MAX_DSI_CTRLS_PER_DISPLAY); i++) { + ctrl = &display->ctrl[i]; + if (!ctrl->ctrl) + continue; + dsi_clk_set_pixel_clk_rate(display->dsi_clk_handle, + bkp_freq->pix_clk_rate, i); + } + +recover_byte_clk: + for (i = 0; (i < display->ctrl_count) && + (i < MAX_DSI_CTRLS_PER_DISPLAY); i++) { + ctrl = &display->ctrl[i]; + if (!ctrl->ctrl) + continue; + dsi_clk_set_byte_clk_rate(display->dsi_clk_handle, + bkp_freq->byte_clk_rate, i); + } + +exit: + dsi_clk_disable_unprepare(&display->clock_info.src_clks); + + return rc; +} + +static int dsi_display_dynamic_clk_switch_vid(struct dsi_display *display, + struct dsi_display_mode *mode) +{ + int rc = 0, mask, i; + struct dsi_display_ctrl *m_ctrl, *ctrl; + struct dsi_dyn_clk_delay delay; + struct link_clk_freq bkp_freq; + + dsi_panel_acquire_panel_lock(display->panel); + + m_ctrl = &display->ctrl[display->clk_master_idx]; + + dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_ON); + + /* mask PLL unlock, FIFO overflow and underflow errors */ + mask = BIT(DSI_PLL_UNLOCK_ERR) | BIT(DSI_FIFO_UNDERFLOW) | + BIT(DSI_FIFO_OVERFLOW); + dsi_display_mask_ctrl_error_interrupts(display, mask, true); + + /* update the phy timings based on new mode */ + for (i = 0; i < display->ctrl_count; i++) { + ctrl = &display->ctrl[i]; + dsi_phy_update_phy_timings(ctrl->phy, &display->config); + } + + /* back up existing rates to handle failure case */ + bkp_freq.byte_clk_rate = m_ctrl->ctrl->clk_freq.byte_clk_rate; + bkp_freq.pix_clk_rate = m_ctrl->ctrl->clk_freq.pix_clk_rate; + bkp_freq.esc_clk_rate = m_ctrl->ctrl->clk_freq.esc_clk_rate; + + rc = dsi_display_update_dsi_bitrate(display, mode->timing.clk_rate_hz); + if (rc) { + pr_err("failed set link frequencies %d\n", rc); + goto exit; + } + + /* calculate pipe delays */ + _dsi_display_calc_pipe_delay(display, &delay, mode); + + /* configure dynamic refresh ctrl registers */ + for (i = 0; i < display->ctrl_count; i++) { + ctrl = &display->ctrl[i]; + if (!ctrl->phy) + continue; + if (ctrl == m_ctrl) + dsi_phy_config_dynamic_refresh(ctrl->phy, &delay, true); + else + dsi_phy_config_dynamic_refresh(ctrl->phy, &delay, + false); + } + + rc = _dsi_display_dyn_update_clks(display, &bkp_freq); + +exit: + dsi_display_mask_ctrl_error_interrupts(display, mask, false); + + dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_ALL_CLKS, + DSI_CLK_OFF); + + /* store newly calculated phy timings in mode private info */ + dsi_phy_dyn_refresh_cache_phy_timings(m_ctrl->phy, + mode->priv_info->phy_timing_val, + mode->priv_info->phy_timing_len); + + dsi_panel_release_panel_lock(display->panel); + + return rc; +} + +static int dsi_display_dfps_update(struct dsi_display *display, + struct dsi_display_mode *dsi_mode) +{ + struct dsi_mode_info *timing; + struct dsi_display_ctrl *m_ctrl, *ctrl; + struct dsi_display_mode *panel_mode; + struct dsi_dfps_capabilities dfps_caps; + int rc = 0; + int i = 0; + + if (!display || !dsi_mode || !display->panel) { + pr_err("Invalid params\n"); + return -EINVAL; + } + timing = &dsi_mode->timing; + + dsi_panel_get_dfps_caps(display->panel, &dfps_caps); + if (!dfps_caps.dfps_support) { + pr_err("dfps not supported\n"); + return -ENOTSUPP; + } + + if (dfps_caps.type == DSI_DFPS_IMMEDIATE_CLK) { + pr_err("dfps clock method not supported\n"); + return -ENOTSUPP; + } + + /* For split DSI, update the clock master first */ + + pr_debug("configuring seamless dynamic fps\n\n"); + SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY); + + m_ctrl = &display->ctrl[display->clk_master_idx]; + rc = dsi_ctrl_async_timing_update(m_ctrl->ctrl, timing); + if (rc) { + pr_err("[%s] failed to dfps update host_%d, rc=%d\n", + display->name, i, rc); + goto error; + } + + /* Update the rest of the controllers */ + display_for_each_ctrl(i, display) { + ctrl = &display->ctrl[i]; + if (!ctrl->ctrl || (ctrl == m_ctrl)) + continue; + + rc = dsi_ctrl_async_timing_update(ctrl->ctrl, timing); + if (rc) { + pr_err("[%s] failed to dfps update host_%d, rc=%d\n", + display->name, i, rc); + goto error; + } + } + + panel_mode = display->panel->cur_mode; + memcpy(panel_mode, dsi_mode, sizeof(*panel_mode)); + /* + * dsi_mode_flags flags are used to communicate with other drm driver + * components, and are transient. They aren't inherently part of the + * display panel's mode and shouldn't be saved into the cached currently + * active mode. + */ + panel_mode->dsi_mode_flags = 0; + +error: + SDE_EVT32(SDE_EVTLOG_FUNC_EXIT); + return rc; +} + +static int dsi_display_dfps_calc_front_porch( + u32 old_fps, + u32 new_fps, + u32 a_total, + u32 b_total, + u32 b_fp, + u32 *b_fp_out) +{ + s32 b_fp_new; + int add_porches, diff; + + if (!b_fp_out) { + pr_err("Invalid params"); + return -EINVAL; + } + + if (!a_total || !new_fps) { + pr_err("Invalid pixel total or new fps in mode request\n"); + return -EINVAL; + } + + /* + * Keep clock, other porches constant, use new fps, calc front porch + * new_vtotal = old_vtotal * (old_fps / new_fps ) + * new_vfp - old_vfp = new_vtotal - old_vtotal + * new_vfp = old_vfp + old_vtotal * ((old_fps - new_fps)/ new_fps) + */ + diff = abs(old_fps - new_fps); + add_porches = mult_frac(b_total, diff, new_fps); + + if (old_fps > new_fps) + b_fp_new = b_fp + add_porches; + else + b_fp_new = b_fp - add_porches; + + pr_debug("fps %u a %u b %u b_fp %u new_fp %d\n", + new_fps, a_total, b_total, b_fp, b_fp_new); + + if (b_fp_new < 0) { + pr_err("Invalid new_hfp calcluated%d\n", b_fp_new); + return -EINVAL; + } + + /** * TODO: To differentiate from clock method when communicating to the * other components, perhaps we should set clk here to original value */ @@ -3897,7 +4724,7 @@ static int dsi_display_get_dfps_timing(struct dsi_display *display, dsi_panel_get_dfps_caps(display->panel, &dfps_caps); if (!dfps_caps.dfps_support) { - pr_err("dfps not supported by panel\n"); + //pr_err("dfps not supported by panel\n"); return -EINVAL; } @@ -3979,7 +4806,7 @@ static int dsi_display_set_mode_sub(struct dsi_display *display, struct dsi_display_mode *mode, u32 flags) { - int rc = 0; + int rc = 0, clk_rate = 0; int i; struct dsi_display_ctrl *ctrl; struct dsi_display_mode_priv_info *priv_info; @@ -4011,6 +4838,26 @@ static int dsi_display_set_mode_sub(struct dsi_display *display, display->name, rc); goto error; } + } else if (mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK) { + if (display->panel->panel_mode == DSI_OP_VIDEO_MODE) { + rc = dsi_display_dynamic_clk_switch_vid(display, mode); + if (rc) + pr_err("dynamic clk change failed %d\n", rc); + /* + * skip rest of the opearations since + * dsi_display_dynamic_clk_switch_vid() already takes + * care of them. + */ + return rc; + } else if (display->panel->panel_mode == DSI_OP_CMD_MODE) { + clk_rate = mode->timing.clk_rate_hz; + rc = dsi_display_dynamic_clk_configure_cmd(display, + clk_rate); + if (rc) { + pr_err("Failed to configure dynamic clk\n"); + return rc; + } + } } display_for_each_ctrl(i, display) { @@ -4236,6 +5083,43 @@ int dsi_display_splash_res_cleanup(struct dsi_display *display) return rc; } +static int dsi_display_link_clk_force_update_ctrl(void *handle) +{ + int rc = 0; + + if (!handle) { + pr_err("%s: Invalid arg\n", __func__); + return -EINVAL; + } + + mutex_lock(&dsi_display_clk_mutex); + + rc = dsi_display_link_clk_force_update(handle); + + mutex_unlock(&dsi_display_clk_mutex); + + return rc; +} + +int dsi_display_clk_ctrl(void *handle, + enum dsi_clk_type clk_type, enum dsi_clk_state clk_state) +{ + int rc = 0; + + if (!handle) { + pr_err("%s: Invalid arg\n", __func__); + return -EINVAL; + } + + mutex_lock(&dsi_display_clk_mutex); + rc = dsi_clk_req_state(handle, clk_type, clk_state); + if (rc) + pr_err("%s: failed set clk state, rc = %d\n", __func__, rc); + mutex_unlock(&dsi_display_clk_mutex); + + return rc; +} + static int dsi_display_force_update_dsi_clk(struct dsi_display *display) { int rc = 0; @@ -4254,93 +5138,13 @@ static int dsi_display_force_update_dsi_clk(struct dsi_display *display) return rc; } - -static int dsi_display_request_update_dsi_bitrate(struct dsi_display *display, - u32 bit_clk_rate) +static ssize_t sysfs_dynamic_dsi_clk_read(struct device *dev, + struct device_attribute *attr, char *buf) { int rc = 0; - int i; - - pr_debug("%s:bit rate:%d\n", __func__, bit_clk_rate); - if (!display->panel) { - pr_err("Invalid params\n"); - return -EINVAL; - } - - if (bit_clk_rate == 0) { - pr_err("Invalid bit clock rate\n"); - return -EINVAL; - } - - display->config.bit_clk_rate_hz_override = bit_clk_rate; - - display_for_each_ctrl(i, display) { - struct dsi_display_ctrl *dsi_disp_ctrl = &display->ctrl[i]; - struct dsi_ctrl *ctrl = dsi_disp_ctrl->ctrl; - u32 num_of_lanes = 0; - u32 bpp = 3; - u64 bit_rate, pclk_rate, bit_rate_per_lane, byte_clk_rate; - struct dsi_host_common_cfg *host_cfg; - - mutex_lock(&ctrl->ctrl_lock); - - host_cfg = &display->panel->host_config; - if (host_cfg->data_lanes & DSI_DATA_LANE_0) - num_of_lanes++; - if (host_cfg->data_lanes & DSI_DATA_LANE_1) - num_of_lanes++; - if (host_cfg->data_lanes & DSI_DATA_LANE_2) - num_of_lanes++; - if (host_cfg->data_lanes & DSI_DATA_LANE_3) - num_of_lanes++; - - if (num_of_lanes == 0) { - pr_err("Invalid lane count\n"); - rc = -EINVAL; - goto error; - } - - bit_rate = display->config.bit_clk_rate_hz_override * - num_of_lanes; - bit_rate_per_lane = bit_rate; - do_div(bit_rate_per_lane, num_of_lanes); - pclk_rate = bit_rate; - do_div(pclk_rate, (8 * bpp)); - byte_clk_rate = bit_rate_per_lane; - do_div(byte_clk_rate, 8); - pr_debug("bit_clk_rate = %llu, bit_clk_rate_per_lane = %llu\n", - bit_rate, bit_rate_per_lane); - pr_debug("byte_clk_rate = %llu, pclk_rate = %llu\n", - byte_clk_rate, pclk_rate); - - ctrl->clk_freq.byte_clk_rate = byte_clk_rate; - ctrl->clk_freq.pix_clk_rate = pclk_rate; - rc = dsi_clk_set_link_frequencies(display->dsi_clk_handle, - ctrl->clk_freq, ctrl->cell_index); - if (rc) { - pr_err("Failed to update link frequencies\n"); - goto error; - } - - ctrl->host_config.bit_clk_rate_hz_override = bit_clk_rate; -error: - mutex_unlock(&ctrl->ctrl_lock); - - /* TODO: recover ctrl->clk_freq in case of failure */ - if (rc) - return rc; - } - - return 0; -} - -static ssize_t sysfs_dynamic_dsi_clk_read(struct device *dev, - struct device_attribute *attr, char *buf) -{ - int rc = 0; - struct dsi_display *display; - struct dsi_display_ctrl *m_ctrl; - struct dsi_ctrl *ctrl; + struct dsi_display *display; + struct dsi_display_ctrl *m_ctrl; + struct dsi_ctrl *ctrl; display = dev_get_drvdata(dev); if (!display) { @@ -4368,7 +5172,7 @@ static ssize_t sysfs_dynamic_dsi_clk_read(struct device *dev, static ssize_t sysfs_dynamic_dsi_clk_write(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { - int rc = 0; + int rc = count; int clk_rate; struct dsi_display *display; @@ -4384,44 +5188,29 @@ static ssize_t sysfs_dynamic_dsi_clk_write(struct device *dev, return rc; } - if (clk_rate <= 0) { - pr_err("%s: bitrate should be greater than 0\n", __func__); - return -EINVAL; - } - - if (clk_rate == display->cached_clk_rate) { - pr_info("%s: ignore duplicated DSI clk setting\n", __func__); - return count; + if (display->panel->panel_mode != DSI_OP_CMD_MODE) { + pr_err("only supported for command mode\n"); + return -ENOTSUPP; } pr_info("%s: bitrate param value: '%d'\n", __func__, clk_rate); mutex_lock(&display->display_lock); + mutex_lock(&dsi_display_clk_mutex); - display->cached_clk_rate = clk_rate; - rc = dsi_display_request_update_dsi_bitrate(display, clk_rate); - if (!rc) { - pr_info("%s: bit clk is ready to be configured to '%d'\n", - __func__, clk_rate); - } else { - pr_err("%s: Failed to prepare to configure '%d'. rc = %d\n", - __func__, clk_rate, rc); - /*Caching clock failed, so don't go on doing so.*/ - atomic_set(&display->clkrate_change_pending, 0); - display->cached_clk_rate = 0; - - mutex_unlock(&display->display_lock); - - return rc; - } - atomic_set(&display->clkrate_change_pending, 1); + rc = dsi_display_dynamic_clk_configure_cmd(display, clk_rate); + if (rc) + pr_err("Failed to configure dynamic clk\n"); + mutex_unlock(&dsi_display_clk_mutex); mutex_unlock(&display->display_lock); +// return rc; return count; } + static DEVICE_ATTR(dynamic_dsi_clock, 0644, sysfs_dynamic_dsi_clk_read, sysfs_dynamic_dsi_clk_write); @@ -4495,6 +5284,75 @@ static int dsi_display_sysfs_deinit(struct dsi_display *display) } +static ssize_t bitghtness_event_num_read(struct file *file, char __user *user_buf, size_t count, loff_t *ppos) +{ + int ret = 0; + const char *devname = NULL; + struct input_handle *handle; + + + if (!brightness_input_dev) + return count; + list_for_each_entry(handle, &(brightness_input_dev->h_list), d_node) { + if (strncmp(handle->name, "event", 5) == 0) { + devname = handle->name; + break; + } + } + + ret = simple_read_from_buffer(user_buf, count, ppos, devname, strlen(devname)); + return ret; +} + +static const struct file_operations bitghtness_event_num_fops = { + .read = bitghtness_event_num_read, + .open = simple_open, + .owner = THIS_MODULE, +}; + +static ssize_t screen_state_enable_read(struct file *file, char __user *user_buf, size_t count, loff_t *ppos) +{ + ssize_t ret =0; + char page[4]; + + pr_info("the screen_state_enable is: %d\n", screen_state_enable); + ret = sprintf(page, "%d\n", screen_state_enable); + ret = simple_read_from_buffer(user_buf, count, ppos, page, strlen(page)); + return ret; + +} + +static ssize_t screen_state_enable_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos) +{ + char buf[8]={0}; + + if( count > 2) + count = 2; + if(copy_from_user(buf, buffer, count)){ + pr_err("%s: read proc input error.\n", __func__); + return count; + } + if('0' == buf[0]) { + screen_state_enable = 0; + } else if('1' == buf[0]){ + screen_state_enable = 1; + } + + //if (!screen_state_enable) { + // //notify to epoll thread + // input_event(brightness_input_dev, EV_MSC, MSC_RAW, 2); + // input_sync(brightness_input_dev); + //} + return count; +} + +static const struct file_operations screen_state_enable_fops = { + .read = screen_state_enable_read, + .write = screen_state_enable_write, + .open = simple_open, + .owner = THIS_MODULE, +}; + /** * dsi_display_bind - bind dsi device with controlling device * @dev: Pointer to base of platform device @@ -4848,6 +5706,12 @@ int dsi_display_dev_probe(struct platform_device *pdev) int i, count, rc = 0, index; bool firm_req = false; struct dsi_display_boot_param *boot_disp; + struct proc_dir_entry *prEntry_tmp = NULL; + + prEntry_tp = proc_mkdir("sensor", NULL); + if( prEntry_tp == NULL ){ + pr_err("Couldn't create sensor directory\n"); + } if (!pdev || !pdev->dev.of_node) { pr_err("pdev not found\n"); @@ -4937,6 +5801,36 @@ int dsi_display_dev_probe(struct platform_device *pdev) goto end; } + //create brightness_event_num + prEntry_tmp = proc_create("brightness_event_num", 0664, prEntry_tp, &bitghtness_event_num_fops); + if (prEntry_tmp == NULL) { + pr_err("Couldn't create tp_event_num_fops\n"); + return 0; + } + //create screen_state_enable + prEntry_tmp = proc_create("screen_state_enable", 0666, prEntry_tp, &screen_state_enable_fops); + if (prEntry_tmp == NULL) { + pr_err("Couldn't create screen_state_enable_fops\n"); + return 0; + } + + //create input event + brightness_input_dev = input_allocate_device(); + if (brightness_input_dev == NULL) { + pr_err("Failed to allocate ps input device\n"); + return 0; + } + brightness_input_dev->name = "oneplus,brightness"; + + set_bit(EV_MSC, brightness_input_dev->evbit); + set_bit(MSC_RAW, brightness_input_dev->mscbit); + + if (input_register_device(brightness_input_dev)) { + pr_err("%s: Failed to register brightness input device\n", __func__); + input_free_device(brightness_input_dev); + return 0; + } + return 0; end: if (display) @@ -4955,6 +5849,10 @@ int dsi_display_dev_remove(struct platform_device *pdev) return -EINVAL; } + printk(KERN_ERR"unregister_device brightness_input_dev...\n"); + input_unregister_device(brightness_input_dev); + input_free_device(brightness_input_dev); + display = platform_get_drvdata(pdev); /* decrement ref count */ @@ -5554,7 +6452,8 @@ static int dsi_display_get_mode_count_no_lock(struct dsi_display *display, u32 *count) { struct dsi_dfps_capabilities dfps_caps; - int num_dfps_rates, rc = 0; + struct dsi_dyn_clk_caps *dyn_clk_caps; + int num_dfps_rates, num_bit_clks, rc = 0; if (!display || !display->panel) { pr_err("invalid display:%d panel:%d\n", display != NULL, @@ -5571,12 +6470,16 @@ static int dsi_display_get_mode_count_no_lock(struct dsi_display *display, return rc; } - num_dfps_rates = !dfps_caps.dfps_support ? 1 : - dfps_caps.max_refresh_rate - - dfps_caps.min_refresh_rate + 1; + num_dfps_rates = !dfps_caps.dfps_support ? 1 : dfps_caps.dfps_list_len; + + dyn_clk_caps = &(display->panel->dyn_clk_caps); - /* Inflate num_of_modes by fps in dfps */ - *count = display->panel->num_timing_nodes * num_dfps_rates; + num_bit_clks = !dyn_clk_caps->dyn_clk_support ? 1 : + dyn_clk_caps->bit_clk_list_len; + + /* Inflate num_of_modes by fps and bit clks in dfps */ + *count = display->panel->num_timing_nodes * + num_dfps_rates * num_bit_clks; return 0; } @@ -5599,6 +6502,73 @@ int dsi_display_get_mode_count(struct dsi_display *display, return 0; } +static void _dsi_display_populate_bit_clks(struct dsi_display *display, + int start, int end, u32 *mode_idx) +{ + struct dsi_dyn_clk_caps *dyn_clk_caps; + struct dsi_display_mode *src, *dst; + struct dsi_host_common_cfg *cfg; + int i, j, total_modes, bpp, lanes = 0; + + if (!display || !mode_idx) + return; + + dyn_clk_caps = &(display->panel->dyn_clk_caps); + if (!dyn_clk_caps->dyn_clk_support) + return; + + cfg = &(display->panel->host_config); + bpp = dsi_pixel_format_to_bpp(cfg->dst_format); + + if (cfg->data_lanes & DSI_DATA_LANE_0) + lanes++; + if (cfg->data_lanes & DSI_DATA_LANE_1) + lanes++; + if (cfg->data_lanes & DSI_DATA_LANE_2) + lanes++; + if (cfg->data_lanes & DSI_DATA_LANE_3) + lanes++; + + dsi_display_get_mode_count_no_lock(display, &total_modes); + + for (i = start; i < end; i++) { + src = &display->modes[i]; + if (!src) + return; + /* + * TODO: currently setting the first bit rate in + * the list as preferred rate. But ideally should + * be based on user or device tree preferrence. + */ + src->timing.clk_rate_hz = dyn_clk_caps->bit_clk_list[0]; + src->pixel_clk_khz = + div_u64(src->timing.clk_rate_hz * lanes, bpp); + src->pixel_clk_khz /= 1000; + src->pixel_clk_khz *= display->ctrl_count; + } + + for (i = 1; i < dyn_clk_caps->bit_clk_list_len; i++) { + if (*mode_idx >= total_modes) + return; + for (j = start; j < end; j++) { + src = &display->modes[j]; + dst = &display->modes[*mode_idx]; + + if (!src || !dst) { + pr_err("invalid mode index\n"); + return; + } + memcpy(dst, src, sizeof(struct dsi_display_mode)); + dst->timing.clk_rate_hz = dyn_clk_caps->bit_clk_list[i]; + dst->pixel_clk_khz = + div_u64(dst->timing.clk_rate_hz * lanes, bpp); + dst->pixel_clk_khz /= 1000; + dst->pixel_clk_khz *= display->ctrl_count; + (*mode_idx)++; + } + } +} + void dsi_display_put_mode(struct dsi_display *display, struct dsi_display_mode *mode) { @@ -5613,7 +6583,8 @@ int dsi_display_get_modes(struct dsi_display *display, bool is_split_link; u32 num_dfps_rates, panel_mode_count, total_mode_count; u32 sublinks_count, mode_idx, array_idx = 0; - int i, rc = -EINVAL; + struct dsi_dyn_clk_caps *dyn_clk_caps; + int i, start, end, rc = -EINVAL; if (!display || !out_modes) { pr_err("Invalid params\n"); @@ -5622,6 +6593,8 @@ int dsi_display_get_modes(struct dsi_display *display, *out_modes = NULL; + pr_err("%s start\n", __func__); + mutex_lock(&display->display_lock); if (display->modes) @@ -5645,10 +6618,12 @@ int dsi_display_get_modes(struct dsi_display *display, goto error; } - num_dfps_rates = !dfps_caps.dfps_support ? 1 : - dfps_caps.max_refresh_rate - - dfps_caps.min_refresh_rate + 1; + dyn_clk_caps = &(display->panel->dyn_clk_caps); + +// num_dfps_rates = !dfps_caps.dfps_support ? 1 : dfps_caps.dfps_list_len; + dyn_clk_caps = &(display->panel->dyn_clk_caps); + num_dfps_rates = !dfps_caps.dfps_support ? 1 : dfps_caps.dfps_list_len; panel_mode_count = display->panel->num_timing_nodes; for (mode_idx = 0; mode_idx < panel_mode_count; mode_idx++) { @@ -5677,7 +6652,7 @@ int dsi_display_get_modes(struct dsi_display *display, panel_mode.timing.h_back_porch *= sublinks_count; panel_mode.timing.h_skew *= sublinks_count; panel_mode.pixel_clk_khz *= sublinks_count; - } else if (display->ctrl_count > 1) { + } else { panel_mode.timing.h_active *= display->ctrl_count; panel_mode.timing.h_front_porch *= display->ctrl_count; panel_mode.timing.h_sync_width *= display->ctrl_count; @@ -5686,6 +6661,8 @@ int dsi_display_get_modes(struct dsi_display *display, panel_mode.pixel_clk_khz *= display->ctrl_count; } + start = array_idx; + for (i = 0; i < num_dfps_rates; i++) { struct dsi_display_mode *sub_mode = &display->modes[array_idx]; @@ -5698,28 +6675,28 @@ int dsi_display_get_modes(struct dsi_display *display, } memcpy(sub_mode, &panel_mode, sizeof(panel_mode)); + array_idx++; - if (dfps_caps.dfps_support) { - curr_refresh_rate = - sub_mode->timing.refresh_rate; - sub_mode->timing.refresh_rate = - dfps_caps.min_refresh_rate + - (i % num_dfps_rates); + if (!dfps_caps.dfps_support) + continue; - dsi_display_get_dfps_timing(display, - sub_mode, curr_refresh_rate); + curr_refresh_rate = sub_mode->timing.refresh_rate; + sub_mode->timing.refresh_rate = dfps_caps.dfps_list[i]; - sub_mode->pixel_clk_khz = - (DSI_H_TOTAL_DSC(&sub_mode->timing) * - DSI_V_TOTAL(&sub_mode->timing) * - sub_mode->timing.refresh_rate) / 1000; - } - array_idx++; + dsi_display_get_dfps_timing(display, sub_mode, + curr_refresh_rate); } + end = array_idx; + /* + * if dynamic clk switch is supported then update all the bit + * clk rates. + */ + _dsi_display_populate_bit_clks(display, start, end, &array_idx); } exit: *out_modes = display->modes; + primary_display = display; rc = 0; error: @@ -5727,6 +6704,8 @@ int dsi_display_get_modes(struct dsi_display *display, kfree(display->modes); mutex_unlock(&display->display_lock); + + pr_err("%s end\n", __func__); return rc; } @@ -5812,7 +6791,8 @@ int dsi_display_find_mode(struct dsi_display *display, if (cmp->timing.v_active == m->timing.v_active && cmp->timing.h_active == m->timing.h_active && - cmp->timing.refresh_rate == m->timing.refresh_rate) { + cmp->timing.refresh_rate == m->timing.refresh_rate && + cmp->pixel_clk_khz == m->pixel_clk_khz) { *out_mode = m; rc = 0; break; @@ -5821,9 +6801,10 @@ int dsi_display_find_mode(struct dsi_display *display, mutex_unlock(&display->display_lock); if (!*out_mode) { - pr_err("[%s] failed to find mode for v_active %u h_active %u rate %u\n", + pr_err("[%s] failed to find mode for v_active %u h_active %u fps %u pclk %u\n", display->name, cmp->timing.v_active, - cmp->timing.h_active, cmp->timing.refresh_rate); + cmp->timing.h_active, cmp->timing.refresh_rate, + cmp->pixel_clk_khz); rc = -ENOENT; } @@ -5831,7 +6812,7 @@ int dsi_display_find_mode(struct dsi_display *display, } /** - * dsi_display_validate_mode_vrr() - Validate if varaible refresh case. + * dsi_display_validate_mode_change() - Validate if varaible refresh case. * @display: DSI display handle. * @cur_dsi_mode: Current DSI mode. * @mode: Mode value structure to be validated. @@ -5839,16 +6820,20 @@ int dsi_display_find_mode(struct dsi_display *display, * is change in fps but vactive and hactive are same. * Return: error code. */ -int dsi_display_validate_mode_vrr(struct dsi_display *display, - struct dsi_display_mode *cur_dsi_mode, - struct dsi_display_mode *mode) +u32 mode_fps = 90; +EXPORT_SYMBOL(mode_fps); +int dsi_display_validate_mode_change(struct dsi_display *display, + struct dsi_display_mode *cur_mode, + struct dsi_display_mode *adj_mode) { int rc = 0; - struct dsi_display_mode adj_mode, cur_mode; struct dsi_dfps_capabilities dfps_caps; - u32 curr_refresh_rate; + struct dsi_dyn_clk_caps *dyn_clk_caps; - if (!display || !mode) { + struct msm_drm_notifier notifier_data; + int dynamic_fps; + + if (!display || !adj_mode) { pr_err("Invalid params\n"); return -EINVAL; } @@ -5860,65 +6845,53 @@ int dsi_display_validate_mode_vrr(struct dsi_display *display, mutex_lock(&display->display_lock); - adj_mode = *mode; - cur_mode = *cur_dsi_mode; - - if ((cur_mode.timing.refresh_rate != adj_mode.timing.refresh_rate) && - (cur_mode.timing.v_active == adj_mode.timing.v_active) && - (cur_mode.timing.h_active == adj_mode.timing.h_active)) { - - curr_refresh_rate = cur_mode.timing.refresh_rate; - rc = dsi_panel_get_dfps_caps(display->panel, &dfps_caps); - if (rc) { - pr_err("[%s] failed to get dfps caps from panel\n", - display->name); - goto error; - } - - cur_mode.timing.refresh_rate = - adj_mode.timing.refresh_rate; + if ((cur_mode->timing.v_active == adj_mode->timing.v_active) && + (cur_mode->timing.h_active == adj_mode->timing.h_active)) { + /* dfps change use case */ + if (cur_mode->timing.refresh_rate != + adj_mode->timing.refresh_rate) { + dsi_panel_get_dfps_caps(display->panel, &dfps_caps); + + if (mode_fps != adj_mode->timing.refresh_rate) { + mode_fps = adj_mode->timing.refresh_rate; + dynamic_fps = mode_fps; + notifier_data.data = &dynamic_fps; + notifier_data.id = MSM_DRM_PRIMARY_DISPLAY; + pr_err("set fps: %d\n", dynamic_fps); + msm_drm_notifier_call_chain(MSM_DRM_EARLY_EVENT_BLANK, ¬ifier_data); + } - rc = dsi_display_get_dfps_timing(display, - &cur_mode, curr_refresh_rate); - if (rc) { - pr_err("[%s] seamless vrr not possible rc=%d\n", - display->name, rc); - goto error; + if (!dfps_caps.dfps_support) { + pr_err("invalid mode dfps not supported\n"); + rc = -ENOTSUPP; + goto error; + } + pr_debug("Mode switch is seamless variable refresh\n"); + adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR; + SDE_EVT32(cur_mode->timing.refresh_rate, + adj_mode->timing.refresh_rate, + cur_mode->timing.h_front_porch, + adj_mode->timing.h_front_porch); } - switch (dfps_caps.type) { - /* - * Ignore any round off factors in porch calculation. - * Worse case is set to 5. - */ - case DSI_DFPS_IMMEDIATE_VFP: - if (abs(DSI_V_TOTAL(&cur_mode.timing) - - DSI_V_TOTAL(&adj_mode.timing)) > 5) - pr_err("Mismatch vfp fps:%d new:%d given:%d\n", - adj_mode.timing.refresh_rate, - cur_mode.timing.v_front_porch, - adj_mode.timing.v_front_porch); - break; - - case DSI_DFPS_IMMEDIATE_HFP: - if (abs(DSI_H_TOTAL_DSC(&cur_mode.timing) - - DSI_H_TOTAL_DSC(&adj_mode.timing)) > 5) - pr_err("Mismatch hfp fps:%d new:%d given:%d\n", - adj_mode.timing.refresh_rate, - cur_mode.timing.h_front_porch, - adj_mode.timing.h_front_porch); - break; - default: - pr_err("Unsupported DFPS mode %d\n", - dfps_caps.type); - rc = -ENOTSUPP; + /* dynamic clk change use case */ + if (cur_mode->pixel_clk_khz != adj_mode->pixel_clk_khz) { + dyn_clk_caps = &(display->panel->dyn_clk_caps); + if (!dyn_clk_caps->dyn_clk_support) { + pr_err("dyn clk change not supported\n"); + rc = -ENOTSUPP; + goto error; + } + if (adj_mode->dsi_mode_flags & DSI_MODE_FLAG_VRR) { + pr_err("dfps and dyn clk not supported in same commit\n"); + rc = -ENOTSUPP; + goto error; + } + pr_debug("dynamic clk change detected\n"); + adj_mode->dsi_mode_flags |= DSI_MODE_FLAG_DYN_CLK; + SDE_EVT32(cur_mode->pixel_clk_khz, + adj_mode->pixel_clk_khz); } - - pr_debug("Mode switch is seamless variable refresh\n"); - mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR; - SDE_EVT32(curr_refresh_rate, adj_mode.timing.refresh_rate, - cur_mode.timing.h_front_porch, - adj_mode.timing.h_front_porch); } error: @@ -5995,7 +6968,6 @@ int dsi_display_set_mode(struct dsi_display *display, pr_err("Invalid params\n"); return -EINVAL; } - mutex_lock(&display->display_lock); adj_mode = *mode; @@ -6010,7 +6982,6 @@ int dsi_display_set_mode(struct dsi_display *display, pr_err("[%s] mode cannot be set\n", display->name); goto error; } - rc = dsi_display_set_mode_sub(display, &adj_mode, flags); if (rc) { pr_err("[%s] failed to set mode\n", display->name); @@ -6027,6 +6998,7 @@ int dsi_display_set_mode(struct dsi_display *display, } memcpy(display->panel->cur_mode, &adj_mode, sizeof(adj_mode)); + error: mutex_unlock(&display->display_lock); return rc; @@ -6407,9 +7379,6 @@ int dsi_display_prepare(struct dsi_display *display) dsi_display_set_ctrl_esd_check_flag(display, false); - /* Set up ctrl isr before enabling core clk */ - dsi_display_ctrl_isr_configure(display, true); - if (mode->dsi_mode_flags & DSI_MODE_FLAG_DMS) { if (display->is_cont_splash_enabled) { pr_err("DMS is not supposed to be set on first frame\n"); @@ -6437,6 +7406,9 @@ int dsi_display_prepare(struct dsi_display *display) } } + /* Set up ctrl isr before enabling core clk */ + dsi_display_ctrl_isr_configure(display, true); + rc = dsi_display_clk_ctrl(display->dsi_clk_handle, DSI_CORE_CLK, DSI_CLK_ON); if (rc) { @@ -6698,6 +7670,7 @@ int dsi_display_pre_kickoff(struct drm_connector *connector, int i; bool enable; + SDE_ATRACE_BEGIN("dsi_display_pre_kickoff"); /* check and setup MISR */ if (display->misr_enable) _dsi_display_setup_misr(display); @@ -6748,6 +7721,7 @@ int dsi_display_pre_kickoff(struct drm_connector *connector, mutex_unlock(&display->display_lock); } + SDE_ATRACE_END("dsi_display_pre_kickoff"); return rc; } @@ -6800,7 +7774,6 @@ int dsi_display_enable(struct dsi_display *display) pr_err("Invalid params\n"); return -EINVAL; } - if (!display->panel->cur_mode) { pr_err("no valid mode set for the display"); return -EINVAL; @@ -6810,6 +7783,8 @@ int dsi_display_enable(struct dsi_display *display) /* Engine states and panel states are populated during splash * resource init and hence we return early */ + SDE_ATRACE_BEGIN("dsi_display_enable"); + if (display->is_cont_splash_enabled) { dsi_display_config_ctrl_for_cont_splash(display); @@ -6892,6 +7867,8 @@ int dsi_display_enable(struct dsi_display *display) error: mutex_unlock(&display->display_lock); SDE_EVT32(SDE_EVTLOG_FUNC_EXIT); + + SDE_ATRACE_END("dsi_display_enable"); return rc; } @@ -7004,73 +7981,2088 @@ int dsi_display_update_pps(char *pps_cmd, void *disp) return 0; } -int dsi_display_unprepare(struct dsi_display *display) +int dsi_display_set_acl_mode(struct drm_connector *connector, int level) { + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; int rc = 0; - if (!display) { - pr_err("Invalid params\n"); - return -EINVAL; - } + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; - SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY); - mutex_lock(&display->display_lock); + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; - rc = dsi_display_wake_up(display); - if (rc) - pr_err("[%s] display wake up failed, rc=%d\n", - display->name, rc); + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; - rc = dsi_panel_unprepare(display->panel); - if (rc) - pr_err("[%s] panel unprepare failed, rc=%d\n", - display->name, rc); + panel = dsi_display->panel; - rc = dsi_display_ctrl_host_disable(display); - if (rc) - pr_err("[%s] failed to disable DSI host, rc=%d\n", - display->name, rc); + mutex_lock(&dsi_display->display_lock); - rc = dsi_display_clk_ctrl(display->dsi_clk_handle, - DSI_LINK_CLK, DSI_CLK_OFF); - if (rc) - pr_err("[%s] failed to disable Link clocks, rc=%d\n", - display->name, rc); + panel->acl_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } - rc = dsi_display_ctrl_deinit(display); + rc = dsi_panel_set_acl_mode(panel, level); if (rc) - pr_err("[%s] failed to deinit controller, rc=%d\n", - display->name, rc); + pr_err("unable to set acl mode\n"); - if (!display->panel->ulps_suspend_enabled) { - rc = dsi_display_phy_disable(display); - if (rc) - pr_err("[%s] failed to disable DSI PHY, rc=%d\n", - display->name, rc); + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} - rc = dsi_display_clk_ctrl(display->dsi_clk_handle, - DSI_CORE_CLK, DSI_CLK_OFF); - if (rc) - pr_err("[%s] failed to disable DSI clocks, rc=%d\n", - display->name, rc); +int dsi_display_get_acl_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; - /* destrory dsi isr set up */ - dsi_display_ctrl_isr_configure(display, false); + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; - rc = dsi_panel_post_unprepare(display->panel); - if (rc) - pr_err("[%s] panel post-unprepare failed, rc=%d\n", - display->name, rc); + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; - mutex_unlock(&display->display_lock); + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; - /* Free up DSI ERROR event callback */ - dsi_display_unregister_error_handler(display); + return dsi_display->panel->acl_mode; +} + +int dsi_display_get_gamma_para(struct dsi_display *dsi_display, struct dsi_panel *panel) +{ + int i = 0; + int j = 0; + int rc = 0; + int flags = 0; + char fb[13] = {0}; + //char c8[135] = {0}; + //char c9[180] = {0}; + char b3[47] = {0}; + char fb_temp[13] = {0}; + char c8_temp[135] = {0}; + char c9_temp[180] = {0}; + char b3_temp[47] = {0}; + char gamma_para_60hz[452] = {0}; + int check_sum_60hz = 0; + + struct dsi_cmd_desc *cmds; + struct dsi_display_mode *mode; + struct dsi_display_ctrl *m_ctrl; + + pr_err("%s start\n", __func__); + + m_ctrl = &dsi_display->ctrl[dsi_display->cmd_master_idx]; + if (!panel || !m_ctrl) + return -EINVAL; + + rc = dsi_display_cmd_engine_enable(dsi_display); + if (rc) { + pr_err("cmd engine enable failed\n"); + return -EINVAL; + } + + dsi_panel_acquire_panel_lock(panel); + mode = panel->cur_mode; + +/* Read 60hz gamma para */ + do { + check_sum_60hz = 0; + if (j > 0) { + pr_err("Failed to read the 60hz gamma parameters %d!", j); + for (i = 0; i < 52; i++) { + if (i != 51) { + pr_err("[60hz][%d]0x%02X,[%d]0x%02X,[%d]0x%02X,[%d]0x%02X,[%d]0x%02X,[%d]0x%02X,[%d]0x%02X,[%d]0x%02X", + i*8, gamma_para[0][i*8], i*8+1, gamma_para[0][i*8+1], i*8+2, gamma_para[0][i*8+2], i*8+3, gamma_para[0][i*8+3], i*8+4, gamma_para[0][i*8+4], + i*8+5, gamma_para[0][i*8+5], i*8+6, gamma_para[0][i*8+6], i*8+7, gamma_para[0][i*8+7]); + } + else { + pr_err("[60hz][%d]0x%02X,[%d]0x%02X,[%d]0x%02X,[%d]0x%02X,[%d]0x%02X", + i*8, gamma_para[0][i*8], i*8+1, gamma_para[0][i*8+1], i*8+2, gamma_para[0][i*8+2], i*8+3, gamma_para[0][i*8+3], i*8+4, gamma_para[0][i*8+4]); + } + } + mdelay(100); + } + for(i = 0; i < 452; i++) + { + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_GAMMA_FLASH_PRE_READ_1); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_GAMMA_FLASH_PRE_READ_1 command\n"); + goto error; + } + + rc = dsi_panel_gamma_read_address_setting(panel, i); + if (rc) { + pr_err("Failed to set gamma read address\n"); + goto error; + } + + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_GAMMA_FLASH_PRE_READ_2); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_GAMMA_FLASH_PRE_READ_2 command\n"); + goto error; + } + + flags = 0; + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_GAMMA_FLASH_READ_FB].cmds; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + if (!m_ctrl->ctrl->vaddr) + goto error; + cmds->msg.rx_buf = fb_temp; + cmds->msg.rx_len = 13; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + if (rc <= 0) { + pr_err("Failed to read DSI_CMD_SET_GAMMA_FLASH_READ_FB\n"); + goto error; + } + memcpy(fb, cmds->msg.rx_buf, 13); + + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_LEVEL2_KEY_DISABLE); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_LEVEL2_KEY_DISABLE command\n"); + goto error; + } + + if (i < 135) { + gamma_para[0][i+18] = fb[12]; + } + else if (i < 315) { + gamma_para[0][i+26] = fb[12]; + } + else if (i < 360) { + gamma_para[0][i+43] = fb[12]; + } + + gamma_para_60hz[i] = fb[12]; + if (i < 449) { + check_sum_60hz = gamma_para_60hz[i] + check_sum_60hz; + } + } + j++; + } + while ((check_sum_60hz != (gamma_para_60hz[450] << 8) + gamma_para_60hz[451]) && (j < 5)); + + if (check_sum_60hz == (gamma_para_60hz[450] << 8) + gamma_para_60hz[451]) { + pr_err("Read 60hz gamma done\n"); + } + else { + pr_err("Failed to read 60hz gamma, use 90hz gamma.\n"); + gamma_read_flag = GAMMA_READ_ERROR; + } + +/* Read 90hz gamma para */ + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_LEVEL2_KEY_ENABLE); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_LEVEL2_KEY_ENABLE command\n"); + goto error; + } + + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_GAMMA_OTP_READ_C8_SMRPS); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_GAMMA_OTP_READ_C8_SMRPS command\n"); + goto error; + } + + flags = 0; + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_GAMMA_OTP_READ_C8].cmds; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds->msg.rx_buf = c8_temp; + cmds->msg.rx_len = 135; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + if (rc <= 0) { + pr_err("Failed to read DSI_CMD_SET_GAMMA_OTP_READ_C8\n"); + goto error; + } + memcpy(&gamma_para[1][18], cmds->msg.rx_buf, 135); + + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_GAMMA_OTP_READ_C9_SMRPS); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_GAMMA_OTP_READ_C9_SMRPS command\n"); + goto error; + } + + flags = 0; + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_GAMMA_OTP_READ_C9].cmds; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds->msg.rx_buf = c9_temp; + cmds->msg.rx_len = 180; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + if (rc <= 0) { + pr_err("Failed to read DSI_CMD_SET_GAMMA_OTP_READ_C9\n"); + goto error; + } + memcpy(&gamma_para[1][161], cmds->msg.rx_buf, 180); + + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_GAMMA_OTP_READ_B3_SMRPS); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_GAMMA_OTP_READ_C9_SMRPS command\n"); + goto error; + } + + flags = 0; + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_GAMMA_OTP_READ_B3].cmds; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + cmds->msg.rx_buf = b3_temp; + cmds->msg.rx_len = 47; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + if (rc <= 0) { + pr_err("Failed to read DSI_CMD_SET_GAMMA_OTP_READ_B3\n"); + goto error; + } + memcpy(b3, cmds->msg.rx_buf, 47); + memcpy(&gamma_para[1][358], &b3[2], 45); + + rc = dsi_panel_tx_cmd_set(panel, DSI_CMD_SET_LEVEL2_KEY_DISABLE); + if (rc) { + pr_err("Failed to send DSI_CMD_SET_GAMMA_OTP_READ_C9_SMRPS command\n"); + goto error; + } + pr_err("Read 90hz gamma done\n"); - SDE_EVT32(SDE_EVTLOG_FUNC_EXIT); - return rc; +error: + dsi_panel_release_panel_lock(panel); + dsi_display_cmd_engine_disable(dsi_display); + pr_err("%s end\n", __func__); + return rc; +} + +int dsi_display_gamma_read(struct dsi_display *dsi_display) +{ + int rc = 0; + struct dsi_panel *panel = NULL; + + pr_err("%s start\n", __func__); + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + mutex_lock(&dsi_display->display_lock); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI clocks, rc=%d\n", dsi_display->name, rc); + goto error; + } + + dsi_display_get_gamma_para(dsi_display, panel); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, DSI_ALL_CLKS, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI clocks, rc=%d\n", dsi_display->name, rc); + goto error; + } + +error: + mutex_unlock(&dsi_display->display_lock); + pr_err("%s end\n", __func__); + return rc; +} + +int dsi_display_read_serial_number(struct dsi_display *dsi_display, + struct dsi_panel *panel, char *buf, int len) +{ + int rc = 0; + u32 flags = 0; + struct dsi_cmd_desc *cmds; + struct dsi_display_mode *mode; + struct dsi_display_ctrl *m_ctrl; + int stage_info = 0; + int prodution_info = 0; + + pr_err("%s start\n", __func__); + + m_ctrl = &dsi_display->ctrl[dsi_display->cmd_master_idx]; + + if (!panel || !m_ctrl) + return -EINVAL; + + rc = dsi_display_cmd_engine_enable(dsi_display); + if (rc) { + pr_err("cmd engine enable failed\n"); + return -EINVAL; + } + + dsi_panel_acquire_panel_lock(panel); + + mode = panel->cur_mode; + + if(strcmp(dsi_display->panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0) { + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_SET_LCDINFO_PRE); + } + + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_SERIAL_NUMBER].cmds; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + if (!m_ctrl->ctrl->vaddr) + goto error; + cmds->msg.rx_buf = buf; + cmds->msg.rx_len = len; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + if (rc <= 0) + pr_err("Failed to get panel serial number, rc=%d\n", rc); + + if(strcmp(dsi_display->panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0) { + flags = 0; + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_STAGE_INFO].cmds; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + if (!m_ctrl->ctrl->vaddr) + goto error; + cmds->msg.rx_buf = &stage_info; + cmds->msg.rx_len = 1; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + if (rc <= 0) + pr_err("Failed to get stage info, rc=%d\n", rc); + + panel->panel_stage_info = stage_info & 0xff; + pr_err("Stage info is 0x%X\n", panel->panel_stage_info); + + flags = 0; + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_PRODUCTION_INFO].cmds; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + if (!m_ctrl->ctrl->vaddr) + goto error; + cmds->msg.rx_buf = &prodution_info; + cmds->msg.rx_len = 1; + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + if (rc <= 0) + pr_err("Failed to get production info, rc=%d\n", rc); + + panel->panel_production_info = prodution_info & 0xff; + pr_err("Production info is 0x%X\n", panel->panel_production_info); + + // memcpy(temp_buffer, cmds->msg.rx_buf, len); + rc = dsi_panel_tx_cmd_set_op(panel, DSI_CMD_SET_LCDINFO_POST); + // for(test =0; test < 16; test++){ + // printk(KERN_ERR"OLED manufacture= %x\n",temp_buffer[test]); + // } + } + + error: + dsi_panel_release_panel_lock(panel); + + dsi_display_cmd_engine_disable(dsi_display); + pr_err("%s end\n", __func__); + + return rc; +} + +int dsi_display_get_serial_number(struct drm_connector *connector) +{ + struct dsi_display_mode *mode; + struct dsi_panel *panel = NULL; + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + char buf[32]; + int panel_year = 0; + int panel_mon = 0; + int panel_day = 0; + int panel_hour = 0; + int panel_min = 0; + int panel_sec = 0; + int len = 0; + u32 count; + int rc = 0; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + mutex_lock(&dsi_display->display_lock); + + if (!dsi_panel_initialized(panel) || !panel->cur_mode) { + goto error; + } + mode = panel->cur_mode; + count = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_SERIAL_NUMBER].count; + + if (count) { + + len = panel->panel_min_index; + if (len > sizeof(buf)) { + pr_err("len is large than buf size!!!\n" ); + goto error; + } + + if ((panel->panel_year_index > len) || (panel->panel_mon_index > len) + || (panel->panel_day_index > len) || (panel->panel_hour_index > len) + || (panel->panel_min_index > len)) { + pr_err("Panel serial number index not corrected.\n"); + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_ALL_CLKS, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + memset(buf, 0, sizeof(buf)); + dsi_display_read_serial_number(dsi_display, panel, buf, len); + memcpy(panel->buf_id, buf, 32); + panel_year = 2011 + ((buf[panel->panel_year_index-1] >> 4) & 0x0f); + if (panel_year == 2011){ + panel_year = 0; + } + panel_mon = buf[panel->panel_mon_index-1] & 0x0f; + if ((panel_mon > 12) || (panel_mon < 1)){ + pr_err("Panel Mon not corrected.\n"); + panel_mon = 0; + } + panel_day = buf[panel->panel_day_index-1] & 0x3f; + if ((panel_day > 31) || (panel_day < 1)){ + pr_err("Panel Day not corrected.\n"); + panel_day = 0; + } + panel_hour = buf[panel->panel_hour_index-1] & 0x3f; + if ((panel_hour > 23) || (panel_hour < 0)){ + pr_err("Panel Hour not corrected.\n"); + panel_hour = 0; + } + panel_min = buf[panel->panel_min_index-1] & 0x3f; + if ((panel_min > 59) || (panel_min < 0)){ + pr_err("Panel Min not corrected.\n"); + panel_min = 0; + } + panel_sec = buf[panel->panel_sec_index-1] & 0x3f; + if ((panel_sec > 59) || (panel_sec < 0)){ + pr_err("Panel sec not corrected.\n"); + panel_sec = 0; + } + panel->panel_year = panel_year; + panel->panel_mon = panel_mon; + panel->panel_day = panel_day; + panel->panel_hour = panel_hour; + panel->panel_min = panel_min; + panel->panel_sec = panel_sec; + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_ALL_CLKS, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to enable DSI clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + } else{ + pr_err("This panel not support serial number.\n"); + } +error: + mutex_unlock(&dsi_display->display_lock); + pr_err("%s start\n", __func__); + return 0; +} + +int dsi_display_update_panel_id_and_gamma_para(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return -EINVAL; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + dsi_display_get_serial_number(connector); + rc = dsi_display_gamma_read(dsi_display); + if (rc) { + pr_err("Failed to read gamma para, rc=%d\n", rc); + } + + return rc; +} + +int dsi_display_get_serial_number_year(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + return dsi_display->panel->panel_year; +} + +int dsi_display_get_serial_number_mon(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + return dsi_display->panel->panel_mon; +} + +int dsi_display_get_serial_number_day(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + return dsi_display->panel->panel_day; +} + +int dsi_display_get_serial_number_hour(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + return dsi_display->panel->panel_hour; +} + +int dsi_display_get_serial_number_min(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + return dsi_display->panel->panel_min; +} + +int dsi_display_get_serial_number_sec(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + return dsi_display->panel->panel_sec; +} + +int dsi_display_get_stage_info(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + if(strcmp(dsi_display->panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0){ + return dsi_display->panel->panel_stage_info; + } + else + return 0xFF; +} + +int dsi_display_get_production_info(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + pr_err("%s end\n", __func__); + + if(strcmp(dsi_display->panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0){ + return dsi_display->panel->panel_production_info; + } + else + return 0xFF; +} + +int dsi_display_get_serial_number_AT(struct drm_connector *connector) +{ + struct dsi_display_mode *mode; + struct dsi_panel *panel = NULL; + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + char buf[32]; + int panel_year = 0; + int panel_mon = 0; + int panel_day = 0; + int panel_hour = 0; + int panel_min = 0; + int panel_sec = 0; + int len = 0; + u32 count; + int rc = 0; + uint64_t serial_number; + pr_err("%s start\n", __func__); + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + mutex_lock(&dsi_display->display_lock); + + if (!dsi_panel_initialized(panel) || !panel->cur_mode) { + goto error; + } + mode = panel->cur_mode; + count = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_SERIAL_NUMBER].count; + + if (count) { + + len = panel->panel_min_index; + if (len > sizeof(buf)) { + pr_err("len is large than buf size!!!\n" ); + goto error; + } + + if ((panel->panel_year_index > len) || (panel->panel_mon_index > len) + || (panel->panel_day_index > len) || (panel->panel_hour_index > len) + || (panel->panel_min_index > len)) { + pr_err("Panel serial number index not corrected.\n"); + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_ALL_CLKS, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + memset(buf, 0, sizeof(buf)); + dsi_display_read_serial_number(dsi_display, panel, buf, len); + memcpy(panel->buf_id, buf, 32); + + panel_year = 2011 + ((buf[panel->panel_year_index-1] >> 4) & 0x0f); + if (panel_year == 2011){ + panel_year = 0; + } + panel_mon = buf[panel->panel_mon_index-1] & 0x0f; + if ((panel_mon > 12) || (panel_mon < 1)){ + pr_err("Panel Mon not corrected.\n"); + panel_mon = 0; + } + panel_day = buf[panel->panel_day_index-1] & 0x3f; + if ((panel_day > 31) || (panel_day < 1)){ + pr_err("Panel Day not corrected.\n"); + panel_day = 0; + } + panel_hour = buf[panel->panel_hour_index-1] & 0x3f; + if ((panel_hour > 23) || (panel_hour < 0)){ + pr_err("Panel Hour not corrected.\n"); + panel_hour = 0; + } + panel_min = buf[panel->panel_min_index-1] & 0x3f; + if ((panel_min > 59) || (panel_min < 0)){ + pr_err("Panel Min not corrected.\n"); + panel_min = 0; + } + panel_sec = buf[panel->panel_sec_index-1] & 0x3f; + if ((panel_sec > 59) || (panel_sec < 0)){ + pr_err("Panel sec not corrected.\n"); + panel_sec = 0; + } +/* + serial_number = ((uint64_t)panel_year << 56) + + ((uint64_t)panel_mon << 48) + + ((uint64_t)panel_day << 40) + + ((uint64_t)panel_hour << 32) + + ((uint64_t)panel_min << 24) + + ((uint64_t)panel_sec << 16) + + ((uint64_t)0 << 8) + + ((uint64_t)0); +*/ + serial_number = (uint64_t)panel_year * 10000000000 + (uint64_t)panel_mon * 100000000 + (uint64_t)panel_day * 1000000 + + (uint64_t)panel_hour * 10000 + (uint64_t)panel_min * 100 + (uint64_t)panel_sec; + + dsi_display_get_serial_number_id(serial_number); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_ALL_CLKS, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to enable DSI clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + } else{ + pr_err("This panel not support serial number.\n"); + } +error: + mutex_unlock(&dsi_display->display_lock); + pr_err("%s END\n", __func__); + return 0; +} + +uint64_t dsi_display_get_serial_number_id(uint64_t serial_number) +{ + + static uint64_t serial_number_at; + + pr_err("%s start\n",__func__); + if(0 == SERIAL_NUMBER_flag) + { + serial_number_at = serial_number; + if(0 == serial_number_at) + SERIAL_NUMBER_flag = 0; + else + SERIAL_NUMBER_flag = 1; + } + + return serial_number_at; +} + + +int dsi_display_set_hbm_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->hbm_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_hbm_mode(panel, level); + if (rc) + pr_err("unable to set hbm mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_get_hbm_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->hbm_mode; +} + +int dsi_display_set_hbm_brightness(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return -EINVAL; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + if ((strcmp(dsi_display->panel->name, "samsung dsc cmd mode oneplus dsi panel") != 0) && (strcmp(dsi_display->panel->name, "samsung s6e3fc2x01 cmd mode dsi panel") != 0)) { + dsi_display->panel->hbm_brightness = 0; + return 0; + } + + mutex_lock(&dsi_display->display_lock); + + panel->hbm_brightness = level; + + if (!dsi_panel_initialized(panel)) + goto error; + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_hbm_brightness(panel, level); + if (rc) + pr_err("Failed to set hbm brightness mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_get_hbm_brightness(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->hbm_brightness; +} + +extern int oneplus_force_screenfp; + +int dsi_display_set_fp_hbm_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->op_force_screenfp = level; + oneplus_force_screenfp=panel->op_force_screenfp; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_op_set_hbm_mode(panel, level); + if (rc) + pr_err("unable to set hbm mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + + +int dsi_display_get_fp_hbm_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->op_force_screenfp; +} + +int dsi_display_set_dci_p3_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->dci_p3_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_dci_p3_mode(panel, level); + if (rc) + pr_err("unable to set dci_p3 mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_get_dci_p3_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->dci_p3_mode; +} + +int dsi_display_set_night_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->night_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_night_mode(panel, level); + if (rc) + pr_err("unable to set night mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_get_night_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->night_mode; +} +int dsi_display_set_native_display_p3_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->naive_display_p3_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_native_display_p3_mode(panel, level); + if (rc) + pr_err("unable to set native display p3 mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_get_native_display_p3_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->naive_display_p3_mode; +} + +int dsi_display_set_native_display_wide_color_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->naive_display_wide_color_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_native_display_wide_color_mode(panel, level); + if (rc) + pr_err("unable to set native display p3 mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_set_native_loading_effect_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->naive_display_loading_effect_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_native_loading_effect_mode(panel, level); + if (rc) + pr_err("unable to set loading effect mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_set_customer_srgb_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->naive_display_customer_srgb_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_customer_srgb_mode(panel, level); + if (rc) + pr_err("unable to set customer srgb mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_set_customer_p3_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->naive_display_customer_p3_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_customer_p3_mode(panel, level); + if (rc) + pr_err("unable to set customer srgb mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} +int dsi_display_set_native_display_srgb_color_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + panel->naive_display_srgb_color_mode = level; + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + rc = dsi_panel_set_native_display_srgb_color_mode(panel, level); + if (rc) + pr_err("unable to set native display p3 mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + return rc; +} + +int dsi_display_get_native_display_srgb_color_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->naive_display_srgb_color_mode; +} + +int dsi_display_get_native_display_wide_color_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->naive_display_wide_color_mode; +} + +int dsi_display_get_native_display_loading_effect_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->naive_display_loading_effect_mode; +} +int dsi_display_get_customer_srgb_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->naive_display_customer_srgb_mode; +} +int dsi_display_get_customer_p3_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->naive_display_customer_p3_mode; +} + +int dsi_display_set_aod_mode(struct drm_connector *connector, int level) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + panel->aod_mode = level; + if (strcmp(dsi_display->panel->name, "samsung s6e3fc2x01 cmd mode dsi panel") == 0){ + printk(KERN_ERR"dsi_display_set_aod_mode\n"); + } + else if(strcmp(dsi_display->panel->name, "samsung dsc cmd mode oneplus dsi panel") == 0){ + printk(KERN_ERR"oneplus SDC 2K OLED dsi_display_set_aod_mode\n"); + } + else + { + dsi_display->panel->aod_mode=0; + return 0; + } + mutex_lock(&dsi_display->display_lock); + if (!dsi_panel_initialized(panel)) { + goto error; + } + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + rc = dsi_panel_set_aod_mode(panel, level); + if (rc) + pr_err("unable to set aod mode\n"); + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to disable DSI core clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } +error: + mutex_unlock(&dsi_display->display_lock); + + return rc; +} + +int dsi_display_get_aod_mode(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->aod_mode; +} + +int dsi_display_set_aod_disable(struct drm_connector *connector, int disable) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + mutex_lock(&dsi_display->display_lock); + panel->aod_disable = disable; + mutex_unlock(&dsi_display->display_lock); + + return rc; +} + +int dsi_display_get_aod_disable(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->aod_disable; +} +int dsi_display_read_panel_id(struct dsi_display *dsi_display, + struct dsi_panel *panel, char* buf, int len) +{ + int rc = 0; + u32 flags = 0; + struct dsi_cmd_desc *cmds; + struct dsi_display_mode *mode; + struct dsi_display_ctrl *m_ctrl; + int retry_times; + + m_ctrl = &dsi_display->ctrl[dsi_display->cmd_master_idx]; + + if (!panel || !m_ctrl) + return -EINVAL; + + rc = dsi_display_cmd_engine_enable(dsi_display); + if (rc) { + pr_err("cmd engine enable failed\n"); + return -EINVAL; + } + + dsi_panel_acquire_panel_lock(panel); + + mode = panel->cur_mode; + cmds = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID].cmds;; + if (cmds->last_command) { + cmds->msg.flags |= MIPI_DSI_MSG_LASTCOMMAND; + flags |= DSI_CTRL_CMD_LAST_COMMAND; + } + flags |= (DSI_CTRL_CMD_FETCH_MEMORY | DSI_CTRL_CMD_READ); + if (!m_ctrl->ctrl->vaddr) + goto error; + + cmds->msg.rx_buf = buf; + cmds->msg.rx_len = len; + retry_times = 0; + do { + rc = dsi_ctrl_cmd_transfer(m_ctrl->ctrl, &cmds->msg, flags); + retry_times++; + } while ((rc <= 0) && (retry_times < 3)); + + if (rc <= 0) + pr_err("rx cmd transfer failed rc=%d\n", rc); + + error: + dsi_panel_release_panel_lock(panel); + + dsi_display_cmd_engine_disable(dsi_display); + + return rc; +} + +char dsi_display_ascii_to_int(char ascii) +{ + char int_value; + + if ((ascii >= 48) && (ascii <= 57)){ + int_value = ascii - 48; + } + else if ((ascii >= 65) && (ascii <= 70)) { + int_value = ascii - 65 + 10; + } + else if ((ascii >= 97) && (ascii <= 102)) { + int_value = ascii - 97 + 10; + } + else { + int_value = 0; + pr_err("Bad para: %d , please enter the right value!", ascii); + } + + return int_value; +} + +int dsi_display_update_dsi_on_command(struct drm_connector *connector, const char *buf, size_t count) +{ + int i = 0; + int j = 0; + unsigned int length; + char *data; + struct dsi_panel_cmd_set *set; + + struct dsi_display *dsi_display = NULL; + struct dsi_panel *panel = NULL; + struct dsi_bridge *c_bridge; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return -EINVAL; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + + mutex_lock(&dsi_display->display_lock); + + length = count / 3; + data = kzalloc(length + 1, GFP_KERNEL); + + for (i = 0; buf[i+2] != 10; i = i+3) { + data[j] = dsi_display_ascii_to_int(buf[i]) << 4; + data[j] += dsi_display_ascii_to_int(buf[i+1]); + j++; + } + data[j] = dsi_display_ascii_to_int(buf[i]) << 4; + data[j] += dsi_display_ascii_to_int(buf[i+1]); + + set = &panel->cur_mode->priv_info->cmd_sets[DSI_CMD_SET_ON]; + + rc = dsi_panel_update_cmd_sets_sub(set, DSI_CMD_SET_ON, data, length); + if (rc) + pr_err("Failed to update_cmd_sets_sub, rc=%d\n", rc); + + mutex_unlock(&dsi_display->display_lock); + + return rc; +} + +static int dsi_display_get_mipi_dsi_msg(const struct mipi_dsi_msg *msg, char* buf) +{ + int len = 0; + size_t i; + char *tx_buf = (char*)msg->tx_buf; + /* Packet Info */ + len += snprintf(buf + len, PAGE_SIZE - len, "%02X ", msg->type); + /* Last bit */ + len += snprintf(buf + len, PAGE_SIZE - len, "%02X ", (msg->flags & MIPI_DSI_MSG_LASTCOMMAND) ? 1 : 0); + len += snprintf(buf + len, PAGE_SIZE - len, "%02X ", msg->channel); + len += snprintf(buf + len, PAGE_SIZE - len, "%02X ", (unsigned int)msg->flags); + /* Delay */ + len += snprintf(buf + len, PAGE_SIZE - len, "%02X ", msg->wait_ms); + len += snprintf(buf + len, PAGE_SIZE - len, "%02X %02X ", msg->tx_len >> 8, msg->tx_len & 0x00FF); + + /* Packet Payload */ + for (i = 0 ; i < msg->tx_len ; i++) { + len += snprintf(buf + len, PAGE_SIZE - len, "%02X ", tx_buf[i]); + } + len += snprintf(buf + len, PAGE_SIZE - len, "\n"); + + return len; +} + +int dsi_display_get_dsi_on_command(struct drm_connector *connector, char *buf) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + struct dsi_panel_cmd_set *cmd; + int i = 0; + int count = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + cmd = &dsi_display->panel->cur_mode->priv_info->cmd_sets[DSI_CMD_SET_ON]; + + for (i = 0; i < cmd->count; i++) { + count += dsi_display_get_mipi_dsi_msg(&cmd->cmds[i].msg, &buf[count]); + } + + return count; +} + +int dsi_display_panel_mismatch_check(struct drm_connector *connector) +{ + struct dsi_display_mode *mode; + struct dsi_panel *panel = NULL; + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + char buf[32]; + int panel_id; + u32 count; + int rc = 0; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return -EINVAL; + + panel = dsi_display->panel; + mutex_lock(&dsi_display->display_lock); + + if (!dsi_panel_initialized(panel) || !panel->cur_mode) { + panel->panel_mismatch = 0; + goto error; + } + + if (!panel->panel_mismatch_check) { + panel->panel_mismatch = 0; + pr_err("This hw not support panel mismatch check(dvt-mp)\n"); + goto error; + } + + mode = panel->cur_mode; + count = mode->priv_info->cmd_sets[DSI_CMD_SET_PANEL_ID].count; + if (count) { + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_ALL_CLKS, DSI_CLK_ON); + if (rc) { + pr_err("[%s] failed to enable DSI clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + + memset(buf, 0, sizeof(buf)); + dsi_display_read_panel_id(dsi_display, panel, buf, 1); + + panel_id = buf[0]; + panel->panel_mismatch = (panel_id == 0x03)? 1 : 0; + + rc = dsi_display_clk_ctrl(dsi_display->dsi_clk_handle, + DSI_ALL_CLKS, DSI_CLK_OFF); + if (rc) { + pr_err("[%s] failed to enable DSI clocks, rc=%d\n", + dsi_display->name, rc); + goto error; + } + } else{ + panel->panel_mismatch = 0; + pr_err("This panel not support panel mismatch check.\n"); + } +error: + mutex_unlock(&dsi_display->display_lock); + return 0; +} + +int dsi_display_panel_mismatch(struct drm_connector *connector) +{ + struct dsi_display *dsi_display = NULL; + struct dsi_bridge *c_bridge; + + if ((connector == NULL) || (connector->encoder == NULL) + || (connector->encoder->bridge == NULL)) + return 0; + + c_bridge = to_dsi_bridge(connector->encoder->bridge); + dsi_display = c_bridge->display; + + if ((dsi_display == NULL) || (dsi_display->panel == NULL)) + return 0; + + return dsi_display->panel->panel_mismatch; +} + +int dsi_display_unprepare(struct dsi_display *display) +{ + int rc = 0; + + if (!display) { + pr_err("Invalid params\n"); + return -EINVAL; + } + + SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY); + mutex_lock(&display->display_lock); + + rc = dsi_display_wake_up(display); + if (rc) + pr_err("[%s] display wake up failed, rc=%d\n", + display->name, rc); + + rc = dsi_panel_unprepare(display->panel); + if (rc) + pr_err("[%s] panel unprepare failed, rc=%d\n", + display->name, rc); + + rc = dsi_display_ctrl_host_disable(display); + if (rc) + pr_err("[%s] failed to disable DSI host, rc=%d\n", + display->name, rc); + + rc = dsi_display_clk_ctrl(display->dsi_clk_handle, + DSI_LINK_CLK, DSI_CLK_OFF); + if (rc) + pr_err("[%s] failed to disable Link clocks, rc=%d\n", + display->name, rc); + + rc = dsi_display_ctrl_deinit(display); + if (rc) + pr_err("[%s] failed to deinit controller, rc=%d\n", + display->name, rc); + + if (!display->panel->ulps_suspend_enabled) { + rc = dsi_display_phy_disable(display); + if (rc) + pr_err("[%s] failed to disable DSI PHY, rc=%d\n", + display->name, rc); + } + + rc = dsi_display_clk_ctrl(display->dsi_clk_handle, + DSI_CORE_CLK, DSI_CLK_OFF); + if (rc) + pr_err("[%s] failed to disable DSI clocks, rc=%d\n", + display->name, rc); + + /* destrory dsi isr set up */ + dsi_display_ctrl_isr_configure(display, false); + + rc = dsi_panel_post_unprepare(display->panel); + if (rc) + pr_err("[%s] panel post-unprepare failed, rc=%d\n", + display->name, rc); + + mutex_unlock(&display->display_lock); + + /* Free up DSI ERROR event callback */ + dsi_display_unregister_error_handler(display); + + SDE_EVT32(SDE_EVTLOG_FUNC_EXIT); + return rc; +} +//*mark.yao@PSW.MM.Display.LCD.Stability,2018/4/28,add for support aod,hbm,seed*/ +struct dsi_display *get_main_display(void) { + return primary_display; } +EXPORT_SYMBOL(get_main_display); static int __init dsi_display_register(void) { diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h index 807699604198fe94eeeecab3ea3af266b139a5b8..5bcd4d455391c9aff520c08d7beec56ebffea451 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, The Linux Foundation.All rights reserved. + * Copyright (c) 2015-2019, The Linux Foundation.All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -22,6 +22,7 @@ #include #include #include +#include #include "msm_drv.h" #include "dsi_defs.h" @@ -409,16 +410,18 @@ int dsi_display_validate_mode(struct dsi_display *display, u32 flags); /** - * dsi_display_validate_mode_vrr() - validates mode if variable refresh case + * dsi_display_validate_mode_change() - validates mode if variable refresh case + * or dynamic clk change case * @display: Handle to display. * @mode: Mode to be validated.. * * Return: 0 if error code. */ -int dsi_display_validate_mode_vrr(struct dsi_display *display, +int dsi_display_validate_mode_change(struct dsi_display *display, struct dsi_display_mode *cur_dsi_mode, struct dsi_display_mode *mode); +extern int msm_drm_notifier_call_chain(unsigned long val, void *v); /** * dsi_display_set_mode() - Set mode on the display. * @display: Handle to display. @@ -582,6 +585,9 @@ int dsi_display_set_tpg_state(struct dsi_display *display, bool enable); int dsi_display_clock_gate(struct dsi_display *display, bool enable); int dsi_dispaly_static_frame(struct dsi_display *display, bool enable); +uint64_t dsi_display_get_serial_number_id(uint64_t serial_number); + +int dsi_display_get_serial_number_AT(struct drm_connector *connector); /** * dsi_display_enable_event() - enable interrupt based connector event @@ -696,4 +702,11 @@ int dsi_display_cont_splash_config(void *display); int dsi_display_get_panel_vfp(void *display, int h_active, int v_active); +extern int connector_state_crtc_index; +extern int msm_drm_notifier_call_chain(unsigned long val, void *v); + +struct dsi_display *get_main_display(void); +extern char gamma_para[2][413]; +int dsi_display_gamma_read(struct dsi_display *dsi_display); + #endif /* _DSI_DISPLAY_H_ */ diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c index d81d57a56318cbfccb67a11e56ee6850a4be52ca..187fc7b08c5217f31497ae013063a260311ad3fa 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -80,6 +80,8 @@ static void convert_to_dsi_mode(const struct drm_display_mode *drm_mode, dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DMS; if (msm_is_mode_seamless_vrr(drm_mode)) dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_VRR; + if (msm_is_mode_seamless_dyn_clk(drm_mode)) + dsi_mode->dsi_mode_flags |= DSI_MODE_FLAG_DYN_CLK; dsi_mode->timing.h_sync_polarity = !!(drm_mode->flags & DRM_MODE_FLAG_PHSYNC); @@ -122,13 +124,18 @@ void dsi_convert_to_drm_mode(const struct dsi_display_mode *dsi_mode, drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DMS; if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_VRR) drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_VRR; + if (dsi_mode->dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK) + drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYN_CLK; if (dsi_mode->timing.h_sync_polarity) drm_mode->flags |= DRM_MODE_FLAG_PHSYNC; if (dsi_mode->timing.v_sync_polarity) drm_mode->flags |= DRM_MODE_FLAG_PVSYNC; - drm_mode_set_name(drm_mode); + /* set mode name */ + snprintf(drm_mode->name, DRM_DISPLAY_MODE_LEN, "%dx%dx%dx%d", + drm_mode->hdisplay, drm_mode->vdisplay, + drm_mode->vrefresh, drm_mode->clock); } static int dsi_bridge_attach(struct drm_bridge *bridge) @@ -173,7 +180,8 @@ static void dsi_bridge_pre_enable(struct drm_bridge *bridge) } if (c_bridge->dsi_mode.dsi_mode_flags & - (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR)) { + (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR | + DSI_MODE_FLAG_DYN_CLK)) { pr_debug("[%d] seamless pre-enable\n", c_bridge->id); return; } @@ -215,7 +223,8 @@ static void dsi_bridge_enable(struct drm_bridge *bridge) } if (c_bridge->dsi_mode.dsi_mode_flags & - (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR)) { + (DSI_MODE_FLAG_SEAMLESS | DSI_MODE_FLAG_VRR | + DSI_MODE_FLAG_DYN_CLK)) { pr_debug("[%d] seamless enable\n", c_bridge->id); return; } @@ -296,6 +305,12 @@ static void dsi_bridge_mode_set(struct drm_bridge *bridge, memset(&(c_bridge->dsi_mode), 0x0, sizeof(struct dsi_display_mode)); convert_to_dsi_mode(adjusted_mode, &(c_bridge->dsi_mode)); + + /* restore bit_clk_rate also for dynamic clk use cases */ + c_bridge->dsi_mode.timing.clk_rate_hz = + dsi_drm_find_bit_clk_rate(c_bridge->display, adjusted_mode); + + pr_debug("clk_rate: %llu\n", c_bridge->dsi_mode.timing.clk_rate_hz); } static bool dsi_bridge_mode_fixup(struct drm_bridge *bridge, @@ -364,17 +379,20 @@ static bool dsi_bridge_mode_fixup(struct drm_bridge *bridge, cur_dsi_mode.timing.dsc_enabled = dsi_mode.priv_info->dsc_enabled; cur_dsi_mode.timing.dsc = &dsi_mode.priv_info->dsc; - rc = dsi_display_validate_mode_vrr(c_bridge->display, + rc = dsi_display_validate_mode_change(c_bridge->display, &cur_dsi_mode, &dsi_mode); - if (rc) - pr_debug("[%s] vrr mode mismatch failure rc=%d\n", + if (rc) { + pr_err("[%s] seamless mode mismatch failure rc=%d\n", c_bridge->display->name, rc); +// return false; + } cur_mode = crtc_state->crtc->mode; /* No DMS/VRR when drm pipeline is changing */ if (!drm_mode_equal(&cur_mode, adjusted_mode) && (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_VRR)) && + (!(dsi_mode.dsi_mode_flags & DSI_MODE_FLAG_DYN_CLK)) && (!crtc_state->active_changed || display->is_cont_splash_enabled)) dsi_mode.dsi_mode_flags |= DSI_MODE_FLAG_DMS; @@ -386,6 +404,33 @@ static bool dsi_bridge_mode_fixup(struct drm_bridge *bridge, return true; } +u64 dsi_drm_find_bit_clk_rate(void *display, + const struct drm_display_mode *drm_mode) +{ + int i = 0, count = 0; + struct dsi_display *dsi_display = display; + struct dsi_display_mode *dsi_mode; + u64 bit_clk_rate = 0; + + if (!dsi_display || !drm_mode) + return 0; + + dsi_display_get_mode_count(dsi_display, &count); + + for (i = 0; i < count; i++) { + dsi_mode = &dsi_display->modes[i]; + if ((dsi_mode->timing.v_active == drm_mode->vdisplay) && + (dsi_mode->timing.h_active == drm_mode->hdisplay) && + (dsi_mode->pixel_clk_khz == drm_mode->clock) && + (dsi_mode->timing.refresh_rate == drm_mode->vrefresh)) { + bit_clk_rate = dsi_mode->timing.clk_rate_hz; + break; + } + } + + return bit_clk_rate; +} + int dsi_conn_get_mode_info(struct drm_connector *connector, const struct drm_display_mode *drm_mode, struct msm_mode_info *mode_info, @@ -410,7 +455,7 @@ int dsi_conn_get_mode_info(struct drm_connector *connector, mode_info->prefill_lines = dsi_mode.priv_info->panel_prefill_lines; mode_info->jitter_numer = dsi_mode.priv_info->panel_jitter_numer; mode_info->jitter_denom = dsi_mode.priv_info->panel_jitter_denom; - mode_info->clk_rate = dsi_mode.priv_info->clk_rate_hz; + mode_info->clk_rate = dsi_drm_find_bit_clk_rate(display, drm_mode); mode_info->mdp_transfer_time_us = dsi_mode.priv_info->mdp_transfer_time_us; @@ -516,6 +561,9 @@ int dsi_conn_set_info_blob(struct drm_connector *connector, panel->dfps_caps.max_refresh_rate); } + sde_kms_info_add_keystr(info, "dyn bitclk support", + panel->dyn_clk_caps.dyn_clk_support ? "true" : "false"); + switch (panel->phy_props.rotation) { case DSI_PANEL_ROTATE_NONE: sde_kms_info_add_keystr(info, "panel orientation", "none"); @@ -676,6 +724,9 @@ int dsi_connector_get_modes(struct drm_connector *connector, } m->width_mm = connector->display_info.width_mm; m->height_mm = connector->display_info.height_mm; + /* set the first mode in list as preferred */ + if (i == 0) + m->type |= DRM_MODE_TYPE_PREFERRED; drm_mode_probed_add(connector, m); } end: @@ -783,6 +834,9 @@ int dsi_conn_post_kickoff(struct drm_connector *connector) c_bridge->dsi_mode.dsi_mode_flags &= ~DSI_MODE_FLAG_VRR; } + /* ensure dynamic clk switch flag is reset */ + c_bridge->dsi_mode.dsi_mode_flags &= ~DSI_MODE_FLAG_DYN_CLK; + return 0; } diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.h b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.h index 7ec55485cfab2a2d3168de6da89faba53c9469a7..1af30e1d8090b3be96f4ebb7d930febee8ef605e 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -139,4 +139,6 @@ int dsi_conn_post_kickoff(struct drm_connector *connector); void dsi_convert_to_drm_mode(const struct dsi_display_mode *dsi_mode, struct drm_display_mode *drm_mode); +u64 dsi_drm_find_bit_clk_rate(void *display, + const struct drm_display_mode *drm_mode); #endif /* _DSI_DRM_H_ */ diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_hw.h b/drivers/gpu/drm/msm/dsi-staging/dsi_hw.h index ec44e4b3f48724ecfe5b192419857a9d839c2626..77c6694fd13e6194a36cc15ee296861b6c274e06 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_hw.h +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_hw.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -53,4 +53,14 @@ #define DSI_R64(dsi_hw, off) readq_relaxed((dsi_hw)->base + (off)) #define DSI_W64(dsi_hw, off, val) writeq_relaxed((val), (dsi_hw)->base + (off)) +#define PLL_CALC_DATA(addr0, addr1, data0, data1) \ + (((data1) << 24) | ((((addr1)/4) & 0xFF) << 16) | \ + ((data0) << 8) | (((addr0)/4) & 0xFF)) + +#define DSI_DYN_REF_REG_W(base, offset, addr0, addr1, data0, data1) \ + writel_relaxed(PLL_CALC_DATA(addr0, addr1, data0, data1), \ + (base) + (offset)) + +#define DSI_GEN_R32(base, offset) readl_relaxed(base + (offset)) +#define DSI_GEN_W32(base, offset, val) writel_relaxed((val), base + (offset)) #endif /* _DSI_HW_H_ */ diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c old mode 100644 new mode 100755 index cf73ffce17d8435e8344f60529ba686ca50ae338..b943a0391c1ab4d2119213ba7c44de5b979b1590 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_panel.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -18,11 +18,19 @@ #include #include #include