Merge "ARM: dts: msm: Update IPA nodes for sdxprairie"

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

&soc {

	qcom,lpm-levels {

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/clock/qcom,aop-qmp.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/regulator/qcom,rpmh-regulator.h>

#include <dt-bindings/msm/msm-bus-ids.h>

#include <dt-bindings/soc/qcom,tcs-mbox.h>

/ {

		qcom,mhi-event-ring-id-limits = <9 10>; /* start and end */

		qcom,modem-cfg-emb-pipe-flt;

		qcom,use-ipa-pm;

		qcom,arm-smmu;

		qcom,smmu-fast-map;

		qcom,wlan-ce-db-over-pcie;

		qcom,bandwidth-vote-for-ipa;

		qcom,msm-bus,name = "ipa";

		qcom,msm-bus,num-cases = <5>;

		qcom,msm-bus,num-paths = <4>;

		qcom,msm-bus,num-paths = <5>;

		qcom,msm-bus,vectors-KBps =

		/* No vote */

			<90 512 0 0>,

			<90 585 0 0>,

			<1 676 0 0>,

			<143 777 0 0>,

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_SNOC_MEM_NOC_GC 0 0>,

		<MSM_BUS_MASTER_SNOC_GC_MEM_NOC MSM_BUS_SLAVE_EBI_CH0 0 0>,

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 0 0>,

		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 0>,

		<MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 0>,

		/* SVS2 */

			<90 512 900000 1800000>,

			<90 585 300000 600000>,

			<1 676 90000 179000>, /*gcc_config_noc_clk_src */

			<143 777 0 120>, /* IB defined for IPA2X_clk in MHz*/

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_SNOC_MEM_NOC_GC 150000 600000>,

		<MSM_BUS_MASTER_SNOC_GC_MEM_NOC MSM_BUS_SLAVE_EBI_CH0 150000 1804000>,

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 75000 450000>,

		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 171400>,

		<MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 150>,

		/* SVS */

			<90 512 1530000 3060000>,

			<90 585 400000 800000>,

			<1 676 100000 199000>,

			<143 777 0 250>, /* IB defined for IPA2X_clk in MHz*/

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_SNOC_MEM_NOC_GC 625000 1000000>,

		<MSM_BUS_MASTER_SNOC_GC_MEM_NOC MSM_BUS_SLAVE_EBI_CH0 625000 3072000>,

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 312500 750000>,

		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 200000>,

		<MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 250>,

		/* NOMINAL */

			<90 512 2592000 5184000>,

			<90 585 800000 1600000>,

			<1 676 200000 399000>,

			<143 777 0 440>, /* IB defined for IPA2X_clk in MHz*/

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_SNOC_MEM_NOC_GC 1250000 2000000>,

		<MSM_BUS_MASTER_SNOC_GC_MEM_NOC MSM_BUS_SLAVE_EBI_CH0 1250000 6220800>,

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 625000 1500000>,

		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 400000>,

		<MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 500>,

		/* TURBO */

			<90 512 2592000 5184000>,

			<90 585 960000 1920000>,

			<1 676 266000 531000>,

			<143 777 0 500>; /* IB defined for IPA clk in MHz*/

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_SNOC_MEM_NOC_GC 2000000 2400000>,

		<MSM_BUS_MASTER_SNOC_GC_MEM_NOC MSM_BUS_SLAVE_EBI_CH0 2000000 7219200>,

		<MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 1000000 1920000>,

		<MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 533320>,

		<MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 600>;

		qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",

		"TURBO";

		qcom,throughput-threshold = <310 600 1000>;

		qcom,throughput-threshold = <600 2500 5000>;

		qcom,scaling-exceptions = <>;

		ipa_smmu_ap: ipa_smmu_ap {

			compatible = "qcom,ipa-smmu-ap-cb";

			iommus = <&apps_smmu 0x5E0 0x0>;

			qcom,iova-mapping = <0x20000000 0x40000000>;

			qcom,additional-mapping =

				/* modem tables in IMEM */

				<0x14688000 0x14688000 0x3000>;

			qcom,ipa-q6-smem-size = <16384>;

			dma-coherent;

		};

		ipa_smmu_wlan: ipa_smmu_wlan {

			compatible = "qcom,ipa-smmu-wlan-cb";

			iommus = <&apps_smmu 0x5E1 0x0>;

		};

		ipa_smmu_uc: ipa_smmu_uc {

			compatible = "qcom,ipa-smmu-uc-cb";

			iommus = <&apps_smmu 0x5E2 0x0>;

			qcom,iova-mapping = <0x40000000 0x20000000>;

		};

		/* smp2p information */

		qcom,smp2p_map_ipa_1_out {

			compatible = "qcom,smp2p-map-ipa-1-out";

			qcom,smem-states = <&smp2p_ipa_1_out 0>;

			qcom,smem-state-names = "ipa-smp2p-out";

		};

		qcom,smp2p_map_ipa_1_in {

			compatible = "qcom,smp2p-map-ipa-1-in";

			interrupts-extended = <&smp2p_ipa_1_in 0 0>;

			interrupt-names = "ipa-smp2p-in";

		};

	};

	tcsr_mutex_block: syscon@1f40000 {

			interrupt-controller;

			#interrupt-cells = <2>;

		};

		smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {

			qcom,entry-name = "ipa";

			#qcom,smem-state-cells = <1>;

		};

		/* ipa - inbound entry from mss */

		smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {

			qcom,entry-name = "ipa";

			interrupt-controller;

			#interrupt-cells = <2>;

		};

	};

	qcom_cedev: qcedev@1de0000 {