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Commit f0b77f2c authored by Steven J. Hill's avatar Steven J. Hill Committed by Ralf Baechle
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MIPS: Clean-up GIC and vectored interrupts. 



This change adds macros for routing of GIC interrupts for EIC and
non-EIC hardware modes. Also added Malta GIC macros having to do
with performance and timer interrupts.

Signed-off-by: default avatarSteven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3576/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent c6a4ebb9

arch/mips/include/asm/gic.h

+14 −1
Original line number Diff line number Diff line
@@ -206,7 +206,7 @@ 


#define GIC_VPE_EIC_SHADOW_SET_BASE	0x0100

#define GIC_VPE_EIC_SS(intr) \

	(GIC_EIC_SHADOW_SET_BASE + (4 * intr))

	(GIC_VPE_EIC_SHADOW_SET_BASE + (4 * intr))



#define GIC_VPE_EIC_VEC_BASE		0x0800

#define GIC_VPE_EIC_VEC(intr) \
@@ -330,6 +330,17 @@ struct gic_intr_map { 
#define GIC_FLAG_TRANSPARENT   0x02

};



/*

 * This is only used in EIC mode. This helps to figure out which

 * shared interrupts we need to process when we get a vector interrupt.

 */

#define GIC_MAX_SHARED_INTR  0x5

struct gic_shared_intr_map {

	unsigned int num_shared_intr;

	unsigned int intr_list[GIC_MAX_SHARED_INTR];

	unsigned int local_intr_mask;

};



extern void gic_init(unsigned long gic_base_addr,

	unsigned long gic_addrspace_size, struct gic_intr_map *intrmap,

	unsigned int intrmap_size, unsigned int irqbase);
@@ -338,5 +349,7 @@ extern unsigned int gic_get_int(void); 
extern void gic_send_ipi(unsigned int intr);

extern unsigned int plat_ipi_call_int_xlate(unsigned int);

extern unsigned int plat_ipi_resched_int_xlate(unsigned int);

extern void gic_bind_eic_interrupt(int irq, int set);

extern unsigned int gic_get_timer_pending(void);



#endif /* _ASM_GICREGS_H */

arch/mips/include/asm/mips-boards/maltaint.h

+10 −0
Original line number Diff line number Diff line
@@ -86,6 +86,16 @@ 
#define GIC_CPU_INT4		4 /* .			*/

#define GIC_CPU_INT5		5 /* Core Interrupt 5   */



/* MALTA GIC local interrupts */

#define GIC_INT_TMR             (GIC_CPU_INT5)

#define GIC_INT_PERFCTR         (GIC_CPU_INT5)



/* GIC constants */

/* Add 2 to convert non-eic hw int # to eic vector # */

#define GIC_CPU_TO_VEC_OFFSET   (2)

/* If we map an intr to pin X, GIC will actually generate vector X+1 */

#define GIC_PIN_TO_VEC_OFFSET   (1)



#define GIC_EXT_INTR(x)		x



/* External Interrupts used for IPI */