Merge "clk: qcom: update dsi 14nm PLL clock names" (f0ab3d73) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/clk/qcom/dispcc-sm6150.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -472,7 +472,7 @@ static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
		"disp_cc_mdss_byte0_clk_src",
		},
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT \| CLK_GET_RATE_NOCACHE,
		.flags = CLK_GET_RATE_NOCACHE,
		.ops = &clk_branch2_ops,
		},
		},

drivers/clk/qcom/mdss/mdss-dsi-pll-14nm.c

+6 −6

Original line number	Diff line number	Diff line
		@@ -78,7 +78,7 @@ static struct dsi_pll_vco_clk dsi0pll_vco_clk = {
		.pll_enable_seqs[0] = dsi_pll_enable_seq_14nm,
		.hw.init = &(struct clk_init_data){
		.name = "dsi0pll_vco_clk_14nm",
		.parent_names = (const char *[]){ "xo_board" },
		.parent_names = (const char *[]){ "bi_tcxo" },
		.num_parents = 1,
		.ops = &clk_ops_dsi_vco,
		},
		@@ -90,7 +90,7 @@ static struct dsi_pll_vco_clk dsi0pll_shadow_vco_clk = {
		.max_rate = 2600000000u,
		.hw.init = &(struct clk_init_data){
		.name = "dsi0pll_shadow_vco_clk_14nm",
		.parent_names = (const char *[]){ "xo_board" },
		.parent_names = (const char *[]){ "bi_tcxo" },
		.num_parents = 1,
		.ops = &clk_ops_shadow_dsi_vco,
		},
		@@ -104,7 +104,7 @@ static struct dsi_pll_vco_clk dsi1pll_vco_clk = {
		.pll_enable_seqs[0] = dsi_pll_enable_seq_14nm,
		.hw.init = &(struct clk_init_data){
		.name = "dsi1pll_vco_clk_14nm",
		.parent_names = (const char *[]){ "xo_board" },
		.parent_names = (const char *[]){ "bi_tcxo" },
		.num_parents = 1,
		.ops = &clk_ops_dsi_vco,
		},
		@@ -118,7 +118,7 @@ static struct dsi_pll_vco_clk dsi1pll_shadow_vco_clk = {
		.pll_enable_seqs[0] = dsi_pll_enable_seq_14nm,
		.hw.init = &(struct clk_init_data){
		.name = "dsi1pll_shadow_vco_clk_14nm",
		.parent_names = (const char *[]){ "xo_board" },
		.parent_names = (const char *[]){ "bi_tcxo" },
		.num_parents = 1,
		.ops = &clk_ops_shadow_dsi_vco,
		},
		@@ -319,7 +319,7 @@ static struct clk_regmap_mux dsi0pll_pixel_clk_mux = {

		.clkr = {
		.hw.init = &(struct clk_init_data){
		.name = "dsi0pll_pixel_clk_mux",
		.name = "dsi0_phy_pll_out_dsiclk",
		.parent_names =
		(const char *[]){ "dsi0pll_pixel_clk_src",
		"dsi0pll_shadow_pixel_clk_src"},
		@@ -409,7 +409,7 @@ static struct clk_regmap_mux dsi0pll_byte_clk_mux = {

		.clkr = {
		.hw.init = &(struct clk_init_data){
		.name = "dsi0pll_byte_clk_mux",
		.name = "dsi0_phy_pll_out_byteclk",
		.parent_names =
		(const char *[]){"dsi0pll_byte_clk_src",
		"dsi0pll_shadow_byte_clk_src"},

drivers/clk/qcom/mdss/mdss-pll.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -408,6 +408,7 @@ static const struct of_device_id mdss_pll_dt_match[] = {
		{.compatible = "qcom,mdss_dsi_pll_7nm"},
		{.compatible = "qcom,mdss_dp_pll_7nm"},
		{.compatible = "qcom,mdss_dsi_pll_28lpm"},
		{.compatible = "qcom,mdss_dsi_pll_14nm"},
		{}
		};