Commit f082e945 authored Jul 02, 2018 by Saranya Chidura Committed by Gerrit - the friendly Code Review server Jul 05, 2018

ARM: dts: msm: fix the byte-cntr interrupt for qcs405



ETR Byte Counter interrupt port is updated for
QCS405.

Change-Id: I0f3e4978736e542208c5bd57575e117e10b8178d
Signed-off-by: Saranya Chidura <schidura@codeaurora.org>

parent 709e9085

arch/arm64/boot/dts/qcom/qcs405-coresight.dtsi

+1 −1

Original line number	Diff line number	Diff line
		@@ -79,7 +79,7 @@
		<&clock_rpmcc RPM_QDSS_A_CLK>;
		clock-names = "apb_pclk", "core_a_clk";

		interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
		interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "byte-cntr-irq";

		port {