Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f067574c authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "clk: qcom: gcc: Remove the unused clocks for TRINKET"

parents 4aa5b5e1 fea2b48a

drivers/clk/qcom/gcc-trinket.c

+0 −19
Original line number Diff line number Diff line
@@ -2386,24 +2386,6 @@ static struct clk_branch gcc_camss_csiphy2_clk = { 
	},

};



static struct clk_branch gcc_camss_csiphy3_clk = {

	.halt_reg = 0x55024,

	.halt_check = BRANCH_HALT,

	.clkr = {

		.enable_reg = 0x55024,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_camss_csiphy3_clk",

			.parent_names = (const char *[]){

				"gcc_camss_csiphy_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gcc_camss_gp0_clk = {

	.halt_reg = 0x50018,

	.halt_check = BRANCH_HALT,
@@ -4188,7 +4170,6 @@ static struct clk_regmap *gcc_trinket_clocks[] = { 
	[GCC_CAMSS_CSIPHY0_CLK] = &gcc_camss_csiphy0_clk.clkr,

	[GCC_CAMSS_CSIPHY1_CLK] = &gcc_camss_csiphy1_clk.clkr,

	[GCC_CAMSS_CSIPHY2_CLK] = &gcc_camss_csiphy2_clk.clkr,

	[GCC_CAMSS_CSIPHY3_CLK] = &gcc_camss_csiphy3_clk.clkr,

	[GCC_CAMSS_CSIPHY_CLK_SRC] = &gcc_camss_csiphy_clk_src.clkr,

	[GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr,

	[GCC_CAMSS_GP0_CLK_SRC] = &gcc_camss_gp0_clk_src.clkr,

drivers/clk/qcom/gpucc-trinket.c

+0 −19
Original line number Diff line number Diff line
@@ -268,24 +268,6 @@ static struct clk_branch gpu_cc_cx_gfx3d_clk = { 
	},

};



static struct clk_branch gpu_cc_cx_gfx3d_slv_clk = {

	.halt_reg = 0x10a8,

	.halt_check = BRANCH_HALT_DELAY,

	.clkr = {

		.enable_reg = 0x10a8,

		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gpu_cc_cx_gfx3d_slv_clk",

			.parent_names = (const char *[]){

				"gpu_cc_gx_gfx3d_clk_src",

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},

};



static struct clk_branch gpu_cc_cx_gmu_clk = {

	.halt_reg = 0x1098,

	.halt_check = BRANCH_HALT,
@@ -405,7 +387,6 @@ static struct clk_regmap *gpu_cc_trinket_clocks[] = { 
	[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,

	[GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,

	[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,

	[GPU_CC_CX_GFX3D_SLV_CLK] = &gpu_cc_cx_gfx3d_slv_clk.clkr,

	[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,

	[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,

	[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,

include/dt-bindings/clock/qcom,gcc-trinket.h

+145 −146
Original line number Diff line number Diff line
@@ -80,152 +80,151 @@ 
#define GCC_CAMSS_CSIPHY0_CLK			63

#define GCC_CAMSS_CSIPHY1_CLK			64

#define GCC_CAMSS_CSIPHY2_CLK			65

#define GCC_CAMSS_CSIPHY3_CLK			66

#define GCC_CAMSS_CSIPHY_CLK_SRC		67

#define GCC_CAMSS_GP0_CLK			68

#define GCC_CAMSS_GP0_CLK_SRC			69

#define GCC_CAMSS_GP1_CLK			70

#define GCC_CAMSS_GP1_CLK_SRC			71

#define GCC_CAMSS_ISPIF_AHB_CLK			72

#define GCC_CAMSS_JPEG_AHB_CLK			73

#define GCC_CAMSS_JPEG_AXI_CLK			74

#define GCC_CAMSS_JPEG_CLK			75

#define GCC_CAMSS_JPEG_CLK_SRC			76

#define GCC_CAMSS_MCLK0_CLK			77

#define GCC_CAMSS_MCLK0_CLK_SRC			78

#define GCC_CAMSS_MCLK1_CLK			79

#define GCC_CAMSS_MCLK1_CLK_SRC			80

#define GCC_CAMSS_MCLK2_CLK			81

#define GCC_CAMSS_MCLK2_CLK_SRC			82

#define GCC_CAMSS_MCLK3_CLK			83

#define GCC_CAMSS_MCLK3_CLK_SRC			84

#define GCC_CAMSS_MICRO_AHB_CLK			85

#define GCC_CAMSS_THROTTLE_NRT_AXI_CLK		86

#define GCC_CAMSS_THROTTLE_RT_AXI_CLK		87

#define GCC_CAMSS_TOP_AHB_CLK			88

#define GCC_CAMSS_VFE0_AHB_CLK			89

#define GCC_CAMSS_VFE0_CLK			90

#define GCC_CAMSS_VFE0_CLK_SRC			91

#define GCC_CAMSS_VFE0_STREAM_CLK		92

#define GCC_CAMSS_VFE1_AHB_CLK			93

#define GCC_CAMSS_VFE1_CLK			94

#define GCC_CAMSS_VFE1_CLK_SRC			95

#define GCC_CAMSS_VFE1_STREAM_CLK		96

#define GCC_CAMSS_VFE_TSCTR_CLK			97

#define GCC_CAMSS_VFE_VBIF_AHB_CLK		98

#define GCC_CAMSS_VFE_VBIF_AXI_CLK		99

#define GCC_CE1_AHB_CLK				100

#define GCC_CE1_AXI_CLK				101

#define GCC_CE1_CLK				102

#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK		103

#define GCC_CPUSS_GNOC_CLK			104

#define GCC_DISP_AHB_CLK			105

#define GCC_DISP_GPLL0_DIV_CLK_SRC		106

#define GCC_DISP_HF_AXI_CLK			107

#define GCC_DISP_THROTTLE_CORE_CLK		108

#define GCC_DISP_XO_CLK				109

#define GCC_GP1_CLK				110

#define GCC_GP1_CLK_SRC				111

#define GCC_GP2_CLK				112

#define GCC_GP2_CLK_SRC				113

#define GCC_GP3_CLK				114

#define GCC_GP3_CLK_SRC				115

#define GCC_GPU_CFG_AHB_CLK			116

#define GCC_GPU_GPLL0_CLK_SRC			117

#define GCC_GPU_GPLL0_DIV_CLK_SRC		118

#define GCC_GPU_MEMNOC_GFX_CLK			119

#define GCC_GPU_SNOC_DVM_GFX_CLK		120

#define GCC_GPU_THROTTLE_CORE_CLK		121

#define GCC_GPU_THROTTLE_XO_CLK			122

#define GCC_MSS_VS_CLK				123

#define GCC_PDM2_CLK				124

#define GCC_PDM2_CLK_SRC			125

#define GCC_PDM_AHB_CLK				126

#define GCC_PDM_XO4_CLK				127

#define GCC_PRNG_AHB_CLK			128

#define GCC_QMIP_CAMERA_NRT_AHB_CLK		129

#define GCC_QMIP_CAMERA_RT_AHB_CLK		130

#define GCC_QMIP_DISP_AHB_CLK			131

#define GCC_QMIP_GPU_CFG_AHB_CLK		132

#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK		133

#define GCC_QUPV3_WRAP0_CORE_2X_CLK		134

#define GCC_QUPV3_WRAP0_CORE_CLK		135

#define GCC_QUPV3_WRAP0_S0_CLK			136

#define GCC_QUPV3_WRAP0_S0_CLK_SRC		137

#define GCC_QUPV3_WRAP0_S1_CLK			138

#define GCC_QUPV3_WRAP0_S1_CLK_SRC		139

#define GCC_QUPV3_WRAP0_S2_CLK			140

#define GCC_QUPV3_WRAP0_S2_CLK_SRC		141

#define GCC_QUPV3_WRAP0_S3_CLK			142

#define GCC_QUPV3_WRAP0_S3_CLK_SRC		143

#define GCC_QUPV3_WRAP0_S4_CLK			144

#define GCC_QUPV3_WRAP0_S4_CLK_SRC		145

#define GCC_QUPV3_WRAP0_S5_CLK			146

#define GCC_QUPV3_WRAP0_S5_CLK_SRC		147

#define GCC_QUPV3_WRAP1_CORE_2X_CLK		148

#define GCC_QUPV3_WRAP1_CORE_CLK		149

#define GCC_QUPV3_WRAP1_S0_CLK			150

#define GCC_QUPV3_WRAP1_S0_CLK_SRC		151

#define GCC_QUPV3_WRAP1_S1_CLK			152

#define GCC_QUPV3_WRAP1_S1_CLK_SRC		153

#define GCC_QUPV3_WRAP1_S2_CLK			154

#define GCC_QUPV3_WRAP1_S2_CLK_SRC		155

#define GCC_QUPV3_WRAP1_S3_CLK			156

#define GCC_QUPV3_WRAP1_S3_CLK_SRC		157

#define GCC_QUPV3_WRAP1_S4_CLK			158

#define GCC_QUPV3_WRAP1_S4_CLK_SRC		159

#define GCC_QUPV3_WRAP1_S5_CLK			160

#define GCC_QUPV3_WRAP1_S5_CLK_SRC		161

#define GCC_QUPV3_WRAP_0_M_AHB_CLK		162

#define GCC_QUPV3_WRAP_0_S_AHB_CLK		163

#define GCC_QUPV3_WRAP_1_M_AHB_CLK		164

#define GCC_QUPV3_WRAP_1_S_AHB_CLK		165

#define GCC_SDCC1_AHB_CLK			166

#define GCC_SDCC1_APPS_CLK			167

#define GCC_SDCC1_APPS_CLK_SRC			168

#define GCC_SDCC1_ICE_CORE_CLK			169

#define GCC_SDCC1_ICE_CORE_CLK_SRC		170

#define GCC_SDCC2_AHB_CLK			171

#define GCC_SDCC2_APPS_CLK			172

#define GCC_SDCC2_APPS_CLK_SRC			173

#define GCC_SYS_NOC_CPUSS_AHB_CLK		174

#define GCC_SYS_NOC_UFS_PHY_AXI_CLK		175

#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK		176

#define GCC_UFS_PHY_AHB_CLK			177

#define GCC_UFS_PHY_AXI_CLK			178

#define GCC_UFS_PHY_AXI_CLK_SRC			179

#define GCC_UFS_PHY_ICE_CORE_CLK		180

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC		181

#define GCC_UFS_PHY_PHY_AUX_CLK			182

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC		183

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK		184

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK		185

#define GCC_UFS_PHY_UNIPRO_CORE_CLK		186

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC		187

#define GCC_USB30_PRIM_MASTER_CLK		188

#define GCC_USB30_PRIM_MASTER_CLK_SRC		189

#define GCC_USB30_PRIM_MOCK_UTMI_CLK		190

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC	191

#define GCC_USB30_PRIM_SLEEP_CLK		192

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC		193

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK		194

#define GCC_USB3_PRIM_PHY_PIPE_CLK		195

#define GCC_VDDA_VS_CLK				196

#define GCC_VDDCX_VS_CLK			197

#define GCC_VDDMX_VS_CLK			198

#define GCC_VIDEO_AHB_CLK			199

#define GCC_VIDEO_AXI0_CLK			200

#define GCC_VIDEO_THROTTLE_CORE_CLK		201

#define GCC_VIDEO_XO_CLK			202

#define GCC_VS_CTRL_AHB_CLK			203

#define GCC_VS_CTRL_CLK				204

#define GCC_VS_CTRL_CLK_SRC			205

#define GCC_VSENSOR_CLK_SRC			206

#define GCC_WCSS_VS_CLK				207

#define GCC_USB3_PRIM_CLKREF_CLK		208

#define GCC_SYS_NOC_COMPUTE_SF_AXI_CLK		209

#define GCC_BIMC_GPU_AXI_CLK			210

#define GCC_UFS_MEM_CLKREF_CLK			211

#define GCC_CAMSS_CSIPHY_CLK_SRC		66

#define GCC_CAMSS_GP0_CLK			67

#define GCC_CAMSS_GP0_CLK_SRC			68

#define GCC_CAMSS_GP1_CLK			69

#define GCC_CAMSS_GP1_CLK_SRC			70

#define GCC_CAMSS_ISPIF_AHB_CLK			71

#define GCC_CAMSS_JPEG_AHB_CLK			72

#define GCC_CAMSS_JPEG_AXI_CLK			73

#define GCC_CAMSS_JPEG_CLK			74

#define GCC_CAMSS_JPEG_CLK_SRC			75

#define GCC_CAMSS_MCLK0_CLK			76

#define GCC_CAMSS_MCLK0_CLK_SRC			77

#define GCC_CAMSS_MCLK1_CLK			78

#define GCC_CAMSS_MCLK1_CLK_SRC			79

#define GCC_CAMSS_MCLK2_CLK			80

#define GCC_CAMSS_MCLK2_CLK_SRC			81

#define GCC_CAMSS_MCLK3_CLK			82

#define GCC_CAMSS_MCLK3_CLK_SRC			83

#define GCC_CAMSS_MICRO_AHB_CLK			84

#define GCC_CAMSS_THROTTLE_NRT_AXI_CLK		85

#define GCC_CAMSS_THROTTLE_RT_AXI_CLK		86

#define GCC_CAMSS_TOP_AHB_CLK			87

#define GCC_CAMSS_VFE0_AHB_CLK			88

#define GCC_CAMSS_VFE0_CLK			89

#define GCC_CAMSS_VFE0_CLK_SRC			90

#define GCC_CAMSS_VFE0_STREAM_CLK		91

#define GCC_CAMSS_VFE1_AHB_CLK			92

#define GCC_CAMSS_VFE1_CLK			93

#define GCC_CAMSS_VFE1_CLK_SRC			94

#define GCC_CAMSS_VFE1_STREAM_CLK		95

#define GCC_CAMSS_VFE_TSCTR_CLK			96

#define GCC_CAMSS_VFE_VBIF_AHB_CLK		97

#define GCC_CAMSS_VFE_VBIF_AXI_CLK		98

#define GCC_CE1_AHB_CLK				99

#define GCC_CE1_AXI_CLK				100

#define GCC_CE1_CLK				101

#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK		102

#define GCC_CPUSS_GNOC_CLK			103

#define GCC_DISP_AHB_CLK			104

#define GCC_DISP_GPLL0_DIV_CLK_SRC		105

#define GCC_DISP_HF_AXI_CLK			106

#define GCC_DISP_THROTTLE_CORE_CLK		107

#define GCC_DISP_XO_CLK				108

#define GCC_GP1_CLK				109

#define GCC_GP1_CLK_SRC				110

#define GCC_GP2_CLK				111

#define GCC_GP2_CLK_SRC				112

#define GCC_GP3_CLK				113

#define GCC_GP3_CLK_SRC				114

#define GCC_GPU_CFG_AHB_CLK			115

#define GCC_GPU_GPLL0_CLK_SRC			116

#define GCC_GPU_GPLL0_DIV_CLK_SRC		117

#define GCC_GPU_MEMNOC_GFX_CLK			118

#define GCC_GPU_SNOC_DVM_GFX_CLK		119

#define GCC_GPU_THROTTLE_CORE_CLK		120

#define GCC_GPU_THROTTLE_XO_CLK			121

#define GCC_MSS_VS_CLK				122

#define GCC_PDM2_CLK				123

#define GCC_PDM2_CLK_SRC			124

#define GCC_PDM_AHB_CLK				125

#define GCC_PDM_XO4_CLK				126

#define GCC_PRNG_AHB_CLK			127

#define GCC_QMIP_CAMERA_NRT_AHB_CLK		128

#define GCC_QMIP_CAMERA_RT_AHB_CLK		129

#define GCC_QMIP_DISP_AHB_CLK			130

#define GCC_QMIP_GPU_CFG_AHB_CLK		131

#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK		132

#define GCC_QUPV3_WRAP0_CORE_2X_CLK		133

#define GCC_QUPV3_WRAP0_CORE_CLK		134

#define GCC_QUPV3_WRAP0_S0_CLK			135

#define GCC_QUPV3_WRAP0_S0_CLK_SRC		136

#define GCC_QUPV3_WRAP0_S1_CLK			137

#define GCC_QUPV3_WRAP0_S1_CLK_SRC		138

#define GCC_QUPV3_WRAP0_S2_CLK			139

#define GCC_QUPV3_WRAP0_S2_CLK_SRC		140

#define GCC_QUPV3_WRAP0_S3_CLK			141

#define GCC_QUPV3_WRAP0_S3_CLK_SRC		142

#define GCC_QUPV3_WRAP0_S4_CLK			143

#define GCC_QUPV3_WRAP0_S4_CLK_SRC		144

#define GCC_QUPV3_WRAP0_S5_CLK			145

#define GCC_QUPV3_WRAP0_S5_CLK_SRC		146

#define GCC_QUPV3_WRAP1_CORE_2X_CLK		147

#define GCC_QUPV3_WRAP1_CORE_CLK		148

#define GCC_QUPV3_WRAP1_S0_CLK			149

#define GCC_QUPV3_WRAP1_S0_CLK_SRC		150

#define GCC_QUPV3_WRAP1_S1_CLK			151

#define GCC_QUPV3_WRAP1_S1_CLK_SRC		152

#define GCC_QUPV3_WRAP1_S2_CLK			153

#define GCC_QUPV3_WRAP1_S2_CLK_SRC		154

#define GCC_QUPV3_WRAP1_S3_CLK			155

#define GCC_QUPV3_WRAP1_S3_CLK_SRC		156

#define GCC_QUPV3_WRAP1_S4_CLK			157

#define GCC_QUPV3_WRAP1_S4_CLK_SRC		158

#define GCC_QUPV3_WRAP1_S5_CLK			159

#define GCC_QUPV3_WRAP1_S5_CLK_SRC		160

#define GCC_QUPV3_WRAP_0_M_AHB_CLK		161

#define GCC_QUPV3_WRAP_0_S_AHB_CLK		162

#define GCC_QUPV3_WRAP_1_M_AHB_CLK		163

#define GCC_QUPV3_WRAP_1_S_AHB_CLK		164

#define GCC_SDCC1_AHB_CLK			165

#define GCC_SDCC1_APPS_CLK			166

#define GCC_SDCC1_APPS_CLK_SRC			167

#define GCC_SDCC1_ICE_CORE_CLK			168

#define GCC_SDCC1_ICE_CORE_CLK_SRC		169

#define GCC_SDCC2_AHB_CLK			170

#define GCC_SDCC2_APPS_CLK			171

#define GCC_SDCC2_APPS_CLK_SRC			172

#define GCC_SYS_NOC_CPUSS_AHB_CLK		173

#define GCC_SYS_NOC_UFS_PHY_AXI_CLK		174

#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK		175

#define GCC_UFS_PHY_AHB_CLK			176

#define GCC_UFS_PHY_AXI_CLK			177

#define GCC_UFS_PHY_AXI_CLK_SRC			178

#define GCC_UFS_PHY_ICE_CORE_CLK		179

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC		180

#define GCC_UFS_PHY_PHY_AUX_CLK			181

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC		182

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK		183

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK		184

#define GCC_UFS_PHY_UNIPRO_CORE_CLK		185

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC		186

#define GCC_USB30_PRIM_MASTER_CLK		187

#define GCC_USB30_PRIM_MASTER_CLK_SRC		188

#define GCC_USB30_PRIM_MOCK_UTMI_CLK		189

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC	190

#define GCC_USB30_PRIM_SLEEP_CLK		191

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC		192

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK		193

#define GCC_USB3_PRIM_PHY_PIPE_CLK		194

#define GCC_VDDA_VS_CLK				195

#define GCC_VDDCX_VS_CLK			196

#define GCC_VDDMX_VS_CLK			197

#define GCC_VIDEO_AHB_CLK			198

#define GCC_VIDEO_AXI0_CLK			119

#define GCC_VIDEO_THROTTLE_CORE_CLK		200

#define GCC_VIDEO_XO_CLK			201

#define GCC_VS_CTRL_AHB_CLK			202

#define GCC_VS_CTRL_CLK				203

#define GCC_VS_CTRL_CLK_SRC			204

#define GCC_VSENSOR_CLK_SRC			205

#define GCC_WCSS_VS_CLK				206

#define GCC_USB3_PRIM_CLKREF_CLK		207

#define GCC_SYS_NOC_COMPUTE_SF_AXI_CLK		208

#define GCC_BIMC_GPU_AXI_CLK			209

#define GCC_UFS_MEM_CLKREF_CLK			210



/* GCC Resets */

#define GCC_QUSB2PHY_PRIM_BCR			0

include/dt-bindings/clock/qcom,gpucc-trinket.h

+10 −11
Original line number Diff line number Diff line
@@ -20,16 +20,15 @@ 
#define GPU_CC_CRC_AHB_CLK			2

#define GPU_CC_CX_APB_CLK			3

#define GPU_CC_CX_GFX3D_CLK			4

#define GPU_CC_CX_GFX3D_SLV_CLK			5

#define GPU_CC_CX_GMU_CLK			6

#define GPU_CC_CX_SNOC_DVM_CLK			7

#define GPU_CC_CXO_AON_CLK			8

#define GPU_CC_CXO_CLK			9

#define GPU_CC_GMU_CLK_SRC			10

#define GPU_CC_SLEEP_CLK			11

#define GPU_CC_GX_GFX3D_CLK			12

#define GPU_CC_GX_GFX3D_CLK_SRC			13

#define GPU_CC_AHB_CLK			14

#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK		15

#define GPU_CC_CX_GMU_CLK			5

#define GPU_CC_CX_SNOC_DVM_CLK			6

#define GPU_CC_CXO_AON_CLK			7

#define GPU_CC_CXO_CLK			8

#define GPU_CC_GMU_CLK_SRC			9

#define GPU_CC_SLEEP_CLK			10

#define GPU_CC_GX_GFX3D_CLK			11

#define GPU_CC_GX_GFX3D_CLK_SRC			12

#define GPU_CC_AHB_CLK			13

#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK		14



#endif