Loading arch/arm64/boot/dts/qcom/sm8150-mhi.dtsi +10 −0 Original line number Diff line number Diff line Loading @@ -13,6 +13,8 @@ &pcie_rc1 { reg = <0 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; mhi_0: qcom,mhi@0 { reg = <0 0 0 0 0 >; Loading Loading @@ -399,6 +401,9 @@ }; mhi_events { #address-cells = <1>; #size-cells = <0>; mhi_event@0 { mhi,num-elements = <32>; mhi,intmod = <1>; Loading Loading @@ -547,6 +552,8 @@ &pcie_rc0 { reg = <0 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; mhi_1: qcom,mhi@0 { reg = <0 0 0 0 0 >; Loading Loading @@ -940,6 +947,9 @@ }; mhi_events { #address-cells = <1>; #size-cells = <0>; mhi_event@0 { mhi,num-elements = <32>; mhi,intmod = <1>; Loading Loading
arch/arm64/boot/dts/qcom/sm8150-mhi.dtsi +10 −0 Original line number Diff line number Diff line Loading @@ -13,6 +13,8 @@ &pcie_rc1 { reg = <0 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; mhi_0: qcom,mhi@0 { reg = <0 0 0 0 0 >; Loading Loading @@ -399,6 +401,9 @@ }; mhi_events { #address-cells = <1>; #size-cells = <0>; mhi_event@0 { mhi,num-elements = <32>; mhi,intmod = <1>; Loading Loading @@ -547,6 +552,8 @@ &pcie_rc0 { reg = <0 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; mhi_1: qcom,mhi@0 { reg = <0 0 0 0 0 >; Loading Loading @@ -940,6 +947,9 @@ }; mhi_events { #address-cells = <1>; #size-cells = <0>; mhi_event@0 { mhi,num-elements = <32>; mhi,intmod = <1>; Loading