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Commit ef8f8732 authored by Sankeerth Billakanti's avatar Sankeerth Billakanti
Browse files

clk: qcom: mdss: add support for 14nm DP PLL for sm6150 target 



Add files to program the DP VCO and dividers for sm6150
target. Add support for the 14nm dp pll in the clock driver.

Change-Id: Ib6f71f3a35645f6e1cd689b56615c1d78a3edbf5
Signed-off-by: default avatarSankeerth Billakanti <sbillaka@codeaurora.org>
parent 8c63eb9b

Documentation/devicetree/bindings/fb/mdss-pll.txt

+2 −1
Original line number Diff line number Diff line
@@ -18,7 +18,8 @@ Required properties: 
                        "qcom,mdss_dsi_pll_10nm",  "qcom,mdss_dp_pll_8998",

                        "qcom,mdss_hdmi_pll_8998", "qcom,mdss_dp_pll_10nm",

                        "qcom,mdss_dsi_pll_7nm",   "qcom,mdss_dp_pll_7nm",

			"qcom,mdss_dsi_pll_28lpm", "qcom,mdss_dsi_pll_14nm"

			"qcom,mdss_dsi_pll_28lpm", "qcom,mdss_dsi_pll_14nm",

			"qcom,mdss_dp_pll_14nm"

- cell-index:		Specifies the controller used

- reg:			offset and length of the register set for the device.

- reg-names :		names to refer to register sets related to this device

drivers/clk/qcom/mdss/Makefile

+1 −0
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@@ -10,3 +10,4 @@ obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dsi-pll-28lpm.o 
obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dsi-pll-28nm-util.o

obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dsi-pll-14nm.o

obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dsi-pll-14nm-util.o

obj-$(CONFIG_QCOM_MDSS_PLL) += mdss-dp-pll-14nm.o

drivers/clk/qcom/mdss/mdss-dp-pll-14nm.c

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File added.

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drivers/clk/qcom/mdss/mdss-dp-pll-14nm.h

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/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 */



#ifndef __MDSS_DP_PLL_14NM_H

#define __MDSS_DP_PLL_14NM_H



#define DP_PHY_REVISION_ID0			0x0000

#define DP_PHY_REVISION_ID1			0x0004

#define DP_PHY_REVISION_ID2			0x0008

#define DP_PHY_REVISION_ID3			0x000C



#define DP_PHY_CFG				0x0010

#define DP_PHY_CFG_1				0x0014

#define DP_PHY_PD_CTL				0x0018

#define DP_PHY_MODE				0x001C



#define DP_PHY_AUX_CFG0				0x0020

#define DP_PHY_AUX_CFG1				0x0024

#define DP_PHY_AUX_CFG2				0x0028

#define DP_PHY_AUX_CFG3				0x002C

#define DP_PHY_AUX_CFG4				0x0030

#define DP_PHY_AUX_CFG5				0x0034

#define DP_PHY_AUX_CFG6				0x0038

#define DP_PHY_AUX_CFG7				0x003C

#define DP_PHY_AUX_CFG8				0x0040

#define DP_PHY_AUX_CFG9				0x0044

#define DP_PHY_AUX_INTERRUPT_MASK		0x0048

#define DP_PHY_AUX_INTERRUPT_CLEAR		0x004C

#define DP_PHY_AUX_BIST_CFG			0x0050



#define DP_PHY_VCO_DIV				0x0068

#define DP_PHY_TX0_TX1_LANE_CTL			0x006C



#define DP_PHY_TX2_TX3_LANE_CTL			0x0088

#define DP_PHY_SPARE0				0x00AC

#define DP_PHY_STATUS				0x00C0



/* Tx registers */

#define QSERDES_TX0_OFFSET			0x0400

#define QSERDES_TX1_OFFSET			0x0800



#define TXn_BIST_MODE_LANENO			0x0000

#define TXn_CLKBUF_ENABLE			0x0008

#define TXn_TX_EMP_POST1_LVL			0x000C



#define TXn_TX_DRV_LVL				0x001C



#define TXn_RESET_TSYNC_EN			0x0024

#define TXn_PRE_STALL_LDO_BOOST_EN		0x0028

#define TXn_TX_BAND				0x002C

#define TXn_SLEW_CNTL				0x0030

#define TXn_INTERFACE_SELECT			0x0034



#define TXn_RES_CODE_LANE_TX			0x003C

#define TXn_RES_CODE_LANE_RX			0x0040

#define TXn_RES_CODE_LANE_OFFSET_TX		0x0044

#define TXn_RES_CODE_LANE_OFFSET_RX		0x0048



#define TXn_DEBUG_BUS_SEL			0x0058

#define TXn_TRANSCEIVER_BIAS_EN			0x005C

#define TXn_HIGHZ_DRVR_EN			0x0060

#define TXn_TX_POL_INV				0x0064

#define TXn_PARRATE_REC_DETECT_IDLE_EN		0x0068



#define TXn_LANE_MODE_1				0x008C



#define TXn_TRAN_DRVR_EMP_EN			0x00C0

#define TXn_TX_INTERFACE_MODE			0x00C4



#define TXn_VMODE_CTRL1				0x00F0





/* PLL register offset */

#define QSERDES_COM_ATB_SEL1			0x0000

#define QSERDES_COM_ATB_SEL2			0x0004

#define QSERDES_COM_FREQ_UPDATE			0x0008

#define QSERDES_COM_BG_TIMER			0x000C

#define QSERDES_COM_SSC_EN_CENTER		0x0010

#define QSERDES_COM_SSC_ADJ_PER1		0x0014

#define QSERDES_COM_SSC_ADJ_PER2		0x0018

#define QSERDES_COM_SSC_PER1			0x001C

#define QSERDES_COM_SSC_PER2			0x0020

#define QSERDES_COM_SSC_STEP_SIZE1		0x0024

#define QSERDES_COM_SSC_STEP_SIZE2		0x0028

#define QSERDES_COM_POST_DIV			0x002C

#define QSERDES_COM_POST_DIV_MUX		0x0030

#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN		0x0034

#define QSERDES_COM_CLK_ENABLE1			0x0038

#define QSERDES_COM_SYS_CLK_CTRL		0x003C

#define QSERDES_COM_SYSCLK_BUF_ENABLE		0x0040

#define QSERDES_COM_PLL_EN			0x0044

#define QSERDES_COM_PLL_IVCO			0x0048

#define QSERDES_COM_LOCK_CMP1_MODE0		0x004C

#define QSERDES_COM_LOCK_CMP2_MODE0		0x0050

#define QSERDES_COM_LOCK_CMP3_MODE0		0x0054



#define QSERDES_COM_CP_CTRL_MODE0		0x0078

#define QSERDES_COM_CP_CTRL_MODE1		0x007C

#define QSERDES_COM_PLL_RCTRL_MODE0		0x0084

#define QSERDES_COM_PLL_CCTRL_MODE0		0x0090

#define QSERDES_COM_PLL_CNTRL			0x009C



#define QSERDES_COM_SYSCLK_EN_SEL		0x00AC

#define QSERDES_COM_CML_SYSCLK_SEL		0x00B0

#define QSERDES_COM_RESETSM_CNTRL		0x00B4

#define QSERDES_COM_RESETSM_CNTRL2		0x00B8

#define QSERDES_COM_LOCK_CMP_EN			0x00C8

#define QSERDES_COM_LOCK_CMP_CFG		0x00CC





#define QSERDES_COM_DEC_START_MODE0		0x00D0

#define QSERDES_COM_DEC_START_MODE1		0x00D4

#define QSERDES_COM_DIV_FRAC_START1_MODE0	0x00DC

#define QSERDES_COM_DIV_FRAC_START2_MODE0	0x00E0

#define QSERDES_COM_DIV_FRAC_START3_MODE0	0x00E4



#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0	0x0108

#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0	0x010C

#define QSERDES_COM_VCO_TUNE_CTRL		0x0124

#define QSERDES_COM_VCO_TUNE_MAP		0x0128

#define QSERDES_COM_VCO_TUNE1_MODE0		0x012C

#define QSERDES_COM_VCO_TUNE2_MODE0		0x0130



#define QSERDES_COM_CMN_STATUS			0x015C

#define QSERDES_COM_RESET_SM_STATUS		0x0160



#define QSERDES_COM_BG_CTRL			0x0170

#define QSERDES_COM_CLK_SELECT			0x0174

#define QSERDES_COM_HSCLK_SEL			0x0178

#define QSERDES_COM_CORECLK_DIV			0x0184

#define QSERDES_COM_SW_RESET			0x0188

#define QSERDES_COM_CORE_CLK_EN			0x018C

#define QSERDES_COM_C_READY_STATUS		0x0190

#define QSERDES_COM_CMN_CONFIG			0x0194

#define QSERDES_COM_SVS_MODE_CLK_SEL		0x019C



#define DP_PLL_POLL_SLEEP_US			500

#define DP_PLL_POLL_TIMEOUT_US			10000



#define DP_PHY_POLL_SLEEP_US			500

#define DP_PHY_POLL_TIMEOUT_US			10000



#define DP_VCO_RATE_8100MHZDIV1000		8100000UL

#define DP_VCO_RATE_10800MHZDIV1000		10800000UL



#define DP_VCO_HSCLK_RATE_1620MHZDIV1000	1620000UL

#define DP_VCO_HSCLK_RATE_2700MHZDIV1000	2700000UL

#define DP_VCO_HSCLK_RATE_5400MHZDIV1000	5400000UL



struct dp_pll_db {

	struct mdss_pll_resources *pll;



	/* lane and orientation settings */

	u8 lane_cnt;

	u8 orientation;



	/* COM PHY settings */

	u32 hsclk_sel;

	u32 dec_start_mode0;

	u32 div_frac_start1_mode0;

	u32 div_frac_start2_mode0;

	u32 div_frac_start3_mode0;

	u32 lock_cmp1_mode0;

	u32 lock_cmp2_mode0;

	u32 lock_cmp3_mode0;



	/* PHY vco divider */

	u32 phy_vco_div;

};



int dp_vco_set_rate_14nm(struct clk_hw *hw, unsigned long rate,

				unsigned long parent_rate);

unsigned long dp_vco_recalc_rate_14nm(struct clk_hw *hw,

				unsigned long parent_rate);

long dp_vco_round_rate_14nm(struct clk_hw *hw, unsigned long rate,

				unsigned long *parent_rate);

int dp_vco_prepare_14nm(struct clk_hw *hw);

void dp_vco_unprepare_14nm(struct clk_hw *hw);

int dp_mux_set_parent_14nm(void *context,

				unsigned int reg, unsigned int val);

int dp_mux_get_parent_14nm(void *context,

				unsigned int reg, unsigned int *val);

#endif /* __MDSS_DP_PLL_14NM_H */

drivers/clk/qcom/mdss/mdss-dp-pll.h

+3 −0
Original line number Diff line number Diff line
@@ -27,6 +27,9 @@ static inline struct dp_pll_vco_clk *to_dp_vco_hw(struct clk_hw *hw) 
	return container_of(hw, struct dp_pll_vco_clk, hw);

}



int dp_pll_clock_register_14nm(struct platform_device *pdev,

				struct mdss_pll_resources *pll_res);



int dp_pll_clock_register_10nm(struct platform_device *pdev,

				struct mdss_pll_resources *pll_res);