Merge "clk: qcom: gcc-sdmshrike: Miscellaneous changes to the GCC plan" into msm-4.14 (eea0e323) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/clk/qcom/gcc-sdmshrike.c

+21 −8

Original line number	Original line	Diff line number	Diff line
	@@ -392,12 +392,23 @@ static struct clk_rcg2 gcc_emac_ptp_clk_src = {
	},		},
	};		};

			static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = {
			F(2500000, P_BI_TCXO, 1, 25, 192),
			F(5000000, P_BI_TCXO, 1, 25, 96),
			F(19200000, P_BI_TCXO, 1, 0, 0),
			F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
			F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
			F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
			F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0),
			{ }
			};

	static struct clk_rcg2 gcc_emac_rgmii_clk_src = {		static struct clk_rcg2 gcc_emac_rgmii_clk_src = {
	.cmd_rcgr = 0x601c,		.cmd_rcgr = 0x601c,
	.mnd_width = 8,		.mnd_width = 8,
	.hid_width = 5,		.hid_width = 5,
	.parent_map = gcc_parent_map_6,		.parent_map = gcc_parent_map_6,
	.freq_tbl = ftbl_gcc_emac_ptp_clk_src,		.freq_tbl = ftbl_gcc_emac_rgmii_clk_src,
	.clkr.hw.init = &(struct clk_init_data){		.clkr.hw.init = &(struct clk_init_data){
	.name = "gcc_emac_rgmii_clk_src",		.name = "gcc_emac_rgmii_clk_src",
	.parent_names = gcc_parent_names_6,		.parent_names = gcc_parent_names_6,
	@@ -1258,9 +1269,9 @@ static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = {
	F(400000, P_BI_TCXO, 12, 1, 4),		F(400000, P_BI_TCXO, 12, 1, 4),
	F(9600000, P_BI_TCXO, 2, 0, 0),		F(9600000, P_BI_TCXO, 2, 0, 0),
	F(19200000, P_BI_TCXO, 1, 0, 0),		F(19200000, P_BI_TCXO, 1, 0, 0),
	F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2),		F(37500000, P_GPLL0_OUT_MAIN, 16, 0, 0),
	F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),		F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),		F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
	{ }		{ }
	};		};

	@@ -1281,8 +1292,9 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
	.rate_max = (unsigned long[VDD_NUM]) {		.rate_max = (unsigned long[VDD_NUM]) {
	[VDD_MIN] = 9600000,		[VDD_MIN] = 9600000,
	[VDD_LOWER] = 19200000,		[VDD_LOWER] = 19200000,
	[VDD_LOW] = 50000000,		[VDD_LOW] = 37500000,
	[VDD_NOMINAL] = 100000000},		[VDD_LOW_L1] = 50000000,
			[VDD_NOMINAL] = 75000000},
	},		},
	};		};

	@@ -2668,14 +2680,15 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
	},		},
	};		};

	static struct clk_gate2 gcc_pcie_0_pipe_clk = {		static struct clk_branch gcc_pcie_0_pipe_clk = {
	.udelay = 500,		.halt_reg = 0x6b024,
			.halt_check = BRANCH_HALT_VOTED,
	.clkr = {		.clkr = {
	.enable_reg = 0x5200c,		.enable_reg = 0x5200c,
	.enable_mask = BIT(4),		.enable_mask = BIT(4),
	.hw.init = &(struct clk_init_data){		.hw.init = &(struct clk_init_data){
	.name = "gcc_pcie_0_pipe_clk",		.name = "gcc_pcie_0_pipe_clk",
	.ops = &clk_gate2_ops,		.ops = &clk_branch2_ops,
	},		},
	},		},
	};		};