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Commit ee8c4fdc authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "arm64: Enable Arm64 858921 errata on kryo2xx gold cores"

parents 05de21ec 4ff56241

arch/arm64/include/asm/cputype.h

+2 −0
Original line number Diff line number Diff line
@@ -128,6 +128,8 @@ 
#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)

#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)

#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)

#define MIDR_KRYO2XX_GOLD \

	MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_GOLD)



#ifndef __ASSEMBLY__

arch/arm64/kernel/cpu_errata.c

+11 −0
Original line number Diff line number Diff line
@@ -538,6 +538,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		.capability = ARM64_WORKAROUND_858921,

		MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),

	},

	{

	/* KRYO2XX all versions */

		.desc = "ARM erratum 858921",

		.capability = ARM64_WORKAROUND_858921,

		MIDR_ALL_VERSIONS(MIDR_KRYO2XX_GOLD),

	},

#endif

#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR

	{
@@ -595,6 +601,11 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
			   MIDR_CPU_VAR_REV(13, 14)),

		.enable = enable_smccc_arch_workaround_1,

	},

	{

		.capability = ARM64_HARDEN_BRANCH_PREDICTOR,

		MIDR_ALL_VERSIONS(MIDR_KRYO2XX_GOLD),

		.enable = enable_smccc_arch_workaround_1,

	},

#endif

#ifdef CONFIG_ARM64_SSBD

	{