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Commit ee451c5d authored by Amit Nischal's avatar Amit Nischal Committed by Gerrit - the friendly Code Review server
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clk: qcom: Add BRANCH_HALT_SKIP flag for gfx3d clock 



For SM6150, GX GDSC is GMU firmware controlled and 
polling for the gfx3d clock status would result into
error. Add BRANCH_HALT_SKIP flag for gfx3d clock in
order to avoid returning error.

Change-Id: I955a0e1db7ff8f4161a74aef63337ea47f634649
Signed-off-by: default avatarAmit Nischal <anischal@codeaurora.org>
parent b98e655c

drivers/clk/qcom/gpucc-sm6150.c

+1 −1
Original line number Diff line number Diff line
@@ -345,7 +345,7 @@ static struct clk_branch gpu_cc_cxo_clk = { 


static struct clk_branch gpu_cc_gx_gfx3d_clk = {

	.halt_reg = 0x1054,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_SKIP,

	.clkr = {

		.enable_reg = 0x1054,

		.enable_mask = BIT(0),