Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit ee17eb83 authored by Jianqun's avatar Jianqun Committed by Heiko Stuebner
Browse files

clk: rockchip: fix rk3288 pll status register location 



In RK3288, APLL lock status bit is in GRF_SOC_STATUS1,
but in RK3188, is GRFSOC_STATUS0.

Signed-off-by: default avatarJianqun <jay.xu@rock-chips.com>

Also name the constant accordingly as GRF_SOC_STATUS1
to prevent confusion.
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Reviewed-by: default avatarDoug Anderson <dianders@chromium.org>
Tested-by: default avatarDoug Anderson <dianders@chromium.org>
parent 11ff376f

drivers/clk/rockchip/clk-rk3288.c

+2 −2
Original line number Diff line number Diff line
@@ -20,7 +20,7 @@ 
#include "clk.h"



#define RK3288_GRF_SOC_CON(x)	(0x244 + x * 4)

#define RK3288_GRF_SOC_STATUS	0x280

#define RK3288_GRF_SOC_STATUS1	0x284



enum rk3288_plls {

	apll, dpll, cpll, gpll, npll,
@@ -733,7 +733,7 @@ static void __init rk3288_clk_init(struct device_node *np) 


	rockchip_clk_register_plls(rk3288_pll_clks,

				   ARRAY_SIZE(rk3288_pll_clks),

				   RK3288_GRF_SOC_STATUS);

				   RK3288_GRF_SOC_STATUS1);

	rockchip_clk_register_branches(rk3288_clk_branches,

				  ARRAY_SIZE(rk3288_clk_branches));

	rockchip_clk_protect_critical(rk3288_critical_clocks,