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Commit edfab628 authored by Sriharsha Allenki's avatar Sriharsha Allenki Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add PHY clocks for SS PHY on QCS405 



Add the gcc pipe clock handle to enable pipe clock
from SS PHY to core and the cfg_ahb_clk to access
the CSR registers to configure SS PHY.
Also correct the CSR register base address for SS PHY.

Change-Id: Idbc20899c8cbbecc2f8e0d13246a66a66356bf08
Signed-off-by: default avatarSriharsha Allenki <sallenki@codeaurora.org>
parent cddaf1ee

arch/arm64/boot/dts/qcom/qcs405-usb.dtsi

+6 −4
Original line number Diff line number Diff line
@@ -105,15 +105,17 @@ 
	};



	/* Secondary USB port related Super Speed PHY */

	usb_ss_phy: ssphy@7678800 {

	usb_ss_phy: ssphy@78000 {

		compatible = "qcom,usb-ssphy";

		reg = <0x7678800 0x400>;

		reg = <0x78000 0x400>;

		vdd-supply = <&pms405_l3>;

		vdda18-supply = <&pms405_l5>;

		qcom,vdd-voltage-level = <0 1050000 1050000>;



		clocks = <&clock_rpmcc RPM_SMD_LN_BB_CLK>;

		clock-names = "ref_clk";

		clocks = <&clock_rpmcc RPM_SMD_LN_BB_CLK>,

			 <&clock_gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,

			 <&clock_gcc GCC_USB3_PHY_PIPE_CLK>;

		clock-names = "ref_clk", "cfg_ahb_clk", "pipe_clk";



		resets = <&clock_gcc GCC_USB3_PHY_BCR>,

			 <&clock_gcc GCC_USB3PHY_PHY_BCR>;