Loading drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +8 −17 Original line number Diff line number Diff line Loading @@ -57,7 +57,7 @@ static u32 dsi_dsc_rc_buf_thresh[] = {0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, * Rate control - Min QP values for each ratio type in dsi_dsc_ratio_type */ static char dsi_dsc_rc_range_min_qp_1_1[][15] = { {0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13}, {0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 12}, {0, 4, 5, 5, 7, 7, 7, 7, 7, 7, 9, 9, 9, 11, 17}, {0, 4, 9, 9, 11, 11, 11, 11, 11, 11, 13, 13, 13, 15, 21}, }; Loading @@ -78,7 +78,7 @@ static char dsi_dsc_rc_range_min_qp_1_1_scr1[][15] = { */ static char dsi_dsc_rc_range_max_qp_1_1[][15] = { {4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15}, {8, 8, 9, 10, 11, 11, 11, 12, 13, 14, 15, 16, 17, 17, 19}, {4, 8, 9, 10, 11, 11, 11, 12, 13, 14, 15, 16, 17, 17, 19}, {12, 12, 13, 14, 15, 15, 15, 16, 17, 18, 19, 20, 21, 21, 23}, }; Loading @@ -89,7 +89,7 @@ static char dsi_dsc_rc_range_max_qp_1_1[][15] = { static char dsi_dsc_rc_range_max_qp_1_1_scr1[][15] = { {4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 10, 11, 11, 12, 13}, {8, 8, 9, 10, 11, 11, 11, 12, 13, 14, 14, 15, 15, 16, 17}, {12, 12, 13, 14, 15, 15, 15, 16, 17, 18, 18, 19, 19, 20, 21}, {12, 12, 13, 14, 15, 15, 15, 16, 17, 18, 18, 19, 19, 20, 23}, }; /* Loading Loading @@ -2062,7 +2062,6 @@ int dsi_dsc_populate_static_param(struct msm_display_dsc_info *dsc) int hrd_delay; int pre_num_extra_mux_bits, num_extra_mux_bits; int slice_bits; int target_bpp_x16; int data; int final_value, final_scale; int ratio_index, mod_offset; Loading Loading @@ -2104,7 +2103,7 @@ int dsi_dsc_populate_static_param(struct msm_display_dsc_info *dsc) } dsc->range_bpg_offset = dsi_dsc_rc_range_bpg_offset; if (bpp == 8) if (bpp <= 10) dsc->initial_offset = 6144; else dsc->initial_offset = 2048; /* bpp = 12 */ Loading @@ -2114,22 +2113,21 @@ int dsi_dsc_populate_static_param(struct msm_display_dsc_info *dsc) else mux_words_size = 48; /* bpc == 8/10 */ dsc->line_buf_depth = bpc + 1; if (bpc == 8) { dsc->line_buf_depth = 9; dsc->input_10_bits = 0; dsc->min_qp_flatness = 3; dsc->max_qp_flatness = 12; dsc->quant_incr_limit0 = 11; dsc->quant_incr_limit1 = 11; } else if (bpc == 10) { /* 10bpc */ dsc->line_buf_depth = 11; dsc->input_10_bits = 1; dsc->min_qp_flatness = 7; dsc->max_qp_flatness = 16; dsc->quant_incr_limit0 = 15; dsc->quant_incr_limit1 = 15; } else { /* 12 bpc */ dsc->line_buf_depth = 9; dsc->input_10_bits = 0; dsc->min_qp_flatness = 11; dsc->max_qp_flatness = 20; Loading @@ -2152,7 +2150,7 @@ int dsi_dsc_populate_static_param(struct msm_display_dsc_info *dsc) break; } dsc->det_thresh_flatness = 7 + 2*(bpc - 8); dsc->det_thresh_flatness = 2 << (bpc - 8); dsc->initial_xmit_delay = dsc->rc_model_size / (2 * bpp); Loading Loading @@ -2191,14 +2189,7 @@ int dsi_dsc_populate_static_param(struct msm_display_dsc_info *dsc) + num_extra_mux_bits); dsc->slice_bpg_offset = DIV_ROUND_UP(data, groups_total); /* bpp * 16 + 0.5 */ data = bpp * 16; data *= 2; data++; data /= 2; target_bpp_x16 = data; data = (dsc->initial_xmit_delay * target_bpp_x16) / 16; data = dsc->initial_xmit_delay * bpp; final_value = dsc->rc_model_size - data + num_extra_mux_bits; final_scale = 8 * dsc->rc_model_size / Loading Loading
drivers/gpu/drm/msm/dsi-staging/dsi_panel.c +8 −17 Original line number Diff line number Diff line Loading @@ -57,7 +57,7 @@ static u32 dsi_dsc_rc_buf_thresh[] = {0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, * Rate control - Min QP values for each ratio type in dsi_dsc_ratio_type */ static char dsi_dsc_rc_range_min_qp_1_1[][15] = { {0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13}, {0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 12}, {0, 4, 5, 5, 7, 7, 7, 7, 7, 7, 9, 9, 9, 11, 17}, {0, 4, 9, 9, 11, 11, 11, 11, 11, 11, 13, 13, 13, 15, 21}, }; Loading @@ -78,7 +78,7 @@ static char dsi_dsc_rc_range_min_qp_1_1_scr1[][15] = { */ static char dsi_dsc_rc_range_max_qp_1_1[][15] = { {4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15}, {8, 8, 9, 10, 11, 11, 11, 12, 13, 14, 15, 16, 17, 17, 19}, {4, 8, 9, 10, 11, 11, 11, 12, 13, 14, 15, 16, 17, 17, 19}, {12, 12, 13, 14, 15, 15, 15, 16, 17, 18, 19, 20, 21, 21, 23}, }; Loading @@ -89,7 +89,7 @@ static char dsi_dsc_rc_range_max_qp_1_1[][15] = { static char dsi_dsc_rc_range_max_qp_1_1_scr1[][15] = { {4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 10, 11, 11, 12, 13}, {8, 8, 9, 10, 11, 11, 11, 12, 13, 14, 14, 15, 15, 16, 17}, {12, 12, 13, 14, 15, 15, 15, 16, 17, 18, 18, 19, 19, 20, 21}, {12, 12, 13, 14, 15, 15, 15, 16, 17, 18, 18, 19, 19, 20, 23}, }; /* Loading Loading @@ -2062,7 +2062,6 @@ int dsi_dsc_populate_static_param(struct msm_display_dsc_info *dsc) int hrd_delay; int pre_num_extra_mux_bits, num_extra_mux_bits; int slice_bits; int target_bpp_x16; int data; int final_value, final_scale; int ratio_index, mod_offset; Loading Loading @@ -2104,7 +2103,7 @@ int dsi_dsc_populate_static_param(struct msm_display_dsc_info *dsc) } dsc->range_bpg_offset = dsi_dsc_rc_range_bpg_offset; if (bpp == 8) if (bpp <= 10) dsc->initial_offset = 6144; else dsc->initial_offset = 2048; /* bpp = 12 */ Loading @@ -2114,22 +2113,21 @@ int dsi_dsc_populate_static_param(struct msm_display_dsc_info *dsc) else mux_words_size = 48; /* bpc == 8/10 */ dsc->line_buf_depth = bpc + 1; if (bpc == 8) { dsc->line_buf_depth = 9; dsc->input_10_bits = 0; dsc->min_qp_flatness = 3; dsc->max_qp_flatness = 12; dsc->quant_incr_limit0 = 11; dsc->quant_incr_limit1 = 11; } else if (bpc == 10) { /* 10bpc */ dsc->line_buf_depth = 11; dsc->input_10_bits = 1; dsc->min_qp_flatness = 7; dsc->max_qp_flatness = 16; dsc->quant_incr_limit0 = 15; dsc->quant_incr_limit1 = 15; } else { /* 12 bpc */ dsc->line_buf_depth = 9; dsc->input_10_bits = 0; dsc->min_qp_flatness = 11; dsc->max_qp_flatness = 20; Loading @@ -2152,7 +2150,7 @@ int dsi_dsc_populate_static_param(struct msm_display_dsc_info *dsc) break; } dsc->det_thresh_flatness = 7 + 2*(bpc - 8); dsc->det_thresh_flatness = 2 << (bpc - 8); dsc->initial_xmit_delay = dsc->rc_model_size / (2 * bpp); Loading Loading @@ -2191,14 +2189,7 @@ int dsi_dsc_populate_static_param(struct msm_display_dsc_info *dsc) + num_extra_mux_bits); dsc->slice_bpg_offset = DIV_ROUND_UP(data, groups_total); /* bpp * 16 + 0.5 */ data = bpp * 16; data *= 2; data++; data /= 2; target_bpp_x16 = data; data = (dsc->initial_xmit_delay * target_bpp_x16) / 16; data = dsc->initial_xmit_delay * bpp; final_value = dsc->rc_model_size - data + num_extra_mux_bits; final_scale = 8 * dsc->rc_model_size / Loading