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Commit ede40902 authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull irq updates from Thomas Gleixner:
 "This update delivers:

   - Yet another interrupt chip diver (LPC32xx)
   - Core functions to handle partitioned per-cpu interrupts
   - Enhancements to the IPI core
   - Proper handling of irq type configuration
   - A large set of ARM GIC enhancements
   - The usual pile of small fixes, cleanups and enhancements"

* 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (31 commits)
  irqchip/bcm2836: Use a more generic memory barrier call
  irqchip/bcm2836: Fix compiler warning on 64-bit build
  irqchip/bcm2836: Drop smp_set_ops on arm64 builds
  irqchip/gic: Add helper functions for GIC setup and teardown
  irqchip/gic: Store GIC configuration parameters
  irqchip/gic: Pass GIC pointer to save/restore functions
  irqchip/gic: Return an error if GIC initialisation fails
  irqchip/gic: Remove static irq_chip definition for eoimode1
  irqchip/gic: Don't initialise chip if mapping IO space fails
  irqchip/gic: WARN if setting the interrupt type for a PPI fails
  irqchip/gic: Don't unnecessarily write the IRQ configuration
  irqchip: Mask the non-type/sense bits when translating an IRQ
  genirq: Ensure IRQ descriptor is valid when setting-up the IRQ
  irqchip/gic-v3: Configure all interrupts as non-secure Group-1
  irqchip/gic-v2m: Add workaround for Broadcom NS2 GICv2m erratum
  irqchip/irq-alpine-msi: Don't use <asm-generic/msi.h>
  irqchip/mbigen: Checking for IS_ERR() instead of NULL
  irqchip/gic-v3: Remove inexistant register definition
  irqchip/gicv3-its: Don't allow devices whose ID is outside range
  irqchip: Add LPC32xx interrupt controller driver
  ...
parents 91e8d0cb 0097852c

Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt

+32 −2
Original line number Diff line number Diff line
@@ -11,6 +11,8 @@ Main node required properties: 
- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt source. Must be a single cell with a value of at least 3.

  If the system requires describing PPI affinity, then the value must

  be at least 4.



  The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI

  interrupts. Other values are reserved for future use.
@@ -24,7 +26,14 @@ Main node required properties: 
		1 = edge triggered

		4 = level triggered



  Cells 4 and beyond are reserved for future use and must have a value

  The 4th cell is a phandle to a node describing a set of CPUs this

  interrupt is affine to. The interrupt must be a PPI, and the node

  pointed must be a subnode of the "ppi-partitions" subnode. For

  interrupt types other than PPI or PPIs that are not partitionned,

  this cell must be zero. See the "ppi-partitions" node description

  below.



  Cells 5 and beyond are reserved for future use and must have a value

  of 0 if present.



- reg : Specifies base physical address(s) and size of the GIC
@@ -50,6 +59,11 @@ Optional 


Sub-nodes:



PPI affinity can be expressed as a single "ppi-partitions" node,

containing a set of sub-nodes, each with the following property:

- affinity: Should be a list of phandles to CPU nodes (as described in

Documentation/devicetree/bindings/arm/cpus.txt).



GICv3 has one or more Interrupt Translation Services (ITS) that are

used to route Message Signalled Interrupts (MSI) to the CPUs.
@@ -91,7 +105,7 @@ Examples: 


	gic: interrupt-controller@2c010000 {

		compatible = "arm,gic-v3";

		#interrupt-cells = <3>;

		#interrupt-cells = <4>;

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;
@@ -119,4 +133,20 @@ Examples: 
			#msi-cells = <1>;

			reg = <0x0 0x2c400000 0 0x200000>;

		};



		ppi-partitions {

			part0: interrupt-partition-0 {

				affinity = <&cpu0 &cpu2>;

			};



			part1: interrupt-partition-1 {

				affinity = <&cpu1 &cpu3>;

			};

		};

	};





	device@0 {

		reg = <0 0 0 4>;

		interrupts = <1 1 4 &part0>;

	};

Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt

0 → 100644
+30 −0
Original line number Diff line number Diff line 
* Freescale Layerscape SCFG PCIe MSI controller



Required properties:



- compatible: should be "fsl,<soc-name>-msi" to identify

	      Layerscape PCIe MSI controller block such as:

              "fsl,1s1021a-msi"

              "fsl,1s1043a-msi"

- msi-controller: indicates that this is a PCIe MSI controller node

- reg: physical base address of the controller and length of memory mapped.

- interrupts: an interrupt to the parent interrupt controller.



Optional properties:

- interrupt-parent: the phandle to the parent interrupt controller.



This interrupt controller hardware is a second level interrupt controller that

is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based

platforms. If interrupt-parent is not provided, the default parent interrupt

controller will be used.

Each PCIe node needs to have property msi-parent that points to

MSI controller node



Examples:



	msi1: msi-controller@1571000 {

		compatible = "fsl,1s1043a-msi";

		reg = <0x0 0x1571000 0x0 0x8>,

		msi-controller;

		interrupts = <0 116 0x4>;

	};

arch/arm/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -531,6 +531,8 @@ config ARCH_LPC32XX 
	select COMMON_CLK

	select CPU_ARM926T

	select GENERIC_CLOCKEVENTS

	select MULTI_IRQ_HANDLER

	select SPARSE_IRQ

	select USE_OF

	help

	  Support for the NXP LPC32XX family of processors

arch/arm/mach-lpc32xx/phy3250.c

+0 −1
Original line number Diff line number Diff line
@@ -206,7 +206,6 @@ static const char *const lpc32xx_dt_compat[] __initconst = { 
DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)")

	.atag_offset	= 0x100,

	.map_io		= lpc32xx_map_io,

	.init_irq	= lpc32xx_init_irq,

	.init_machine	= lpc3250_machine_init,

	.dt_compat	= lpc32xx_dt_compat,

MACHINE_END

drivers/irqchip/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ config ARM_GIC_V3 
	select IRQ_DOMAIN

	select MULTI_IRQ_HANDLER

	select IRQ_DOMAIN_HIERARCHY

	select PARTITION_PERCPU



config ARM_GIC_V3_ITS

	bool
@@ -244,3 +245,11 @@ config IRQ_MXS 
config MVEBU_ODMI

	bool

	select GENERIC_MSI_IRQ_DOMAIN



config LS_SCFG_MSI

	def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE

	depends on PCI && PCI_MSI

	select PCI_MSI_IRQ_DOMAIN



config PARTITION_PERCPU

	bool