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Commit ed8e2081 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "defconfig: enable PCIe host driver for sdxprairie"

parents 6c9748ac 410254eb

arch/arm/configs/vendor/sdxprairie-perf_defconfig

+2 −0
Original line number Diff line number Diff line
@@ -31,6 +31,8 @@ CONFIG_PARTITION_ADVANCED=y 
CONFIG_ARCH_QCOM=y

CONFIG_ARCH_SDXPRAIRIE=y

# CONFIG_VDSO is not set

CONFIG_PCI_MSM=y

CONFIG_PCI_MSM_MSI=y

CONFIG_PREEMPT=y

CONFIG_CMA=y

CONFIG_SECCOMP=y

arch/arm/configs/vendor/sdxprairie_defconfig

+2 −0
Original line number Diff line number Diff line
@@ -31,6 +31,8 @@ CONFIG_PARTITION_ADVANCED=y 
CONFIG_ARCH_QCOM=y

CONFIG_ARCH_SDXPRAIRIE=y

# CONFIG_VDSO is not set

CONFIG_PCI_MSM=y

CONFIG_PCI_MSM_MSI=y

CONFIG_PREEMPT=y

CONFIG_CMA=y

CONFIG_SECCOMP=y

drivers/pci/host/pci-msm.c

+0 −27
Original line number Diff line number Diff line
@@ -289,8 +289,6 @@ enum msm_pcie_res { 
	MSM_PCIE_RES_ELBI,

	MSM_PCIE_RES_IATU,

	MSM_PCIE_RES_CONF,

	MSM_PCIE_RES_IO,

	MSM_PCIE_RES_BARS,

	MSM_PCIE_RES_TCSR,

	MSM_PCIE_MAX_RES,

};
@@ -538,15 +536,11 @@ struct msm_pcie_dev_t { 
	void __iomem		     *iatu;

	void __iomem		     *dm_core;

	void __iomem		     *conf;

	void __iomem		     *bars;

	void __iomem		     *tcsr;



	uint32_t			    axi_bar_start;

	uint32_t			    axi_bar_end;



	struct resource		   *dev_mem_res;

	struct resource		   *dev_io_res;



	uint32_t			    wake_n;

	uint32_t			    vreg_n;

	uint32_t			    gpio_n;
@@ -852,8 +846,6 @@ static const struct msm_pcie_res_info_t msm_pcie_res_info[MSM_PCIE_MAX_RES] = { 
	{"elbi",	NULL, NULL},

	{"iatu",	NULL, NULL},

	{"conf",	NULL, NULL},

	{"io",		NULL, NULL},

	{"bars",	NULL, NULL},

	{"tcsr",	NULL, NULL}

};
@@ -888,17 +880,6 @@ static void msm_pcie_check_l1ss_support_all(struct msm_pcie_dev_t *dev); 


static void msm_pcie_config_link_pm(struct msm_pcie_dev_t *dev, bool enable);



#ifdef CONFIG_ARM

static inline void msm_pcie_fixup_irqs(struct msm_pcie_dev_t *dev)

{

	pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);

}

#else

static inline void msm_pcie_fixup_irqs(struct msm_pcie_dev_t *dev)

{

}

#endif



static inline void msm_pcie_write_reg(void __iomem *base, u32 offset, u32 value)

{

	writel_relaxed(value, base + offset);
@@ -3722,11 +3703,7 @@ static int msm_pcie_get_resources(struct msm_pcie_dev_t *dev, 
	dev->iatu = dev->res[MSM_PCIE_RES_IATU].base;

	dev->dm_core = dev->res[MSM_PCIE_RES_DM_CORE].base;

	dev->conf = dev->res[MSM_PCIE_RES_CONF].base;

	dev->bars = dev->res[MSM_PCIE_RES_BARS].base;

	dev->tcsr = dev->res[MSM_PCIE_RES_TCSR].base;

	dev->dev_mem_res = dev->res[MSM_PCIE_RES_BARS].resource;

	dev->dev_io_res = dev->res[MSM_PCIE_RES_IO].resource;

	dev->dev_io_res->flags = IORESOURCE_IO;



out:

	kfree(clkfreq);
@@ -3743,10 +3720,7 @@ static void msm_pcie_release_resources(struct msm_pcie_dev_t *dev) 
	dev->iatu = NULL;

	dev->dm_core = NULL;

	dev->conf = NULL;

	dev->bars = NULL;

	dev->tcsr = NULL;

	dev->dev_mem_res = NULL;

	dev->dev_io_res = NULL;

}



static int msm_pcie_enable(struct msm_pcie_dev_t *dev, u32 options)
@@ -4383,7 +4357,6 @@ int msm_pcie_enumerate(u32 rc_idx) 


			bus = bridge->bus;



			msm_pcie_fixup_irqs(dev);

			pci_assign_unassigned_bus_resources(bus);

			pci_bus_add_devices(bus);