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Commit ed709d13 authored by Scott Wood's avatar Scott Wood Committed by Paul Mackerras
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[POWERPC] Fix IPIC pending register assignments 



This patch fixes the assignment of pending registers to IRQ numbers for
the IPIC; the code previously assigned all IRQs to the high pending word
regardless of which word the interrupt belonged to.

Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent 7d452c32

arch/powerpc/sysdev/ipic.c

+21 −21
Original line number Diff line number Diff line
@@ -210,7 +210,7 @@ static struct ipic_info ipic_info[] = { 
		.prio_mask = 4,

	},

	[64] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SIPNR_L,

		.mask	= IPIC_SIMSR_L,

		.prio	= IPIC_SMPRR_A,

		.force	= IPIC_SIFCR_L,
@@ -218,7 +218,7 @@ static struct ipic_info ipic_info[] = { 
		.prio_mask = 0,

	},

	[65] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SIPNR_L,

		.mask	= IPIC_SIMSR_L,

		.prio	= IPIC_SMPRR_A,

		.force	= IPIC_SIFCR_L,
@@ -226,7 +226,7 @@ static struct ipic_info ipic_info[] = { 
		.prio_mask = 1,

	},

	[66] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SIPNR_L,

		.mask	= IPIC_SIMSR_L,

		.prio	= IPIC_SMPRR_A,

		.force	= IPIC_SIFCR_L,
@@ -234,7 +234,7 @@ static struct ipic_info ipic_info[] = { 
		.prio_mask = 2,

	},

	[67] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SIPNR_L,

		.mask	= IPIC_SIMSR_L,

		.prio	= IPIC_SMPRR_A,

		.force	= IPIC_SIFCR_L,
@@ -242,7 +242,7 @@ static struct ipic_info ipic_info[] = { 
		.prio_mask = 3,

	},

	[68] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SIPNR_L,

		.mask	= IPIC_SIMSR_L,

		.prio	= IPIC_SMPRR_B,

		.force	= IPIC_SIFCR_L,
@@ -250,7 +250,7 @@ static struct ipic_info ipic_info[] = { 
		.prio_mask = 0,

	},

	[69] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SIPNR_L,

		.mask	= IPIC_SIMSR_L,

		.prio	= IPIC_SMPRR_B,

		.force	= IPIC_SIFCR_L,
@@ -258,7 +258,7 @@ static struct ipic_info ipic_info[] = { 
		.prio_mask = 1,

	},

	[70] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SIPNR_L,

		.mask	= IPIC_SIMSR_L,

		.prio	= IPIC_SMPRR_B,

		.force	= IPIC_SIFCR_L,
@@ -266,7 +266,7 @@ static struct ipic_info ipic_info[] = { 
		.prio_mask = 2,

	},

	[71] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SIPNR_L,

		.mask	= IPIC_SIMSR_L,

		.prio	= IPIC_SMPRR_B,

		.force	= IPIC_SIFCR_L,
@@ -274,91 +274,91 @@ static struct ipic_info ipic_info[] = { 
		.prio_mask = 3,

	},

	[72] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SIPNR_L,

		.mask	= IPIC_SIMSR_L,

		.prio	= 0,

		.force	= IPIC_SIFCR_L,

		.bit	= 8,

	},

	[73] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SIPNR_L,

		.mask	= IPIC_SIMSR_L,

		.prio	= 0,

		.force	= IPIC_SIFCR_L,

		.bit	= 9,

	},

	[74] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SIPNR_L,

		.mask	= IPIC_SIMSR_L,

		.prio	= 0,

		.force	= IPIC_SIFCR_L,

		.bit	= 10,

	},

	[75] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SIPNR_L,

		.mask	= IPIC_SIMSR_L,

		.prio	= 0,

		.force	= IPIC_SIFCR_L,

		.bit	= 11,

	},

	[76] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SIPNR_L,

		.mask	= IPIC_SIMSR_L,

		.prio	= 0,

		.force	= IPIC_SIFCR_L,

		.bit	= 12,

	},

	[77] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SIPNR_L,

		.mask	= IPIC_SIMSR_L,

		.prio	= 0,

		.force	= IPIC_SIFCR_L,

		.bit	= 13,

	},

	[78] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SIPNR_L,

		.mask	= IPIC_SIMSR_L,

		.prio	= 0,

		.force	= IPIC_SIFCR_L,

		.bit	= 14,

	},

	[79] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SIPNR_L,

		.mask	= IPIC_SIMSR_L,

		.prio	= 0,

		.force	= IPIC_SIFCR_L,

		.bit	= 15,

	},

	[80] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SIPNR_L,

		.mask	= IPIC_SIMSR_L,

		.prio	= 0,

		.force	= IPIC_SIFCR_L,

		.bit	= 16,

	},

	[84] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SIPNR_L,

		.mask	= IPIC_SIMSR_L,

		.prio	= 0,

		.force	= IPIC_SIFCR_L,

		.bit	= 20,

	},

	[85] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SIPNR_L,

		.mask	= IPIC_SIMSR_L,

		.prio	= 0,

		.force	= IPIC_SIFCR_L,

		.bit	= 21,

	},

	[90] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SIPNR_L,

		.mask	= IPIC_SIMSR_L,

		.prio	= 0,

		.force	= IPIC_SIFCR_L,

		.bit	= 26,

	},

	[91] = {

		.pend	= IPIC_SIPNR_H,

		.pend	= IPIC_SIPNR_L,

		.mask	= IPIC_SIMSR_L,

		.prio	= 0,

		.force	= IPIC_SIFCR_L,