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Commit ece62678 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-for-linus-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 

Pull clk framework updates from Michael Turquette:
 "The clk framework and driver changes for 4.5 look pretty typical.  The
  bulk of the changes are to clk controller drivers, though some
  improvements to the core and some re-usable blocks/templates also
  received some love.

  In this past cycle the clk maintainers developed a good workflow for
  handling the common case of patch submissions containing a new
  drivers, new shared Device Tree header and a new Device Tree binding
  description.  This requires coordination with the Device Tree
  maintainers and with the architecture maintainers (typically the
  arm-soc tree in our case).

  This explains the increase in changes to include/dt-bindings/... and
  to Documentation/devicetree/bindings/clock/... coming from the clk
  tree.  The same commits can be expected to come through those trees on
  occasion, through the use of shared, immutable branches"

* tag 'clk-for-linus-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (125 commits)
  clk: remove duplicated COMMON_CLK_NXP record from clk/Kconfig
  clk: fix clk-gpio.c with optional clock= DT property
  clk: rockchip: fix section mismatches with new child-clocks
  clk: gpio: handle error codes for of_clk_get_parent_count()
  clk: gpio: fix memory leak
  clk: shmobile: r8a7795: Add SATA0 clock
  clk: bcm2835: Add PWM clock support
  clk: bcm2835: Support for clock parent selection
  clk: bcm2835: add a round up ability to the clock divisor
  clk: lpc32xx: add common clock framework driver
  clk: lpc18xx: add NXP specific COMMON_CLK_NXP configuration symbol
  dt-bindings: clock: add NXP LPC32xx clock list for consumers
  dt-bindings: clock: add description of LPC32xx USB clock controller
  dt-bindings: clock: add description of LPC32xx clock controller
  clk: rockchip: rk3036: include downstream muxes into fractional dividers
  clk: add flag for clocks that need to be enabled on rate changes
  clk: rockchip: Allow the RK3288 SPDIF clocks to change their parent
  clk: rockchip: include downstream muxes into fractional dividers
  clk: rockchip: handle mux dependency of fractional dividers
  clk: bcm2835: Add a driver for the auxiliary peripheral clock gates.
  ...
parents d45187aa 3da834e3

Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.txt

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Broadcom BCM2835 auxiliary peripheral support



This binding uses the common clock binding:

    Documentation/devicetree/bindings/clock/clock-bindings.txt



The auxiliary peripherals (UART, SPI1, and SPI2) have a small register

area controlling clock gating to the peripherals, and providing an IRQ

status register.



Required properties:

- compatible:	Should be "brcm,bcm2835-aux"

- #clock-cells:	Should be <1>. The permitted clock-specifier values can be

		  found in include/dt-bindings/clock/bcm2835-aux.h

- reg:		Specifies base physical address and size of the registers

- clocks:	The parent clock phandle



Example:



	clocks: cprman@7e101000 {

		compatible = "brcm,bcm2835-cprman";

		#clock-cells = <1>;

		reg = <0x7e101000 0x2000>;

		clocks = <&clk_osc>;

	};



	aux: aux@0x7e215004 {

		compatible = "brcm,bcm2835-aux";

		#clock-cells = <1>;

		reg = <0x7e215000 0x8>;

		clocks = <&clocks BCM2835_CLOCK_VPU>;

	};

Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt

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@@ -208,3 +208,8 @@ These clock IDs are defined in: 
    ch3_unused	lcpll_ports	4	BCM_NS2_LCPLL_PORTS_CH3_UNUSED

    ch3_unused	lcpll_ports	4	BCM_NS2_LCPLL_PORTS_CH3_UNUSED

    ch4_unused	lcpll_ports	5	BCM_NS2_LCPLL_PORTS_CH4_UNUSED

    ch4_unused	lcpll_ports	5	BCM_NS2_LCPLL_PORTS_CH4_UNUSED

    ch5_unused	lcpll_ports	6	BCM_NS2_LCPLL_PORTS_CH5_UNUSED

    ch5_unused	lcpll_ports	6	BCM_NS2_LCPLL_PORTS_CH5_UNUSED



BCM63138

--------

PLL and leaf clock compatible strings for BCM63138 are:

    "brcm,bcm63138-armpll"

Documentation/devicetree/bindings/clock/cs2000-cp.txt

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CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier



Required properties:



- compatible:		"cirrus,cs2000-cp"

- reg:			The chip select number on the I2C bus

- clocks:		common clock binding for CLK_IN, XTI/REF_CLK

- clock-names:		CLK_IN : clk_in, XTI/REF_CLK : ref_clk

- #clock-cells:		must be <0>



Example:



&i2c2 {

	...

	cs2000: clk_multiplier@4f {

		#clock-cells = <0>;

		compatible = "cirrus,cs2000-cp";

		reg = <0x4f>;

		clocks = <&rcar_sound 0>, <&x12_clk>;

		clock-names = "clk_in", "ref_clk";

	};

};

Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt

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NVIDIA Tegra210 Clock And Reset Controller



This binding uses the common clock binding:

Documentation/devicetree/bindings/clock/clock-bindings.txt



The CAR (Clock And Reset) Controller on Tegra is the HW module responsible

for muxing and gating Tegra's clocks, and setting their rates.



Required properties :

- compatible : Should be "nvidia,tegra210-car"

- reg : Should contain CAR registers location and length

- clocks : Should contain phandle and clock specifiers for two clocks:

  the 32 KHz "32k_in".

- #clock-cells : Should be 1.

  In clock consumers, this cell represents the clock ID exposed by the

  CAR. The assignments may be found in header file

  <dt-bindings/clock/tegra210-car.h>.

- #reset-cells : Should be 1.

  In clock consumers, this cell represents the bit number in the CAR's

  array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.



Example SoC include file:



/ {

	tegra_car: clock {

		compatible = "nvidia,tegra210-car";

		reg = <0x60006000 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	usb@c5004000 {

		clocks = <&tegra_car TEGRA210_CLK_USB2>;

	};

};



Example board file:



/ {

	clocks {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <0>;



		clk_32k: clock@1 {

			compatible = "fixed-clock";

			reg = <1>;

			#clock-cells = <0>;

			clock-frequency = <32768>;

		};

	};



	&tegra_car {

		clocks = <&clk_32k>;

	};

};

Documentation/devicetree/bindings/clock/nxp,lpc3220-clk.txt

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NXP LPC32xx Clock Controller



Required properties:

- compatible: should be "nxp,lpc3220-clk"

- reg:  should contain clock controller registers location and length

- #clock-cells: must be 1, the cell holds id of a clock provided by the

  clock controller

- clocks: phandles of external oscillators, the list must contain one

  32768 Hz oscillator and may have one optional high frequency oscillator

- clock-names: list of external oscillator clock names, must contain

  "xtal_32k" and may have optional "xtal"



Examples:



	/* System Control Block */

	scb {

		compatible = "simple-bus";

		ranges = <0x0 0x040004000 0x00001000>;

		#address-cells = <1>;

		#size-cells = <1>;



		clk: clock-controller@0 {

			compatible = "nxp,lpc3220-clk";

			reg = <0x00 0x114>;

			#clock-cells = <1>;



			clocks = <&xtal_32k>, <&xtal>;

			clock-names = "xtal_32k", "xtal";

		};

	};