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Commit ecab22aa authored by Vegard Nossum's avatar Vegard Nossum Committed by Ingo Molnar
Browse files

x86: use symbolic constants for MSR_IA32_MISC_ENABLE bits 



Impact: Cleanup. No functional changes.

Signed-off-by: default avatarVegard Nossum <vegard.nossum@gmail.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 71d8f978

arch/x86/kernel/cpu/cpufreq/e_powersaver.c

+3 −3
Original line number Diff line number Diff line
@@ -204,12 +204,12 @@ static int eps_cpu_init(struct cpufreq_policy *policy) 
	}

	/* Enable Enhanced PowerSaver */

	rdmsrl(MSR_IA32_MISC_ENABLE, val);

	if (!(val & 1 << 16)) {

		val |= 1 << 16;

	if (!(val & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {

		val |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;

		wrmsrl(MSR_IA32_MISC_ENABLE, val);

		/* Can be locked at 0 */

		rdmsrl(MSR_IA32_MISC_ENABLE, val);

		if (!(val & 1 << 16)) {

		if (!(val & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {

			printk(KERN_INFO "eps: Can't enable Enhanced PowerSaver\n");

			return -ENODEV;

		}

arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c

+3 −3
Original line number Diff line number Diff line
@@ -390,14 +390,14 @@ static int centrino_cpu_init(struct cpufreq_policy *policy) 
	   enable it if not. */

	rdmsr(MSR_IA32_MISC_ENABLE, l, h);



	if (!(l & (1<<16))) {

		l |= (1<<16);

	if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {

		l |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;

		dprintk("trying to enable Enhanced SpeedStep (%x)\n", l);

		wrmsr(MSR_IA32_MISC_ENABLE, l, h);



		/* check to see if it stuck */

		rdmsr(MSR_IA32_MISC_ENABLE, l, h);

		if (!(l & (1<<16))) {

		if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {

			printk(KERN_INFO PFX

				"couldn't enable Enhanced SpeedStep\n");

			return -ENODEV;

arch/x86/kernel/cpu/intel.c

+2 −2
Original line number Diff line number Diff line
@@ -147,10 +147,10 @@ static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c) 
	 */

	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {

		rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);

		if ((lo & (1<<9)) == 0) {

		if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {

			printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");

			printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");

			lo |= (1<<9);	/* Disable hw prefetching */

			lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;

			wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);

		}

	}

arch/x86/kernel/cpu/mcheck/mce_intel_64.c

+3 −3
Original line number Diff line number Diff line
@@ -49,13 +49,13 @@ static void __cpuinit intel_init_thermal(struct cpuinfo_x86 *c) 
	 */

	rdmsr(MSR_IA32_MISC_ENABLE, l, h);

	h = apic_read(APIC_LVTTHMR);

	if ((l & (1 << 3)) && (h & APIC_DM_SMI)) {

	if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {

		printk(KERN_DEBUG

		       "CPU%d: Thermal monitoring handled by SMI\n", cpu);

		return;

	}



	if (cpu_has(c, X86_FEATURE_TM2) && (l & (1 << 13)))

	if (cpu_has(c, X86_FEATURE_TM2) && (l & MSR_IA32_MISC_ENABLE_TM2))

		tm2 = 1;



	if (h & APIC_VECTOR_MASK) {
@@ -73,7 +73,7 @@ static void __cpuinit intel_init_thermal(struct cpuinfo_x86 *c) 
	wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03, h);



	rdmsr(MSR_IA32_MISC_ENABLE, l, h);

	wrmsr(MSR_IA32_MISC_ENABLE, l | (1 << 3), h);

	wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);



	l = apic_read(APIC_LVTTHMR);

	apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);

arch/x86/kernel/cpu/mcheck/p4.c

+2 −2
Original line number Diff line number Diff line
@@ -85,7 +85,7 @@ static void intel_init_thermal(struct cpuinfo_x86 *c) 
	 */

	rdmsr(MSR_IA32_MISC_ENABLE, l, h);

	h = apic_read(APIC_LVTTHMR);

	if ((l & (1<<3)) && (h & APIC_DM_SMI)) {

	if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {

		printk(KERN_DEBUG "CPU%d: Thermal monitoring handled by SMI\n",

				cpu);

		return; /* -EBUSY */
@@ -111,7 +111,7 @@ static void intel_init_thermal(struct cpuinfo_x86 *c) 
	vendor_thermal_interrupt = intel_thermal_interrupt;



	rdmsr(MSR_IA32_MISC_ENABLE, l, h);

	wrmsr(MSR_IA32_MISC_ENABLE, l | (1<<3), h);

	wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);



	l = apic_read(APIC_LVTTHMR);

	apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);