Merge "drm/msm/sde: introduce sde_mdp_vsync_sel feature flag in top blk" (ec99174e) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+10 −2

Original line number	Diff line number	Diff line
		@@ -2712,7 +2712,7 @@ static int sde_pp_parse_dt(struct device_node np, struct sde_mdss_cfg sde_cfg)
		int rc, prop_count[PP_PROP_MAX], i;
		struct sde_prop_value *prop_value = NULL;
		bool prop_exists[PP_PROP_MAX];
		u32 off_count;
		u32 off_count, major_version;
		struct sde_pingpong_cfg *pp;
		struct sde_pingpong_sub_blks *sblk;

		@@ -2761,6 +2761,9 @@ static int sde_pp_parse_dt(struct device_node np, struct sde_mdss_cfg sde_cfg)
		sblk->te.id = SDE_PINGPONG_TE;
		snprintf(sblk->te.name, SDE_HW_BLK_NAME_LEN, "te_%u",
		pp->id - PINGPONG_0);

		major_version = SDE_HW_MAJOR(sde_cfg->hwversion);
		if (major_version < SDE_HW_MAJOR(SDE_HW_VER_500))
		set_bit(SDE_PINGPONG_TE, &pp->features);

		sblk->te2.base = PROP_VALUE_ACCESS(prop_value, TE2_OFF, i);
		@@ -2813,6 +2816,7 @@ static int sde_parse_dt(struct device_node np, struct sde_mdss_cfg cfg)
		struct sde_prop_value *prop_value = NULL;
		bool prop_exists[SDE_PROP_MAX];
		const char *type;
		u32 major_version;

		if (!cfg) {
		SDE_ERROR("invalid argument\n");
		@@ -2900,6 +2904,10 @@ static int sde_parse_dt(struct device_node np, struct sde_mdss_cfg cfg)
		cfg->mdp[0].smart_panel_align_mode =
		PROP_VALUE_ACCESS(prop_value, SMART_PANEL_ALIGN_MODE, 0);

		major_version = SDE_HW_MAJOR(sde_cfg->hwversion);
		if (major_version < SDE_HW_MAJOR(SDE_HW_VER_500))
		set_bit(SDE_MDP_VSYNC_SEL, &cfg->mdp[0].features);

		rc = of_property_read_string(np, sde_prop[QSEED_TYPE].prop_name, &type);
		if (!rc && !strcmp(type, "qseedv3")) {
		cfg->qseed_type = SDE_SSPP_SCALER_QSEED3;

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -105,6 +105,7 @@ enum {
		* @SDE_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth
		* compression initial revision
		* @SDE_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5
		* @SDE_MDP_VSYNC_SEL Vsync selection for command mode panels
		* @SDE_MDP_MAX Maximum value

		*/
		@@ -114,6 +115,7 @@ enum {
		SDE_MDP_BWC,
		SDE_MDP_UBWC_1_0,
		SDE_MDP_UBWC_1_5,
		SDE_MDP_VSYNC_SEL,
		SDE_MDP_MAX
		};

drivers/gpu/drm/msm/sde/sde_hw_top.c

+40 −14

Original line number	Diff line number	Diff line
		@@ -221,28 +221,16 @@ static void sde_hw_get_danger_status(struct sde_hw_mdp *mdp,
		status->wb[WB_3] = 0;
		}

		static void sde_hw_setup_vsync_source(struct sde_hw_mdp *mdp,
		static void _update_vsync_source(struct sde_hw_mdp *mdp,
		struct sde_vsync_source_cfg *cfg)
		{
		struct sde_hw_blk_reg_map *c;
		u32 reg, wd_load_value, wd_ctl, wd_ctl2, i;
		static const u32 pp_offset[PINGPONG_MAX] = {0xC, 0x8, 0x4, 0x13, 0x18};

		if (!mdp \|\| !cfg \|\| (cfg->pp_count > ARRAY_SIZE(cfg->ppnumber)))
		if (!mdp \|\| !cfg)
		return;

		c = &mdp->hw;
		reg = SDE_REG_READ(c, MDP_VSYNC_SEL);
		for (i = 0; i < cfg->pp_count; i++) {
		int pp_idx = cfg->ppnumber[i] - PINGPONG_0;

		if (pp_idx >= ARRAY_SIZE(pp_offset))
		continue;

		reg &= ~(0xf << pp_offset[pp_idx]);
		reg \|= (cfg->vsync_source & 0xf) << pp_offset[pp_idx];
		}
		SDE_REG_WRITE(c, MDP_VSYNC_SEL, reg);

		if (cfg->vsync_source >= SDE_VSYNC_SOURCE_WD_TIMER_4 &&
		cfg->vsync_source <= SDE_VSYNC_SOURCE_WD_TIMER_0) {
		@@ -293,6 +281,39 @@ static void sde_hw_setup_vsync_source(struct sde_hw_mdp *mdp,
		}
		}

		static void sde_hw_setup_vsync_source(struct sde_hw_mdp *mdp,
		struct sde_vsync_source_cfg *cfg)
		{
		struct sde_hw_blk_reg_map *c;
		u32 reg, wd_load_value, wd_ctl, wd_ctl2, i;
		static const u32 pp_offset[PINGPONG_MAX] = {0xC, 0x8, 0x4, 0x13, 0x18};

		if (!mdp \|\| !cfg \|\| (cfg->pp_count > ARRAY_SIZE(cfg->ppnumber)))
		return;

		c = &mdp->hw;
		reg = SDE_REG_READ(c, MDP_VSYNC_SEL);
		for (i = 0; i < cfg->pp_count; i++) {
		int pp_idx = cfg->ppnumber[i] - PINGPONG_0;

		if (pp_idx >= ARRAY_SIZE(pp_offset))
		continue;

		reg &= ~(0xf << pp_offset[pp_idx]);
		reg \|= (cfg->vsync_source & 0xf) << pp_offset[pp_idx];
		}
		SDE_REG_WRITE(c, MDP_VSYNC_SEL, reg);

		_update_vsync_source(mdp, cfg);
		}

		static void sde_hw_setup_vsync_source_v1(struct sde_hw_mdp *mdp,
		struct sde_vsync_source_cfg *cfg)
		{
		_update_vsync_source(mdp, cfg);
		}


		static void sde_hw_get_safe_status(struct sde_hw_mdp *mdp,
		struct sde_danger_safe_status *status)
		{
		@@ -393,6 +414,11 @@ static void _setup_mdp_ops(struct sde_hw_mdp_ops *ops,
		ops->setup_dce = sde_hw_setup_dce;
		ops->reset_ubwc = sde_hw_reset_ubwc;
		ops->intf_audio_select = sde_hw_intf_audio_select;
		if (cap & BIT(SDE_MDP_VSYNC_SEL))
		ops->setup_vsync_source = sde_hw_setup_vsync_source;
		else
		ops->setup_vsync_source = sde_hw_setup_vsync_source_v1;

		}

		static const struct sde_mdp_cfg *_top_offset(enum sde_mdp mdp,