Merge "pinctrl: qcom: Add irq_enable callback for msm gpio"

	raw_spin_unlock_irqrestore(&pctrl->lock, flags);

}

static void msm_gpio_irq_enable(struct irq_data *d)

{

	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);

	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);

	const struct msm_pingroup *g;

	unsigned long flags;

	u32 val;

	g = &pctrl->soc->groups[d->hwirq];

	raw_spin_lock_irqsave(&pctrl->lock, flags);

	/* clear the interrupt status bit before unmask to avoid

	 * any erraneous interrupts that would have got latched

	 * when the intterupt is not in use.

	 */

	val = readl(pctrl->regs + g->intr_status_reg);

	val &= ~BIT(g->intr_status_bit);

	writel(val, pctrl->regs + g->intr_status_reg);

	val = readl(pctrl->regs + g->intr_cfg_reg);

	val |= BIT(g->intr_enable_bit);

	writel(val, pctrl->regs + g->intr_cfg_reg);

	set_bit(d->hwirq, pctrl->enabled_irqs);

	raw_spin_unlock_irqrestore(&pctrl->lock, flags);

}

static void msm_gpio_irq_unmask(struct irq_data *d)

{

	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);

static struct irq_chip msm_gpio_irq_chip = {

	.name           = "msmgpio",

	.irq_enable     = msm_gpio_irq_enable,

	.irq_mask       = msm_gpio_irq_mask,

	.irq_unmask     = msm_gpio_irq_unmask,

	.irq_ack        = msm_gpio_irq_ack,