Merge "clk: qcom: clk-rcg2: Introduce a cfg offset for RCGs" (ec03da5a) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/clk/qcom/Kconfig

+1 −0

Original line number	Diff line number	Diff line
		@@ -318,6 +318,7 @@ config MSM_CAMCC_SDMSHRIKE

		config MDM_GCC_QCS405
		tristate "QCS405 Global Clock Controller"
		select QCOM_GDSC
		depends on COMMON_CLK_QCOM
		help
		Support for the global clock controller on Qualcomm Technologies, Inc

drivers/clk/qcom/clk-alpha-pll.c

+14 −20

Original line number	Diff line number	Diff line
		@@ -181,15 +181,10 @@ void clk_alpha_pll_configure(struct clk_alpha_pll pll, struct regmap regmap,
		{
		u32 val, mask;

		if (config->l)
		regmap_write(regmap, pll->offset + PLL_L_VAL,
		config->l);
		if (config->alpha)
		regmap_write(regmap, pll->offset + PLL_ALPHA_VAL,
		config->alpha);
		if (config->alpha_u)
		regmap_write(regmap, pll->offset + PLL_ALPHA_VAL_U,
		config->alpha_u);
		regmap_write(regmap, pll->offset + PLL_L_VAL, config->l);
		regmap_write(regmap, pll->offset + PLL_ALPHA_VAL, config->alpha);
		regmap_write(regmap, pll->offset + PLL_ALPHA_VAL_U, config->alpha_u);

		if (config->config_ctl_val)
		regmap_write(regmap, pll->offset + PLL_CONFIG_CTL,
		config->config_ctl_val);
		@@ -1487,6 +1482,8 @@ static int clk_alpha_pll_slew_update(struct clk_alpha_pll *pll)
		return ret;
		}

		static int clk_alpha_pll_calibrate(struct clk_hw *hw);

		static int clk_alpha_pll_slew_set_rate(struct clk_hw *hw, unsigned long rate,
		unsigned long parent_rate)
		{
		@@ -1495,7 +1492,13 @@ static int clk_alpha_pll_slew_set_rate(struct clk_hw *hw, unsigned long rate,
		const struct pll_vco curr_vco = NULL, vco;
		u32 l, ctl;
		u64 a;
		int i = 0;
		int i = 0, rc;

		if (!clk_hw_is_enabled(hw)) {
		rc = clk_alpha_pll_calibrate(hw);
		if (rc)
		return rc;
		}

		freq_hz = alpha_pll_round_rate(pll, rate, parent_rate, &l, &a);
		if (freq_hz != rate) {
		@@ -1594,7 +1597,6 @@ static int clk_alpha_pll_calibrate(struct clk_hw *hw)
		calibration_freq = (pll->vco_table[0].min_freq +
		pll->vco_table[0].max_freq)/2;


		freq_hz = alpha_pll_round_rate(pll, calibration_freq,
		clk_hw_get_rate(parent), &l, &a);
		if (freq_hz != calibration_freq) {
		@@ -1648,15 +1650,7 @@ static int clk_alpha_pll_calibrate(struct clk_hw *hw)

		static int clk_alpha_pll_slew_enable(struct clk_hw *hw)
		{
		int rc;

		rc = clk_alpha_pll_calibrate(hw);
		if (rc)
		return rc;

		rc = clk_alpha_pll_enable(hw);

		return rc;
		return clk_alpha_pll_enable(hw);
		}

		const struct clk_ops clk_alpha_pll_slew_ops = {

drivers/clk/qcom/clk-rcg.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -161,6 +161,7 @@ extern const struct clk_ops clk_dyn_rcg_ops;
		* @current_freq: last cached frequency when using branches with shared RCGs
		* @enable_safe_config: When set, the RCG is parked at CXO when it's disabled
		* @clkr: regmap clock handle
		* @cfg_off: defines the cfg register offseted from the CMD_RCGR
		* @flags: additional flag parameters for the RCG
		*/
		struct clk_rcg2 {
		@@ -172,6 +173,7 @@ struct clk_rcg2 {
		unsigned long current_freq;
		bool enable_safe_config;
		struct clk_regmap clkr;
		u8 cfg_off;
		u8 flags;
		#define FORCE_ENABLE_RCG BIT(0)
		#define DFS_ENABLE_RCG BIT(1)

drivers/clk/qcom/clk-rcg2.c

+23 −14

Original line number	Diff line number	Diff line
		@@ -92,7 +92,8 @@ static u8 clk_rcg2_get_parent(struct clk_hw *hw)
		u32 cfg;
		int i, ret;

		ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
		ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + rcg->cfg_off +
		CFG_REG, &cfg);
		if (ret)
		goto err;

		@@ -147,13 +148,14 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
		u32 old_cfg;

		/* Read back the old configuration */
		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &old_cfg);
		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + rcg->cfg_off + CFG_REG,
		&old_cfg);

		if (rcg->flags & DFS_ENABLE_RCG)
		return 0;

		ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
		CFG_SRC_SEL_MASK, cfg);
		ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr +
		rcg->cfg_off + CFG_REG, CFG_SRC_SEL_MASK, cfg);
		if (ret)
		return ret;

		@@ -272,13 +274,16 @@ clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
		return rcg->current_freq;
		}

		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + rcg->cfg_off + CFG_REG,
		&cfg);

		if (rcg->mnd_width) {
		mask = BIT(rcg->mnd_width) - 1;
		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG, &m);
		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + rcg->cfg_off +
		M_REG, &m);
		m &= mask;
		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG, &n);
		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + rcg->cfg_off +
		N_REG, &n);
		n = ~n;
		n &= mask;
		n += m;
		@@ -389,22 +394,26 @@ static int clk_rcg2_configure(struct clk_rcg2 rcg, const struct freq_tbl f)
		return index;

		/* Read back the old configuration */
		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &old_cfg);
		regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + rcg->cfg_off + CFG_REG,
		&old_cfg);

		if (rcg->mnd_width && f->n) {
		mask = BIT(rcg->mnd_width) - 1;
		ret = regmap_update_bits(rcg->clkr.regmap,
		rcg->cmd_rcgr + M_REG, mask, f->m);
		rcg->cmd_rcgr + rcg->cfg_off + M_REG,
		mask, f->m);
		if (ret)
		return ret;

		ret = regmap_update_bits(rcg->clkr.regmap,
		rcg->cmd_rcgr + N_REG, mask, ~(f->n - f->m));
		rcg->cmd_rcgr + rcg->cfg_off + N_REG,
		mask, ~(f->n - f->m));
		if (ret)
		return ret;

		ret = regmap_update_bits(rcg->clkr.regmap,
		rcg->cmd_rcgr + D_REG, mask, ~f->n);
		rcg->cmd_rcgr + rcg->cfg_off + D_REG,
		mask, ~f->n);
		if (ret)
		return ret;
		}
		@@ -416,7 +425,7 @@ static int clk_rcg2_configure(struct clk_rcg2 rcg, const struct freq_tbl f)
		if (rcg->mnd_width && f->n && (f->m != f->n))
		cfg \|= CFG_MODE_DUAL_EDGE;
		ret = regmap_update_bits(rcg->clkr.regmap,
		rcg->cmd_rcgr + CFG_REG, mask, cfg);
		rcg->cmd_rcgr + rcg->cfg_off + CFG_REG, mask, cfg);
		if (ret)
		return ret;

		@@ -445,7 +454,7 @@ static void clk_rcg2_list_registers(struct seq_file f, struct clk_hw hw)
		size = ARRAY_SIZE(data1);
		for (i = 0; i < size; i++) {
		regmap_read(rcg->clkr.regmap, (rcg->cmd_rcgr +
		data1[i].offset), &val);
		rcg->cfg_off + data1[i].offset), &val);
		clock_debug_output(f, false, "%20s: 0x%.8x\n",
		data1[i].name, val);
		}
		@@ -453,7 +462,7 @@ static void clk_rcg2_list_registers(struct seq_file f, struct clk_hw hw)
		size = ARRAY_SIZE(data);
		for (i = 0; i < size; i++) {
		regmap_read(rcg->clkr.regmap, (rcg->cmd_rcgr +
		data[i].offset), &val);
		rcg->cfg_off + data[i].offset), &val);
		clock_debug_output(f, false, "%20s: 0x%.8x\n",
		data[i].name, val);
		}

drivers/clk/qcom/gcc-qcs405.c

+32 −21

Original line number	Diff line number	Diff line
		@@ -823,7 +823,7 @@ static struct clk_rcg2 byte0_clk_src = {
		.name = "byte0_clk_src",
		.parent_names = gcc_parent_names_5,
		.num_parents = 4,
		.flags = CLK_GET_RATE_NOCACHE,
		.flags = CLK_SET_RATE_PARENT \| CLK_GET_RATE_NOCACHE,
		.ops = &clk_byte2_ops,
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		@@ -926,17 +926,12 @@ static struct clk_rcg2 gfx3d_clk_src = {
		.hid_width = 5,
		.parent_map = gcc_parent_map_7,
		.freq_tbl = ftbl_gfx3d_clk_src,
		.flags = FORCE_ENABLE_RCG,
		.clkr.hw.init = &(struct clk_init_data){
		.name = "gfx3d_clk_src",
		.parent_names = gcc_parent_names_7,
		.num_parents = 6,
		.ops = &clk_rcg2_ops,
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_LOW] = 270000000,
		[VDD_NOMINAL] = 484800000,
		[VDD_HIGH] = 598000000},
		},
		};

		@@ -1132,7 +1127,7 @@ static struct clk_rcg2 pclk0_clk_src = {
		.name = "pclk0_clk_src",
		.parent_names = gcc_parent_names_12,
		.num_parents = 4,
		.flags = CLK_GET_RATE_NOCACHE,
		.flags = CLK_SET_RATE_PARENT \| CLK_GET_RATE_NOCACHE,
		.ops = &clk_pixel_ops,
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		@@ -2152,8 +2147,8 @@ static struct clk_branch gcc_mdss_mdp_clk = {
		},
		};

		static DEFINE_CLK_VOTER(mdss_mdp_vote_clk, &gcc_mdss_mdp_clk.c, 0);
		static DEFINE_CLK_VOTER(mdss_rotator_vote_clk, &gcc_mdss_mdp_clk.c, 0);
		static DEFINE_CLK_VOTER(mdss_mdp_vote_clk, gcc_mdss_mdp_clk, 0);
		static DEFINE_CLK_VOTER(mdss_rotator_vote_clk, gcc_mdss_mdp_clk, 0);

		static struct clk_branch gcc_mdss_pclk0_clk = {
		.halt_reg = 0x4d084,
		@@ -2218,6 +2213,12 @@ static struct clk_branch gcc_oxili_gfx3d_clk = {
		.num_parents = 1,
		.flags = CLK_SET_RATE_PARENT,
		.ops = &clk_branch2_ops,
		.vdd_class = &vdd_cx,
		.num_rate_max = VDD_NUM,
		.rate_max = (unsigned long[VDD_NUM]) {
		[VDD_LOW] = 270000000,
		[VDD_NOMINAL] = 484800000,
		[VDD_HIGH] = 598000000},
		},
		},
		};
		@@ -2651,8 +2652,7 @@ static struct clk_branch gcc_usb3_phy_aux_clk = {
		};

		static struct clk_branch gcc_usb3_phy_pipe_clk = {
		.halt_reg = 0x39018,
		.halt_check = BRANCH_HALT,
		.halt_check = BRANCH_HALT_SKIP,
		.clkr = {
		.enable_reg = 0x39018,
		.enable_mask = BIT(0),
		@@ -2958,6 +2958,8 @@ static const struct qcom_cc_desc mdss_qcs405_desc = {
		.config = &gcc_qcs405_regmap_config,
		.clks = mdss_qcs405_clocks,
		.num_clks = ARRAY_SIZE(mdss_qcs405_clocks),
		.hwclks = mdss_qcs405_hws,
		.num_hwclks = ARRAY_SIZE(mdss_qcs405_hws),
		};

		static const struct of_device_id mdss_qcs405_match_table[] = {
		@@ -2970,7 +2972,10 @@ MODULE_DEVICE_TABLE(of, mdss_qcs405_match_table);
		static int mdss_qcs405_probe(struct platform_device *pdev)
		{
		struct clk *clk;
		int ret = 0, i;
		struct regmap *regmap;
		struct resource *res;
		void __iomem *base;
		int ret = 0;

		clk = devm_clk_get(&pdev->dev, "pclk0_src");
		if (IS_ERR(clk)) {
		@@ -2986,16 +2991,22 @@ static int mdss_qcs405_probe(struct platform_device *pdev)
		return PTR_ERR(clk);
		}

		/* register hardware clocks */
		for (i = 0; i < ARRAY_SIZE(mdss_qcs405_hws); i++) {
		clk = devm_clk_register(&pdev->dev, mdss_qcs405_hws[i]);
		if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "Unable to register hardware clocks\n");
		return PTR_ERR(clk);
		}
		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		if (res == NULL) {
		dev_err(&pdev->dev, "Failed to get resources\n");
		return -EINVAL;
		}

		ret = qcom_cc_probe(pdev, &mdss_qcs405_desc);
		base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
		if (IS_ERR(base))
		return PTR_ERR(base);

		regmap = devm_regmap_init_mmio(&pdev->dev, base,
		mdss_qcs405_desc.config);
		if (IS_ERR(regmap))
		return PTR_ERR(regmap);

		ret = qcom_cc_really_probe(pdev, &mdss_qcs405_desc, regmap);
		if (ret) {
		dev_err(&pdev->dev, "Failed to register MDSS clocks\n");
		return ret;