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Commit ebc28311 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus 

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] Increase cp0 compare clockevent min_delta_ns from 0x30 to 0x300.
  [MIPS] Cache: Provide more information on cache policy on bootup.
  [MIPS] Fix aliasing bug in copy_user_highpage, take 2.
  [MIPS] VPE loader: convert from struct class_ device to struct device
  [MIPS] MIPSsim: Fix booting from NFS root
  [MIPS] Alchemy: Get rid of au1xxx_irq_map_t.
  [MIPS] Alchemy: Get rid of au_ffz().
  [MIPS] Alchemy: Get rid of au_ffs().
  [MIPS] Alchemy: cleanup interrupt code.
  [MIPS] Lasat: Fix build by conversion to irq_cpu.c.
  [MIPS] Lasat: Add #ifndef ... #endif include warpper to lasatint.h.
  [MIPS] IP22: Enable -Werror.
  [MIPS] IP22: Fix warning.
  [MIPS] IP22: Complain if requesting the front panel irq failed.
  [MIPS] vmlinux.lds.S: Handle KPROBES_TEXT.
  [MIPS] vmlinux.lds.S: Fix handling of .notes in final link.
  [MIPS] vmlinux.lds.S: Remove duplicate comment.
  [MIPS] MSP71XX: Add workarounds file.
  [MIPS] IP32: Fix build by conversion to irq_cpu.c.
parents fc8a327d 8bb00d83

arch/mips/Kconfig

+2 −0
Original line number Diff line number Diff line
@@ -133,6 +133,7 @@ config LASAT 
	select DMA_NONCOHERENT

	select SYS_HAS_EARLY_PRINTK

	select HW_HAS_PCI

	select IRQ_CPU

	select PCI_GT64XXX_PCI0

	select MIPS_NILE4

	select R5000_CPU_SCACHE
@@ -410,6 +411,7 @@ config SGI_IP32 
	select BOOT_ELF32

	select DMA_NONCOHERENT

	select HW_HAS_PCI

	select IRQ_CPU

	select R5000_CPU_SCACHE

	select RM7000_CPU_SCACHE

	select SYS_HAS_CPU_R5000

arch/mips/au1000/common/au1xxx_irqmap.c

+1 −1
Original line number Diff line number Diff line
@@ -54,7 +54,7 @@ 
 * Careful if you change match 2 request!

 * The interrupt handler is called directly from the low level dispatch code.

 */

au1xxx_irq_map_t __initdata au1xxx_ic0_map[] = {

struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = {



#if defined(CONFIG_SOC_AU1000)

	{ AU1000_UART0_INT, INTC_INT_HIGH_LEVEL, 0},

arch/mips/au1000/common/dbdma.c

+1 −1
Original line number Diff line number Diff line
@@ -859,7 +859,7 @@ dbdma_interrupt(int irq, void *dev_id) 


	intstat = dbdma_gptr->ddma_intstat;

	au_sync();

	chan_index = au_ffs(intstat) - 1;

	chan_index = ffs(intstat);



	ctp = chan_tab_ptr[chan_index];

	cp = ctp->chan_ptr;

arch/mips/au1000/common/irq.c

+317 −345
Original line number Diff line number Diff line
@@ -26,39 +26,18 @@ 
 *  with this program; if not, write  to the Free Software Foundation, Inc.,

 *  675 Mass Ave, Cambridge, MA 02139, USA.

 */

#include <linux/errno.h>

#include <linux/bitops.h>

#include <linux/init.h>

#include <linux/irq.h>

#include <linux/kernel_stat.h>

#include <linux/module.h>

#include <linux/signal.h>

#include <linux/sched.h>

#include <linux/types.h>

#include <linux/io.h>

#include <linux/interrupt.h>

#include <linux/ioport.h>

#include <linux/timex.h>

#include <linux/slab.h>

#include <linux/random.h>

#include <linux/delay.h>

#include <linux/bitops.h>

#include <linux/irq.h>



#include <asm/bootinfo.h>

#include <asm/io.h>

#include <asm/mipsregs.h>

#include <asm/system.h>

#include <asm/mach-au1x00/au1000.h>

#ifdef CONFIG_MIPS_PB1000

#include <asm/mach-pb1x00/pb1000.h>

#endif



#undef DEBUG_IRQ

#ifdef DEBUG_IRQ

/* note: prints function name for you */

#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)

#else

#define DPRINTK(fmt, args...)

#endif



#define EXT_INTC0_REQ0 2 /* IP 2 */

#define EXT_INTC0_REQ1 3 /* IP 3 */

#define EXT_INTC1_REQ0 4 /* IP 4 */
@@ -69,14 +48,96 @@ void (*board_init_irq)(void); 


static DEFINE_SPINLOCK(irq_lock);



#ifdef CONFIG_PM



/*

 * Save/restore the interrupt controller state.

 * Called from the save/restore core registers as part of the

 * au_sleep function in power.c.....maybe I should just pm_register()

 * them instead?

 */

static unsigned int	sleep_intctl_config0[2];

static unsigned int	sleep_intctl_config1[2];

static unsigned int	sleep_intctl_config2[2];

static unsigned int	sleep_intctl_src[2];

static unsigned int	sleep_intctl_assign[2];

static unsigned int	sleep_intctl_wake[2];

static unsigned int	sleep_intctl_mask[2];



void save_au1xxx_intctl(void)

{

	sleep_intctl_config0[0] = au_readl(IC0_CFG0RD);

	sleep_intctl_config1[0] = au_readl(IC0_CFG1RD);

	sleep_intctl_config2[0] = au_readl(IC0_CFG2RD);

	sleep_intctl_src[0] = au_readl(IC0_SRCRD);

	sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD);

	sleep_intctl_wake[0] = au_readl(IC0_WAKERD);

	sleep_intctl_mask[0] = au_readl(IC0_MASKRD);



	sleep_intctl_config0[1] = au_readl(IC1_CFG0RD);

	sleep_intctl_config1[1] = au_readl(IC1_CFG1RD);

	sleep_intctl_config2[1] = au_readl(IC1_CFG2RD);

	sleep_intctl_src[1] = au_readl(IC1_SRCRD);

	sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD);

	sleep_intctl_wake[1] = au_readl(IC1_WAKERD);

	sleep_intctl_mask[1] = au_readl(IC1_MASKRD);

}



/*

 * For most restore operations, we clear the entire register and

 * then set the bits we found during the save.

 */

void restore_au1xxx_intctl(void)

{

	au_writel(0xffffffff, IC0_MASKCLR); au_sync();



	au_writel(0xffffffff, IC0_CFG0CLR); au_sync();

	au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync();

	au_writel(0xffffffff, IC0_CFG1CLR); au_sync();

	au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync();

	au_writel(0xffffffff, IC0_CFG2CLR); au_sync();

	au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync();

	au_writel(0xffffffff, IC0_SRCCLR); au_sync();

	au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync();

	au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync();

	au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync();

	au_writel(0xffffffff, IC0_WAKECLR); au_sync();

	au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync();

	au_writel(0xffffffff, IC0_RISINGCLR); au_sync();

	au_writel(0xffffffff, IC0_FALLINGCLR); au_sync();

	au_writel(0x00000000, IC0_TESTBIT); au_sync();



	au_writel(0xffffffff, IC1_MASKCLR); au_sync();



	au_writel(0xffffffff, IC1_CFG0CLR); au_sync();

	au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync();

	au_writel(0xffffffff, IC1_CFG1CLR); au_sync();

	au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync();

	au_writel(0xffffffff, IC1_CFG2CLR); au_sync();

	au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync();

	au_writel(0xffffffff, IC1_SRCCLR); au_sync();

	au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync();

	au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync();

	au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync();

	au_writel(0xffffffff, IC1_WAKECLR); au_sync();

	au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync();

	au_writel(0xffffffff, IC1_RISINGCLR); au_sync();

	au_writel(0xffffffff, IC1_FALLINGCLR); au_sync();

	au_writel(0x00000000, IC1_TESTBIT); au_sync();



	au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync();



	au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync();

}

#endif /* CONFIG_PM */





inline void local_enable_irq(unsigned int irq_nr)

{

	if (irq_nr > AU1000_LAST_INTC0_INT) {

		au_writel(1 << (irq_nr - 32), IC1_MASKSET);

		au_writel(1 << (irq_nr - 32), IC1_WAKESET);

	}

	else {

	} else {

		au_writel(1 << irq_nr, IC0_MASKSET);

		au_writel(1 << irq_nr, IC0_WAKESET);

	}
@@ -89,8 +150,7 @@ inline void local_disable_irq(unsigned int irq_nr) 
	if (irq_nr > AU1000_LAST_INTC0_INT) {

		au_writel(1 << (irq_nr - 32), IC1_MASKCLR);

		au_writel(1 << (irq_nr - 32), IC1_WAKECLR);

	}

	else {

	} else {

		au_writel(1 << irq_nr, IC0_MASKCLR);

		au_writel(1 << irq_nr, IC0_WAKECLR);

	}
@@ -103,8 +163,7 @@ static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr) 
	if (irq_nr > AU1000_LAST_INTC0_INT) {

		au_writel(1 << (irq_nr - 32), IC1_RISINGCLR);

		au_writel(1 << (irq_nr - 32), IC1_MASKCLR);

	}

	else {

	} else {

		au_writel(1 << irq_nr, IC0_RISINGCLR);

		au_writel(1 << irq_nr, IC0_MASKCLR);

	}
@@ -117,8 +176,7 @@ static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr) 
	if (irq_nr > AU1000_LAST_INTC0_INT) {

		au_writel(1 << (irq_nr - 32), IC1_FALLINGCLR);

		au_writel(1 << (irq_nr - 32), IC1_MASKCLR);

	}

	else {

	} else {

		au_writel(1 << irq_nr, IC0_FALLINGCLR);

		au_writel(1 << irq_nr, IC0_MASKCLR);

	}
@@ -135,8 +193,7 @@ static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr) 
		au_writel(1 << (irq_nr - 32), IC1_FALLINGCLR);

		au_writel(1 << (irq_nr - 32), IC1_RISINGCLR);

		au_writel(1 << (irq_nr - 32), IC1_MASKCLR);

	}

	else {

	} else {

		au_writel(1 << irq_nr, IC0_FALLINGCLR);

		au_writel(1 << irq_nr, IC0_RISINGCLR);

		au_writel(1 << irq_nr, IC0_MASKCLR);
@@ -162,9 +219,9 @@ static inline void mask_and_ack_level_irq(unsigned int irq_nr) 


static void end_irq(unsigned int irq_nr)

{

	if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {

	if (!(irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS)))

		local_enable_irq(irq_nr);

	}



#if defined(CONFIG_MIPS_PB1000)

	if (irq_nr == AU1000_GPIO_15) {

		au_writel(0x4000, PB1000_MDR); /* enable int */
@@ -181,16 +238,13 @@ unsigned long save_local_and_disable(int controller) 
	spin_lock_irqsave(&irq_lock, flags);

	if (controller) {

		mask = au_readl(IC1_MASKSET);

		for (i=32; i<64; i++) {

		for (i = 32; i < 64; i++)

			local_disable_irq(i);

		}

	}

	else {

	} else {

		mask = au_readl(IC0_MASKSET);

		for (i=0; i<32; i++) {

		for (i = 0; i < 32; i++)

			local_disable_irq(i);

	}

	}

	spin_unlock_irqrestore(&irq_lock, flags);



	return mask;
@@ -263,7 +317,8 @@ void startup_match20_interrupt(irq_handler_t handler) 
	static struct irqaction action;

	memset(&action, 0, sizeof(struct irqaction));



	/* This is a big problem.... since we didn't use request_irq

	/*

	 * This is a big problem.... since we didn't use request_irq

	 * when kernel/irq.c calls probe_irq_xxx this interrupt will

	 * be probed for usage. This will end up disabling the device :(

	 * Give it a bogus "action" pointer -- this will keep it from
@@ -328,7 +383,8 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req) 
			au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);

			break;

		default: /* disable the interrupt */

				printk("unexpected int type %d (irq %d)\n", type, irq_nr);

			printk(KERN_WARNING "unexpected int type %d (irq %d)\n",

			       type, irq_nr);

			au_writel(1 << (irq_nr - 32), IC1_CFG0CLR);

			au_writel(1 << (irq_nr - 32), IC1_CFG1CLR);

			au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
@@ -341,8 +397,7 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req) 
		au_writel(1 << (irq_nr - 32), IC1_SRCSET);

		au_writel(1 << (irq_nr - 32), IC1_MASKCLR);

		au_writel(1 << (irq_nr - 32), IC1_WAKECLR);

	}

	else {

	} else {

		switch (type) {

		case INTC_INT_RISE_EDGE: /* 0:0:1 */

			au_writel(1 << irq_nr, IC0_CFG2CLR);
@@ -380,7 +435,8 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req) 
			au_writel(1 << irq_nr, IC0_CFG2CLR);

			break;

		default: /* disable the interrupt */

				printk("unexpected int type %d (irq %d)\n", type, irq_nr);

			printk(KERN_WARNING "unexpected int type %d (irq %d)\n",

			       type, irq_nr);

			au_writel(1 << irq_nr, IC0_CFG0CLR);

			au_writel(1 << irq_nr, IC0_CFG1CLR);

			au_writel(1 << irq_nr, IC0_CFG2CLR);
@@ -397,68 +453,6 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req) 
	au_sync();

}





void __init arch_init_irq(void)

{

	int i;

	unsigned long cp0_status;

	au1xxx_irq_map_t *imp;

	extern au1xxx_irq_map_t au1xxx_irq_map[];

	extern au1xxx_irq_map_t au1xxx_ic0_map[];

	extern int au1xxx_nr_irqs;

	extern int au1xxx_ic0_nr_irqs;



	cp0_status = read_c0_status();



	/* Initialize interrupt controllers to a safe state.

	*/

	au_writel(0xffffffff, IC0_CFG0CLR);

	au_writel(0xffffffff, IC0_CFG1CLR);

	au_writel(0xffffffff, IC0_CFG2CLR);

	au_writel(0xffffffff, IC0_MASKCLR);

	au_writel(0xffffffff, IC0_ASSIGNSET);

	au_writel(0xffffffff, IC0_WAKECLR);

	au_writel(0xffffffff, IC0_SRCSET);

	au_writel(0xffffffff, IC0_FALLINGCLR);

	au_writel(0xffffffff, IC0_RISINGCLR);

	au_writel(0x00000000, IC0_TESTBIT);



	au_writel(0xffffffff, IC1_CFG0CLR);

	au_writel(0xffffffff, IC1_CFG1CLR);

	au_writel(0xffffffff, IC1_CFG2CLR);

	au_writel(0xffffffff, IC1_MASKCLR);

	au_writel(0xffffffff, IC1_ASSIGNSET);

	au_writel(0xffffffff, IC1_WAKECLR);

	au_writel(0xffffffff, IC1_SRCSET);

	au_writel(0xffffffff, IC1_FALLINGCLR);

	au_writel(0xffffffff, IC1_RISINGCLR);

	au_writel(0x00000000, IC1_TESTBIT);



	/* Initialize IC0, which is fixed per processor.

	*/

	imp = au1xxx_ic0_map;

	for (i=0; i<au1xxx_ic0_nr_irqs; i++) {

		setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);

		imp++;

	}



	/* Now set up the irq mapping for the board.

	*/

	imp = au1xxx_irq_map;

	for (i=0; i<au1xxx_nr_irqs; i++) {

		setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);

		imp++;

	}



	set_c0_status(ALLINTS);



	/* Board specific IRQ initialization.

	*/

	if (board_init_irq)

		(*board_init_irq)();

}





/*

 * Interrupts are nested. Even if an interrupt handler is registered

 * as "fast", we might get another interrupt before we return from
@@ -468,12 +462,13 @@ void __init arch_init_irq(void) 
static void intc0_req0_irqdispatch(void)

{

	int irq = 0;

	static unsigned long intc0_req0 = 0;

	static unsigned long intc0_req0;



	intc0_req0 |= au_readl(IC0_REQ0INT);



	if (!intc0_req0)

		return;



#ifdef AU1000_USB_DEV_REQ_INT

	/*

	 * Because of the tight timing of SETUP token to reply
@@ -486,7 +481,7 @@ static void intc0_req0_irqdispatch(void) 
		return;

	}

#endif

	irq = au_ffs(intc0_req0) - 1;

	irq = ffs(intc0_req0);

	intc0_req0 &= ~(1 << irq);

	do_IRQ(irq);

}
@@ -495,14 +490,14 @@ static void intc0_req0_irqdispatch(void) 
static void intc0_req1_irqdispatch(void)

{

	int irq = 0;

	static unsigned long intc0_req1 = 0;

	static unsigned long intc0_req1;



	intc0_req1 |= au_readl(IC0_REQ1INT);



	if (!intc0_req1)

		return;



	irq = au_ffs(intc0_req1) - 1;

	irq = ffs(intc0_req1);

	intc0_req1 &= ~(1 << irq);

	do_IRQ(irq);

}
@@ -515,14 +510,14 @@ static void intc0_req1_irqdispatch(void) 
static void intc1_req0_irqdispatch(void)

{

	int irq = 0;

	static unsigned long intc1_req0 = 0;

	static unsigned long intc1_req0;



	intc1_req0 |= au_readl(IC1_REQ0INT);



	if (!intc1_req0)

		return;



	irq = au_ffs(intc1_req0) - 1;

	irq = ffs(intc1_req0);

	intc1_req0 &= ~(1 << irq);

	irq += 32;

	do_IRQ(irq);
@@ -532,102 +527,19 @@ static void intc1_req0_irqdispatch(void) 
static void intc1_req1_irqdispatch(void)

{

	int irq = 0;

	static unsigned long intc1_req1 = 0;

	static unsigned long intc1_req1;



	intc1_req1 |= au_readl(IC1_REQ1INT);



	if (!intc1_req1)

		return;



	irq = au_ffs(intc1_req1) - 1;

	irq = ffs(intc1_req1);

	intc1_req1 &= ~(1 << irq);

	irq += 32;

	do_IRQ(irq);

}



#ifdef CONFIG_PM



/* Save/restore the interrupt controller state.

 * Called from the save/restore core registers as part of the

 * au_sleep function in power.c.....maybe I should just pm_register()

 * them instead?

 */

static unsigned int	sleep_intctl_config0[2];

static unsigned int	sleep_intctl_config1[2];

static unsigned int	sleep_intctl_config2[2];

static unsigned int	sleep_intctl_src[2];

static unsigned int	sleep_intctl_assign[2];

static unsigned int	sleep_intctl_wake[2];

static unsigned int	sleep_intctl_mask[2];



void

save_au1xxx_intctl(void)

{

	sleep_intctl_config0[0] = au_readl(IC0_CFG0RD);

	sleep_intctl_config1[0] = au_readl(IC0_CFG1RD);

	sleep_intctl_config2[0] = au_readl(IC0_CFG2RD);

	sleep_intctl_src[0] = au_readl(IC0_SRCRD);

	sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD);

	sleep_intctl_wake[0] = au_readl(IC0_WAKERD);

	sleep_intctl_mask[0] = au_readl(IC0_MASKRD);



	sleep_intctl_config0[1] = au_readl(IC1_CFG0RD);

	sleep_intctl_config1[1] = au_readl(IC1_CFG1RD);

	sleep_intctl_config2[1] = au_readl(IC1_CFG2RD);

	sleep_intctl_src[1] = au_readl(IC1_SRCRD);

	sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD);

	sleep_intctl_wake[1] = au_readl(IC1_WAKERD);

	sleep_intctl_mask[1] = au_readl(IC1_MASKRD);

}



/* For most restore operations, we clear the entire register and

 * then set the bits we found during the save.

 */

void

restore_au1xxx_intctl(void)

{

	au_writel(0xffffffff, IC0_MASKCLR); au_sync();



	au_writel(0xffffffff, IC0_CFG0CLR); au_sync();

	au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync();

	au_writel(0xffffffff, IC0_CFG1CLR); au_sync();

	au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync();

	au_writel(0xffffffff, IC0_CFG2CLR); au_sync();

	au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync();

	au_writel(0xffffffff, IC0_SRCCLR); au_sync();

	au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync();

	au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync();

	au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync();

	au_writel(0xffffffff, IC0_WAKECLR); au_sync();

	au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync();

	au_writel(0xffffffff, IC0_RISINGCLR); au_sync();

	au_writel(0xffffffff, IC0_FALLINGCLR); au_sync();

	au_writel(0x00000000, IC0_TESTBIT); au_sync();



	au_writel(0xffffffff, IC1_MASKCLR); au_sync();



	au_writel(0xffffffff, IC1_CFG0CLR); au_sync();

	au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync();

	au_writel(0xffffffff, IC1_CFG1CLR); au_sync();

	au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync();

	au_writel(0xffffffff, IC1_CFG2CLR); au_sync();

	au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync();

	au_writel(0xffffffff, IC1_SRCCLR); au_sync();

	au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync();

	au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync();

	au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync();

	au_writel(0xffffffff, IC1_WAKECLR); au_sync();

	au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync();

	au_writel(0xffffffff, IC1_RISINGCLR); au_sync();

	au_writel(0xffffffff, IC1_FALLINGCLR); au_sync();

	au_writel(0x00000000, IC1_TESTBIT); au_sync();



	au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync();



	au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync();

}

#endif /* CONFIG_PM */



asmlinkage void plat_irq_dispatch(void)

{

	unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
@@ -645,3 +557,63 @@ asmlinkage void plat_irq_dispatch(void) 
	else

		spurious_interrupt();

}



void __init arch_init_irq(void)

{

	int i;

	unsigned long cp0_status;

	struct au1xxx_irqmap *imp;

	extern struct au1xxx_irqmap au1xxx_irq_map[];

	extern struct au1xxx_irqmap au1xxx_ic0_map[];

	extern int au1xxx_nr_irqs;

	extern int au1xxx_ic0_nr_irqs;



	cp0_status = read_c0_status();



	/* Initialize interrupt controllers to a safe state.

	*/

	au_writel(0xffffffff, IC0_CFG0CLR);

	au_writel(0xffffffff, IC0_CFG1CLR);

	au_writel(0xffffffff, IC0_CFG2CLR);

	au_writel(0xffffffff, IC0_MASKCLR);

	au_writel(0xffffffff, IC0_ASSIGNSET);

	au_writel(0xffffffff, IC0_WAKECLR);

	au_writel(0xffffffff, IC0_SRCSET);

	au_writel(0xffffffff, IC0_FALLINGCLR);

	au_writel(0xffffffff, IC0_RISINGCLR);

	au_writel(0x00000000, IC0_TESTBIT);



	au_writel(0xffffffff, IC1_CFG0CLR);

	au_writel(0xffffffff, IC1_CFG1CLR);

	au_writel(0xffffffff, IC1_CFG2CLR);

	au_writel(0xffffffff, IC1_MASKCLR);

	au_writel(0xffffffff, IC1_ASSIGNSET);

	au_writel(0xffffffff, IC1_WAKECLR);

	au_writel(0xffffffff, IC1_SRCSET);

	au_writel(0xffffffff, IC1_FALLINGCLR);

	au_writel(0xffffffff, IC1_RISINGCLR);

	au_writel(0x00000000, IC1_TESTBIT);



	/* Initialize IC0, which is fixed per processor.

	*/

	imp = au1xxx_ic0_map;

	for (i = 0; i < au1xxx_ic0_nr_irqs; i++) {

		setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);

		imp++;

	}



	/* Now set up the irq mapping for the board.

	*/

	imp = au1xxx_irq_map;

	for (i = 0; i < au1xxx_nr_irqs; i++) {

		setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);

		imp++;

	}



	set_c0_status(ALLINTS);



	/* Board specific IRQ initialization.

	*/

	if (board_init_irq)

		(*board_init_irq)();

}

arch/mips/au1000/db1x00/irqmap.c

+1 −1
Original line number Diff line number Diff line
@@ -79,7 +79,7 @@ char irq_tab_alchemy[][5] __initdata = { 
#endif





au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {

struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {



#ifndef CONFIG_MIPS_MIRAGE

#ifdef CONFIG_MIPS_DB1550