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Commit ebad6b94 authored by Alexander Usyskin's avatar Alexander Usyskin Committed by Greg Kroah-Hartman
Browse files

mei: me: d0i3: move mei_me_hw_reset down in the file 



Move mei_me_hw_reset down in the source file to avoid
forward declarations when introducing d0i3 flow in the next patch.

Signed-off-by: default avatarAlexander Usyskin <alexander.usyskin@intel.com>
Signed-off-by: default avatarTomas Winkler <tomas.winkler@intel.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 859ef2ff

drivers/misc/mei/hw-me.c

+52 −51
Original line number Diff line number Diff line
@@ -290,57 +290,6 @@ static void mei_me_hw_reset_release(struct mei_device *dev) 
	/* complete this write before we set host ready on another CPU */

	mmiowb();

}

/**

 * mei_me_hw_reset - resets fw via mei csr register.

 *

 * @dev: the device structure

 * @intr_enable: if interrupt should be enabled after reset.

 *

 * Return: always 0

 */

static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)

{

	u32 hcsr = mei_hcsr_read(dev);



	/* H_RST may be found lit before reset is started,

	 * for example if preceding reset flow hasn't completed.

	 * In that case asserting H_RST will be ignored, therefore

	 * we need to clean H_RST bit to start a successful reset sequence.

	 */

	if ((hcsr & H_RST) == H_RST) {

		dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr);

		hcsr &= ~H_RST;

		mei_hcsr_set(dev, hcsr);

		hcsr = mei_hcsr_read(dev);

	}



	hcsr |= H_RST | H_IG | H_CSR_IS_MASK;



	if (intr_enable)

		hcsr |= H_CSR_IE_MASK;

	else

		hcsr &= ~H_CSR_IE_MASK;



	dev->recvd_hw_ready = false;

	mei_hcsr_write(dev, hcsr);



	/*

	 * Host reads the H_CSR once to ensure that the

	 * posted write to H_CSR completes.

	 */

	hcsr = mei_hcsr_read(dev);



	if ((hcsr & H_RST) == 0)

		dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr);



	if ((hcsr & H_RDY) == H_RDY)

		dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr);



	if (intr_enable == false)

		mei_me_hw_reset_release(dev);



	return 0;

}



/**

 * mei_me_host_set_ready - enable device
@@ -1082,6 +1031,58 @@ int mei_me_pg_exit_sync(struct mei_device *dev) 
		return mei_me_pg_legacy_exit_sync(dev);

}



/**

 * mei_me_hw_reset - resets fw via mei csr register.

 *

 * @dev: the device structure

 * @intr_enable: if interrupt should be enabled after reset.

 *

 * Return: always 0

 */

static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)

{

	u32 hcsr = mei_hcsr_read(dev);



	/* H_RST may be found lit before reset is started,

	 * for example if preceding reset flow hasn't completed.

	 * In that case asserting H_RST will be ignored, therefore

	 * we need to clean H_RST bit to start a successful reset sequence.

	 */

	if ((hcsr & H_RST) == H_RST) {

		dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr);

		hcsr &= ~H_RST;

		mei_hcsr_set(dev, hcsr);

		hcsr = mei_hcsr_read(dev);

	}



	hcsr |= H_RST | H_IG | H_CSR_IS_MASK;



	if (intr_enable)

		hcsr |= H_CSR_IE_MASK;

	else

		hcsr &= ~H_CSR_IE_MASK;



	dev->recvd_hw_ready = false;

	mei_hcsr_write(dev, hcsr);



	/*

	 * Host reads the H_CSR once to ensure that the

	 * posted write to H_CSR completes.

	 */

	hcsr = mei_hcsr_read(dev);



	if ((hcsr & H_RST) == 0)

		dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr);



	if ((hcsr & H_RDY) == H_RDY)

		dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr);



	if (intr_enable == false)

		mei_me_hw_reset_release(dev);



	return 0;

}



/**

 * mei_me_irq_quick_handler - The ISR of the MEI device

 *