Merge "clk: qcom: Add support for gcc_usb2 ref clocks" (ebaa2888) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/clk/qcom/gcc-sm6150.c

+42 −0

Original line number	Diff line number	Diff line
		@@ -3146,6 +3146,45 @@ static struct clk_branch gcc_wcss_vs_clk = {
		},
		};

		static struct clk_branch gcc_rx1_usb2_clkref_clk = {
		.halt_reg = 0x8c030,
		.halt_check = BRANCH_HALT_VOTED,
		.clkr = {
		.enable_reg = 0x8c030,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_rx1_usb2_clkref_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_usb2_prim_clkref_clk = {
		.halt_reg = 0x8c028,
		.halt_check = BRANCH_HALT_VOTED,
		.clkr = {
		.enable_reg = 0x8c028,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_usb2_prim_clkref_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_usb2_sec_clkref_clk = {
		.halt_reg = 0x8c018,
		.halt_check = BRANCH_HALT_VOTED,
		.clkr = {
		.enable_reg = 0x8c018,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_usb2_sec_clkref_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		/* Measure-only clock for ddrss_gcc_debug_clk. */
		static struct clk_dummy measure_only_bimc_clk = {
		.rrate = 1000,
		@@ -3362,6 +3401,9 @@ static struct clk_regmap *gcc_sm6150_clocks[] = {
		[GPLL6_OUT_MAIN] = &gpll6_out_main.clkr,
		[GPLL7_OUT_MAIN] = &gpll7_out_main.clkr,
		[GPLL8_OUT_MAIN] = &gpll8_out_main.clkr,
		[GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
		[GCC_USB2_PRIM_CLKREF_CLK] = &gcc_usb2_prim_clkref_clk.clkr,
		[GCC_USB2_SEC_CLKREF_CLK] = &gcc_usb2_sec_clkref_clk.clkr,
		};

		static const struct qcom_reset_map gcc_sm6150_resets[] = {

+3 −0

Original line number	Diff line number	Diff line
		@@ -187,6 +187,9 @@
		#define GCC_CPUSS_GNOC_CLK 167
		#define GCC_DISP_XO_CLK 168
		#define GCC_VIDEO_XO_CLK 169
		#define GCC_RX1_USB2_CLKREF_CLK 170
		#define GCC_USB2_PRIM_CLKREF_CLK 171
		#define GCC_USB2_SEC_CLKREF_CLK 172

		/* GCC Resets */
		#define GCC_QUSB2PHY_PRIM_BCR 0