Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit eb14cb74 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
Browse files

drm/i915: Add state readout and checking for has_dp_encoder and dp_m_n 



Add functions to read out the CPU and PCH transcoder M/N values,
and use them to fill out the pipe config dp_m_n information. And
while at it populate has_dp_encoder too.

Also refactor ironlake_get_fdi_m_n_config() to simply call the new
intel_cpu_transcoder_get_m_n() function.

v2: Remember the DDI

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 42571aef

drivers/gpu/drm/i915/intel_ddi.c

+14 −0
Original line number Diff line number Diff line
@@ -1285,6 +1285,20 @@ static void intel_ddi_get_config(struct intel_encoder *encoder, 
	default:

		break;

	}



	switch (temp & TRANS_DDI_MODE_SELECT_MASK) {

	case TRANS_DDI_MODE_SELECT_HDMI:

	case TRANS_DDI_MODE_SELECT_DVI:

	case TRANS_DDI_MODE_SELECT_FDI:

		break;

	case TRANS_DDI_MODE_SELECT_DP_SST:

	case TRANS_DDI_MODE_SELECT_DP_MST:

		pipe_config->has_dp_encoder = true;

		intel_dp_get_m_n(intel_crtc, pipe_config);

		break;

	default:

		break;

	}

}



static void intel_ddi_destroy(struct drm_encoder *encoder)

drivers/gpu/drm/i915/intel_display.c

+66 −10
Original line number Diff line number Diff line
@@ -5858,22 +5858,66 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 
	return ret;

}



static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,

					struct intel_crtc_config *pipe_config)

static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,

					 struct intel_link_m_n *m_n)

{

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	enum transcoder transcoder = pipe_config->cpu_transcoder;

	enum pipe pipe = crtc->pipe;



	pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));

	pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));

	pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))

	m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));

	m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));

	m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))

		& ~TU_SIZE_MASK;

	pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));

	pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))

	m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));

	m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))

		    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;

}



static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,

					 enum transcoder transcoder,

					 struct intel_link_m_n *m_n)

{

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;

	enum pipe pipe = crtc->pipe;



	if (INTEL_INFO(dev)->gen >= 5) {

		m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));

		m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));

		m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))

			& ~TU_SIZE_MASK;

		m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));

		m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))

			    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;

	} else {

		m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));

		m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));

		m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))

			& ~TU_SIZE_MASK;

		m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));

		m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))

			    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;

	}

}



void intel_dp_get_m_n(struct intel_crtc *crtc,

		      struct intel_crtc_config *pipe_config)

{

	if (crtc->config.has_pch_encoder)

		intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);

	else

		intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,

					     &pipe_config->dp_m_n);

}



static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,

					struct intel_crtc_config *pipe_config)

{

	intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,

				     &pipe_config->fdi_m_n);

}



static void ironlake_get_pfit_config(struct intel_crtc *crtc,

				     struct intel_crtc_config *pipe_config)

{
@@ -8239,6 +8283,11 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, 
		      pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,

		      pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,

		      pipe_config->fdi_m_n.tu);

	DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",

		      pipe_config->has_dp_encoder,

		      pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,

		      pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,

		      pipe_config->dp_m_n.tu);

	DRM_DEBUG_KMS("requested mode:\n");

	drm_mode_debug_printmodeline(&pipe_config->requested_mode);

	DRM_DEBUG_KMS("adjusted mode:\n");
@@ -8608,6 +8657,13 @@ intel_pipe_config_compare(struct drm_device *dev, 
	PIPE_CONF_CHECK_I(fdi_m_n.link_n);

	PIPE_CONF_CHECK_I(fdi_m_n.tu);



	PIPE_CONF_CHECK_I(has_dp_encoder);

	PIPE_CONF_CHECK_I(dp_m_n.gmch_m);

	PIPE_CONF_CHECK_I(dp_m_n.gmch_n);

	PIPE_CONF_CHECK_I(dp_m_n.link_m);

	PIPE_CONF_CHECK_I(dp_m_n.link_n);

	PIPE_CONF_CHECK_I(dp_m_n.tu);



	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);

	PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);

	PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);

drivers/gpu/drm/i915/intel_dp.c

+4 −0
Original line number Diff line number Diff line
@@ -1444,6 +1444,10 @@ static void intel_dp_get_config(struct intel_encoder *encoder, 


	pipe_config->adjusted_mode.flags |= flags;



	pipe_config->has_dp_encoder = true;



	intel_dp_get_m_n(crtc, pipe_config);



	if (dp_to_dig_port(intel_dp)->port == PORT_A) {

		if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)

			pipe_config->port_clock = 162000;

drivers/gpu/drm/i915/intel_drv.h

+2 −0
Original line number Diff line number Diff line
@@ -801,5 +801,7 @@ extern void hsw_pc8_disable_interrupts(struct drm_device *dev); 
extern void hsw_pc8_restore_interrupts(struct drm_device *dev);

extern void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv);

extern void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);

extern void intel_dp_get_m_n(struct intel_crtc *crtc,

			     struct intel_crtc_config *pipe_config);



#endif /* __INTEL_DRV_H__ */