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Commit eaffcb0f authored by Emil Medve's avatar Emil Medve Committed by Scott Wood
Browse files

powerpc/dts: Factorize the clock control node 



Signed-off-by: default avatarEmil Medve <Emilian.Medve@Freescale.com>
Change-Id: I25ce24a25862b4ca460164159867abefe00ccdd1
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
parent 94701fcb

arch/powerpc/boot/dts/b4860emu.dts

+2 −2
Original line number Diff line number Diff line
@@ -193,9 +193,9 @@ 
		fsl,liodn-bits = <12>;

	};



	clockgen: global-utilities@e1000 {

/include/ "fsl/qoriq-clockgen2.dtsi"

	global-utilities@e1000 {

		compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";

		reg = <0xe1000 0x1000>;

	};



/include/ "fsl/qoriq-dma-0.dtsi"

arch/powerpc/boot/dts/fsl/b4420si-post.dtsi

+2 −26
Original line number Diff line number Diff line
@@ -80,33 +80,9 @@ 
		compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";

	};



	clockgen: global-utilities@e1000 {

/include/ "qoriq-clockgen2.dtsi"

	global-utilities@e1000 {

		compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";

		ranges = <0x0 0xe1000 0x1000>;

		#address-cells = <1>;

		#size-cells = <1>;



		sysclk: sysclk {

			#clock-cells = <0>;

			compatible = "fsl,qoriq-sysclk-2.0";

			clock-output-names = "sysclk";

		};



		pll0: pll0@800 {

			#clock-cells = <1>;

			reg = <0x800 0x4>;

			compatible = "fsl,qoriq-core-pll-2.0";

			clocks = <&sysclk>;

			clock-output-names = "pll0", "pll0-div2", "pll0-div4";

		};



		pll1: pll1@820 {

			#clock-cells = <1>;

			reg = <0x820 0x4>;

			compatible = "fsl,qoriq-core-pll-2.0";

			clocks = <&sysclk>;

			clock-output-names = "pll1", "pll1-div2", "pll1-div4";

		};



		mux0: mux0@0 {

			#clock-cells = <0>;

arch/powerpc/boot/dts/fsl/b4860si-post.dtsi

+2 −26
Original line number Diff line number Diff line
@@ -124,33 +124,9 @@ 
		compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0";

	};



	clockgen: global-utilities@e1000 {

/include/ "qoriq-clockgen2.dtsi"

	global-utilities@e1000 {

		compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0";

		ranges = <0x0 0xe1000 0x1000>;

		#address-cells = <1>;

		#size-cells = <1>;



		sysclk: sysclk {

			#clock-cells = <0>;

			compatible = "fsl,qoriq-sysclk-2.0";

			clock-output-names = "sysclk";

		};



		pll0: pll0@800 {

			#clock-cells = <1>;

			reg = <0x800 0x4>;

			compatible = "fsl,qoriq-core-pll-2.0";

			clocks = <&sysclk>;

			clock-output-names = "pll0", "pll0-div2", "pll0-div4";

		};



		pll1: pll1@820 {

			#clock-cells = <1>;

			reg = <0x820 0x4>;

			compatible = "fsl,qoriq-core-pll-2.0";

			clocks = <&sysclk>;

			clock-output-names = "pll1", "pll1-div2", "pll1-div4";

		};



		mux0: mux0@0 {

			#clock-cells = <0>;

arch/powerpc/boot/dts/fsl/p2041si-post.dtsi

+2 −46
Original line number Diff line number Diff line
@@ -305,53 +305,9 @@ 
		#sleep-cells = <2>;

	};



	clockgen: global-utilities@e1000 {

/include/ "qoriq-clockgen1.dtsi"

	global-utilities@e1000 {

		compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";

		ranges = <0x0 0xe1000 0x1000>;

		reg = <0xe1000 0x1000>;

		clock-frequency = <0>;

		#address-cells = <1>;

		#size-cells = <1>;



		sysclk: sysclk {

			#clock-cells = <0>;

			compatible = "fsl,qoriq-sysclk-1.0";

			clock-output-names = "sysclk";

		};



		pll0: pll0@800 {

			#clock-cells = <1>;

			reg = <0x800 0x4>;

			compatible = "fsl,qoriq-core-pll-1.0";

			clocks = <&sysclk>;

			clock-output-names = "pll0", "pll0-div2";

		};



		pll1: pll1@820 {

			#clock-cells = <1>;

			reg = <0x820 0x4>;

			compatible = "fsl,qoriq-core-pll-1.0";

			clocks = <&sysclk>;

			clock-output-names = "pll1", "pll1-div2";

		};



		mux0: mux0@0 {

			#clock-cells = <0>;

			reg = <0x0 0x4>;

			compatible = "fsl,qoriq-core-mux-1.0";

			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;

			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";

			clock-output-names = "cmux0";

		};



		mux1: mux1@20 {

			#clock-cells = <0>;

			reg = <0x20 0x4>;

			compatible = "fsl,qoriq-core-mux-1.0";

			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;

			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";

			clock-output-names = "cmux1";

		};



		mux2: mux2@40 {

			#clock-cells = <0>;

arch/powerpc/boot/dts/fsl/p3041si-post.dtsi

+2 −46
Original line number Diff line number Diff line
@@ -332,53 +332,9 @@ 
		#sleep-cells = <2>;

	};



	clockgen: global-utilities@e1000 {

/include/ "qoriq-clockgen1.dtsi"

	global-utilities@e1000 {

		compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";

		ranges = <0x0 0xe1000 0x1000>;

		reg = <0xe1000 0x1000>;

		clock-frequency = <0>;

		#address-cells = <1>;

		#size-cells = <1>;



		sysclk: sysclk {

			#clock-cells = <0>;

			compatible = "fsl,qoriq-sysclk-1.0";

			clock-output-names = "sysclk";

		};



		pll0: pll0@800 {

			#clock-cells = <1>;

			reg = <0x800 0x4>;

			compatible = "fsl,qoriq-core-pll-1.0";

			clocks = <&sysclk>;

			clock-output-names = "pll0", "pll0-div2";

		};



		pll1: pll1@820 {

			#clock-cells = <1>;

			reg = <0x820 0x4>;

			compatible = "fsl,qoriq-core-pll-1.0";

			clocks = <&sysclk>;

			clock-output-names = "pll1", "pll1-div2";

		};



		mux0: mux0@0 {

			#clock-cells = <0>;

			reg = <0x0 0x4>;

			compatible = "fsl,qoriq-core-mux-1.0";

			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;

			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";

			clock-output-names = "cmux0";

		};



		mux1: mux1@20 {

			#clock-cells = <0>;

			reg = <0x20 0x4>;

			compatible = "fsl,qoriq-core-mux-1.0";

			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;

			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";

			clock-output-names = "cmux1";

		};



		mux2: mux2@40 {

			#clock-cells = <0>;