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Commit eae75cff authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
Browse files

Merge "usb: configfs: Set USB gadget speed as super speed plus"

parents eca4db7f 51f8475a

arch/arm64/boot/dts/qcom/sm8150-usb.dtsi

+36 −36
Original line number Diff line number Diff line
@@ -152,7 +152,6 @@ 
		     USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xde 0

		     USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0

		     USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a 0

		     USB3_DP_QSERDES_COM_CMN_IPTRIM 0x14 0

		     USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0

		     USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06 0

		     USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
@@ -173,22 +172,23 @@ 
		     USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xab 0

		     USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xea 0

		     USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0

		     USB3_DP_QSERDES_COM_VCO_TUNE_CTRL 0x00 0

		     USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02 0

		     USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0

		     USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0

		     USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0

		     USB3_DP_QSERDES_COM_HSCLK_SEL 0x01 0

		     USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0

		     USB3_DP_QSERDES_COM_SVS_MODE_CLK_SEL 0x5 0

		     USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xca 0

		     USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1e 0

		     USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca 0

		     USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e 0

		     USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0

		     USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0xd4 0

		     USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0xd0 0

		     USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02 0

		     USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20 0

		     USB3_DP_QSERDES_TXA_LANE_MODE_1 0x05 0

		     USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0

		     USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0xe4 0

		     USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0xd0 0

		     USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x04 0

		     USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2f 0

		     USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0
@@ -199,32 +199,34 @@ 
		     USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08 0

		     USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x05 0

		     USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x05 0

		     USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0f 0

		     USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54 0

		     USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x08 0

		     USB3_DP_QSERDES_RXA_GM_CAL 0x1f 0

		     USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0f 0

		     USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4a 0

		     USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x08 0

		     USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0a 0

		     USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xc0 0

		     USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00 0

		     USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0

		     USB3_DP_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0

		     USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0

		     USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0e 0

		     USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0x36 0

		     USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x36 0

		     USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xb6 0

		     USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x17 0

		     USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x7c 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xfc 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0xfc 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0xff 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x23 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0x34 0

		     USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0x3f 0

		     USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0xbf 0

		     USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x3f 0

		     USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x3f 0

		     USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x8a 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xdc 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0xdc 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x5c 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x0b 0

		     USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xb3 0

		     USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0

		     USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x30 0

		     USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0xd4 0

		     USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0xd0 0

		     USB3_DP_QSERDES_TXB_LANE_MODE_1 0x05 0

		     USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0

		     USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0xe4 0

		     USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0xd0 0

		     USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x04 0

		     USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2f 0

		     USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0
@@ -235,26 +237,28 @@ 
		     USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08 0

		     USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x05 0

		     USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x05 0

		     USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0f 0

		     USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54 0

		     USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x08 0

		     USB3_DP_QSERDES_RXB_GM_CAL 0x1f 0

		     USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0f 0

		     USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4a 0

		     USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x08 0

		     USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0a 0

		     USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xc0 0

		     USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00 0

		     USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0

		     USB3_DP_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0

		     USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0

		     USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0e 0

		     USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x36 0

		     USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x36 0

		     USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xb6 0

		     USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x17 0

		     USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0x7c 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xfc 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0xfc 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0xff 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x23 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0x34 0

		     USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x3f 0

		     USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xbf 0

		     USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x3f 0

		     USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x3f 0

		     USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0x8a 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xdc 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0xdc 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x5c 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x0b 0

		     USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xb3 0

		     USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0

		     USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x30 0

		     USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xd0 0
@@ -265,11 +269,7 @@ 
		     USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0

		     USB3_DP_PCS_EQ_CONFIG1 0x0d 0

		     USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8 0

		     USB3_DP_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x55 0

		     USB3_DP_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x30 0

		     USB3_DP_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x05 0

		     USB3_DP_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x15 0

		     USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x04 0

		     USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0

		     0xffffffff 0xffffffff 0x00>;



		qcom,qmp-phy-reg-offset =

drivers/usb/gadget/configfs.c

+1 −1
Original line number Diff line number Diff line
@@ -1563,7 +1563,7 @@ static const struct usb_gadget_driver configfs_driver_template = { 
	.suspend	= composite_suspend,

	.resume		= composite_resume,



	.max_speed	= USB_SPEED_SUPER,

	.max_speed	= USB_SPEED_SUPER_PLUS,

	.driver = {

		.owner          = THIS_MODULE,

		.name		= "configfs-gadget",