Loading Makefile +1 −1 Original line number Diff line number Diff line # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 14 SUBLEVEL = 22 SUBLEVEL = 23 EXTRAVERSION = NAME = Petit Gorille Loading arch/arm64/kernel/cpufeature.c +4 −2 Original line number Diff line number Diff line Loading @@ -175,9 +175,11 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { }; static const struct arm64_ftr_bits ftr_ctr[] = { ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 29, 1, 1), /* DIC */ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 28, 1, 1), /* IDC */ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 20, 4, 0), /* ERG */ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */ /* * Linux can handle differing I-cache policies. Userspace JITs will Loading arch/arm64/kernel/traps.c +1 −9 Original line number Diff line number Diff line Loading @@ -57,7 +57,7 @@ static const char *handler[]= { "Error" }; int show_unhandled_signals = 1; int show_unhandled_signals = 0; /* * Dump out the contents of some kernel memory nicely... Loading Loading @@ -578,14 +578,6 @@ asmlinkage long do_ni_syscall(struct pt_regs *regs) } #endif if (show_unhandled_signals_ratelimited()) { pr_info("%s[%d]: syscall %d\n", current->comm, task_pid_nr(current), regs->syscallno); dump_instr("", regs); if (user_mode(regs)) __show_regs(regs); } return sys_ni_syscall(); } Loading arch/arm64/mm/proc.S +1 −1 Original line number Diff line number Diff line Loading @@ -201,7 +201,7 @@ ENDPROC(cpu_do_switch_mm) .macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2 adrp \tmp1, empty_zero_page msr ttbr1_el1, \tmp2 msr ttbr1_el1, \tmp1 isb tlbi vmalle1 dsb nsh Loading arch/m32r/Kconfig +2 −2 Original line number Diff line number Diff line Loading @@ -196,8 +196,8 @@ config TIMER_DIVIDE default "128" config CPU_BIG_ENDIAN bool "Generate big endian code" default n bool default !CPU_LITTLE_ENDIAN config CPU_LITTLE_ENDIAN bool "Generate little endian code" Loading Loading
Makefile +1 −1 Original line number Diff line number Diff line # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 14 SUBLEVEL = 22 SUBLEVEL = 23 EXTRAVERSION = NAME = Petit Gorille Loading
arch/arm64/kernel/cpufeature.c +4 −2 Original line number Diff line number Diff line Loading @@ -175,9 +175,11 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { }; static const struct arm64_ftr_bits ftr_ctr[] = { ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RAO */ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 29, 1, 1), /* DIC */ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 28, 1, 1), /* IDC */ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0), /* CWG */ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), /* ERG */ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 20, 4, 0), /* ERG */ ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1), /* DminLine */ /* * Linux can handle differing I-cache policies. Userspace JITs will Loading
arch/arm64/kernel/traps.c +1 −9 Original line number Diff line number Diff line Loading @@ -57,7 +57,7 @@ static const char *handler[]= { "Error" }; int show_unhandled_signals = 1; int show_unhandled_signals = 0; /* * Dump out the contents of some kernel memory nicely... Loading Loading @@ -578,14 +578,6 @@ asmlinkage long do_ni_syscall(struct pt_regs *regs) } #endif if (show_unhandled_signals_ratelimited()) { pr_info("%s[%d]: syscall %d\n", current->comm, task_pid_nr(current), regs->syscallno); dump_instr("", regs); if (user_mode(regs)) __show_regs(regs); } return sys_ni_syscall(); } Loading
arch/arm64/mm/proc.S +1 −1 Original line number Diff line number Diff line Loading @@ -201,7 +201,7 @@ ENDPROC(cpu_do_switch_mm) .macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2 adrp \tmp1, empty_zero_page msr ttbr1_el1, \tmp2 msr ttbr1_el1, \tmp1 isb tlbi vmalle1 dsb nsh Loading
arch/m32r/Kconfig +2 −2 Original line number Diff line number Diff line Loading @@ -196,8 +196,8 @@ config TIMER_DIVIDE default "128" config CPU_BIG_ENDIAN bool "Generate big endian code" default n bool default !CPU_LITTLE_ENDIAN config CPU_LITTLE_ENDIAN bool "Generate little endian code" Loading