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Commit ea7eaa39 authored by Dhananjay Phadke's avatar Dhananjay Phadke Committed by David S. Miller
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netxen: cache align register map table 



Aligning register offset translation table imporves performance
on rx side.

Signed-off-by: default avatarDhananjay Phadke <dhananjay@netxen.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent a92e9e65

drivers/net/netxen/netxen_nic_hw.c

+2 −1
Original line number Diff line number Diff line
@@ -89,7 +89,8 @@ static void __iomem *pci_base_offset(struct netxen_adapter *adapter, 
}



#define CRB_WIN_LOCK_TIMEOUT 100000000

static crb_128M_2M_block_map_t crb_128M_2M_map[64] = {

static crb_128M_2M_block_map_t

crb_128M_2M_map[64] __cacheline_aligned_in_smp = {

    {{{0, 0,         0,         0} } },		/* 0: PCI */

    {{{1, 0x0100000, 0x0102000, 0x120000},	/* 1: PCIE */

	  {1, 0x0110000, 0x0120000, 0x130000},