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Commit e9b37ae2 authored by Kyle Yan's avatar Kyle Yan
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ARM: dts: msm: Add device nodes for NPU devfreq devices on SDM855



Add initial devfreq nodes for NPU hardware monitors.

Change-Id: I67ffedef458688ad2f2c74c99c1a3a6b6779c3ef
Signed-off-by: default avatarKyle Yan <kyan@codeaurora.org>
parent 98cd82ec
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+29 −0
Original line number Diff line number Diff line
@@ -961,6 +961,35 @@
		qcom,count-unit = <0x10000>;
	};

	npu_npu_ddr_bw: qcom,npu-npu-ddr-bw {
		compatible = "qcom,devbw";
		governor = "performance";
		qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>;
		qcom,bw-tbl =
			< MHZ_TO_MBPS( 200, 4) >, /* 762 MB/s */
			< MHZ_TO_MBPS( 300, 4) >, /* 1144 MB/s */
			< MHZ_TO_MBPS( 451, 4) >, /* 1720 MB/s */
			< MHZ_TO_MBPS( 547, 4) >, /* 2086 MB/s */
			< MHZ_TO_MBPS( 681, 4) >, /* 2597 MB/s */
			< MHZ_TO_MBPS( 768, 4) >, /* 2929 MB/s */
			< MHZ_TO_MBPS(1017, 4) >, /* 3879 MB/s */
			< MHZ_TO_MBPS(1296, 4) >, /* 4943 MB/s */
			< MHZ_TO_MBPS(1555, 4) >, /* 5931 MB/s */
			< MHZ_TO_MBPS(1804, 4) >, /* 6881 MB/s */
			< MHZ_TO_MBPS(2092, 4) >; /* 7980 MB/s */
	};

	npu_npu_ddr_bwmon: qcom,npu-npu-ddr-bwmon@9960300 {
		compatible = "qcom,bimc-bwmon4";
		reg = <0x9960300 0x300>, <0x9960200 0x200>;
		reg-names = "base", "global_base";
		interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
		qcom,mport = <0>;
		qcom,hw-timer-hz = <19200000>;
		qcom,target-dev = <&npu_npu_ddr_bw>;
		qcom,count-unit = <0x10000>;
	};

	cdsp_cdsp_l3_lat: qcom,cdsp-cdsp-l3-lat {
		compatible = "devfreq-simple-dev";
		clock-names = "devfreq_clk";